Merge branch 'main' of https://github.com/ucb-bar/radiance into main

radiance.mk

@@ -9,7 +9,7 @@
 RADPIE_SRC_DIR = $(base_dir)/generators/radiance/radpie
 RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release
 
-EXTRA_SIM_REQS += radpie
+# EXTRA_SIM_REQS += radpie
 EXTRA_SIM_LDFLAGS += -L$(RADPIE_BUILD_DIR) -Wl,-rpath,$(RADPIE_BUILD_DIR) -lradpie
 EXTRA_SIM_PREPROC_DEFINES += \
 	+define+SIMULATION \

src/main/scala/radiance/memory/Coalescing.scala

@@ -344,13 +344,18 @@ class SourceGenerator[T <: Data](
   io.id.valid := (if (ignoreInUse) true.B else !lowestFreeRow.valid)
   io.id.bits := lowestFree
   when(io.gen && io.id.valid /* fire */ ) {
-    occupancyTable(io.id.bits).valid := true.B // mark in use
-    if (metadata.isDefined) {
-      occupancyTable(io.id.bits).meta := io.meta
+    // handle reclaim at the same cycle, e.g. for 0-latency D channel response
+    when (!io.reclaim.valid || io.reclaim.bits =/= io.id.bits) {
+      occupancyTable(io.id.bits).valid := true.B // mark in use
+      if (metadata.isDefined) {
+        occupancyTable(io.id.bits).meta := io.meta
+      }
     }
   }
   when(io.reclaim.valid) {
     // @perf: would this require multiple write ports?
+    // NOTE: this does not seem sufficient to handle same-cycle gen-reclaimon
+    // its own
     occupancyTable(io.reclaim.bits).valid := false.B // mark freed
   }
   io.peek := {

src/main/scala/radiance/tile/RadianceCluster.scala

@@ -405,7 +405,6 @@ class RadianceClusterModuleImp(outer: RadianceCluster) extends ClusterModuleImp(
       }
       // must empty backup before filling data pipe
       assert(!(sram_read_backup_reg.valid && data_pipe.valid && data_pipe_in.fire))
-      assert(data_pipe_in.valid === data_pipe_in.fire)
 
       r_node.d.bits := r_edge.AccessAck(
         Mux(r_node.d.valid, metadata_pipe.bits.source, 0.U),

src/main/scala/radiance/tile/RadianceTile.scala

@@ -325,8 +325,8 @@ class RadianceTile private (
   }
 
   // Barrier synchronization node
-  // FIXME: hardcoded params
-  val numBarriers = 8
+  // FIXME: hardcoded param eq
+  val numBarriers = numWarps
   def barrierIdBits = log2Ceil(numBarriers)
   val barrierMasterNode = BarrierMasterNode(barrierIdBits)
 
@@ -570,7 +570,7 @@ class RadianceTileModuleImp(outer: RadianceTile)
 
       // make connection:
       // VortexBundle <--> sourceId filter <--> VortexTLAdapter <--> dmemNodes
-      // 
+      //
       // Chisel doesn't support 2-D array in BlackBox interface to Verilog, so
       // need to flatten everything.
       dmemTLAdapters.zipWithIndex.foreach {