From 2a3a9c844f62b1f31653582b23b693a0a1a52bb1 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 29 Mar 2024 12:27:53 -0700 Subject: [PATCH 1/5] Bump vortex --- src/main/resources/vsrc/vortex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/resources/vsrc/vortex b/src/main/resources/vsrc/vortex index 3718a57..62c7d1f 160000 --- a/src/main/resources/vsrc/vortex +++ b/src/main/resources/vsrc/vortex @@ -1 +1 @@ -Subproject commit 3718a579370807dfb57980ec2c45491d0138133d +Subproject commit 62c7d1f4cf8e97fd3f0ce2e75bb1af7c821c2c19 From 9e877b0efc603a7910b34edc76515e852f4fac83 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 29 Mar 2024 12:28:27 -0700 Subject: [PATCH 2/5] Set numBarriers == numWarps still requires manually updating radiance.mk --- src/main/scala/radiance/tile/RadianceTile.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/radiance/tile/RadianceTile.scala b/src/main/scala/radiance/tile/RadianceTile.scala index 31212df..80fad66 100644 --- a/src/main/scala/radiance/tile/RadianceTile.scala +++ b/src/main/scala/radiance/tile/RadianceTile.scala @@ -325,8 +325,8 @@ class RadianceTile private ( } // Barrier synchronization node - // FIXME: hardcoded params - val numBarriers = 8 + // FIXME: hardcoded param eq + val numBarriers = numWarps def barrierIdBits = log2Ceil(numBarriers) val barrierMasterNode = BarrierMasterNode(barrierIdBits) @@ -570,7 +570,7 @@ class RadianceTileModuleImp(outer: RadianceTile) // make connection: // VortexBundle <--> sourceId filter <--> VortexTLAdapter <--> dmemNodes - // + // // Chisel doesn't support 2-D array in BlackBox interface to Verilog, so // need to flatten everything. dmemTLAdapters.zipWithIndex.foreach { From 48c3a5692ed1a055af00ef353a6d539299c8ab29 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 29 Mar 2024 12:49:27 -0700 Subject: [PATCH 3/5] Remove radpie from EXTRA_SIM_REQS Cargo causes VCS rebuild without RTL change which makes param sweep runs annoying. --- radiance.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radiance.mk b/radiance.mk index 48dd596..f286092 100644 --- a/radiance.mk +++ b/radiance.mk @@ -9,7 +9,7 @@ RADPIE_SRC_DIR = $(base_dir)/generators/radiance/radpie RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release -EXTRA_SIM_REQS += radpie +# EXTRA_SIM_REQS += radpie EXTRA_SIM_LDFLAGS += -L$(RADPIE_BUILD_DIR) -Wl,-rpath,$(RADPIE_BUILD_DIR) -lradpie EXTRA_SIM_PREPROC_DEFINES += \ +define+SIMULATION \ From 47c7eacafd2eb8a02d5c7ed65a8bbaca746b2ee3 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Mon, 8 Apr 2024 18:23:39 -0700 Subject: [PATCH 4/5] SourceGen: Handle gen and claim at the same cycle This is possible for 0-latency response on the D channel. --- src/main/scala/radiance/memory/Coalescing.scala | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/main/scala/radiance/memory/Coalescing.scala b/src/main/scala/radiance/memory/Coalescing.scala index 338c36c..13a01a5 100644 --- a/src/main/scala/radiance/memory/Coalescing.scala +++ b/src/main/scala/radiance/memory/Coalescing.scala @@ -344,13 +344,18 @@ class SourceGenerator[T <: Data]( io.id.valid := (if (ignoreInUse) true.B else !lowestFreeRow.valid) io.id.bits := lowestFree when(io.gen && io.id.valid /* fire */ ) { - occupancyTable(io.id.bits).valid := true.B // mark in use - if (metadata.isDefined) { - occupancyTable(io.id.bits).meta := io.meta + // handle reclaim at the same cycle, e.g. for 0-latency D channel response + when (!io.reclaim.valid || io.reclaim.bits =/= io.id.bits) { + occupancyTable(io.id.bits).valid := true.B // mark in use + if (metadata.isDefined) { + occupancyTable(io.id.bits).meta := io.meta + } } } when(io.reclaim.valid) { // @perf: would this require multiple write ports? + // NOTE: this does not seem sufficient to handle same-cycle gen-reclaimon + // its own occupancyTable(io.reclaim.bits).valid := false.B // mark freed } io.peek := { From 675624e9c80caf38f1af3eb38ef95baccf084074 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Mon, 8 Apr 2024 18:24:38 -0700 Subject: [PATCH 5/5] Remove obsolete assertion on cluster SRAM --- src/main/scala/radiance/tile/RadianceCluster.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/src/main/scala/radiance/tile/RadianceCluster.scala b/src/main/scala/radiance/tile/RadianceCluster.scala index 4ce2412..cf39016 100644 --- a/src/main/scala/radiance/tile/RadianceCluster.scala +++ b/src/main/scala/radiance/tile/RadianceCluster.scala @@ -358,7 +358,6 @@ class RadianceClusterModuleImp(outer: RadianceCluster) extends ClusterModuleImp( sram_read_backup_reg.valid := false.B } assert(!(sram_read_backup_reg.valid && data_pipe.valid && data_pipe_in.fire)) // must empty backup before filling data pipe - assert(data_pipe_in.valid === data_pipe_in.fire) r_node.d.bits := r_edge.AccessAck( Mux(r_node.d.valid, metadata_pipe.bits.source, 0.U),