From df26764fc07ca46bf7d44e20311a926dbd041402 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 23 Jan 2024 22:14:15 -0800 Subject: [PATCH] Reduce sharedmem addr mapping to 8KB smem size is set to 16KB, and reqs exceeding this range gets filtered out of smemNodes from inside the core. Lower 8KB is mapped to smem banks, and upper 8KB is reserved for MMIO. --- src/main/scala/radiance/tile/VortexTile.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/radiance/tile/VortexTile.scala b/src/main/scala/radiance/tile/VortexTile.scala index 64769e1..068b82b 100644 --- a/src/main/scala/radiance/tile/VortexTile.scala +++ b/src/main/scala/radiance/tile/VortexTile.scala @@ -326,7 +326,7 @@ class VortexTile private ( // base for bank 1: ff...000000|01|00 // mask for bank 1; 00...111111|00|11 val base = 0xff000000L | (bankId * 4 /*wordSize*/ ) - val mask = 0x00ffffffL ^ ((numLsuLanes - 1) * 4 /*wordSize*/ ) + val mask = 0x00001fffL ^ ((numLsuLanes - 1) * 4 /*wordSize*/ ) LazyModule(new TLRAM(AddressSet(base, mask), beatBytes = 4 /*wordSize*/ )) } // smem lanes-to-banks crossbar