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Fix verilog lint error

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Hansung Kim
2023-04-10 20:37:26 -07:00
parent b53711965e
commit dca52ace0b
1 changed files with 1 additions and 1 deletions
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2
src/main/resources/vsrc/SimMemTrace.v
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@@ -41,7 +41,7 @@ module SimMemTrace #(parameter FILENAME = "undefined", NUM_LANES = 4) (
longint __in_address[NUM_LANES-1:0]; longint __in_address[NUM_LANES-1:0];
bit __in_is_store[NUM_LANES-1:0]; bit __in_is_store[NUM_LANES-1:0];
int __in_store_mask [NUM_LANES-1:0]; logic [`MASK_WIDTH-1:0] __in_store_mask [NUM_LANES-1:0];
longint __in_data[NUM_LANES-1:0]; longint __in_data[NUM_LANES-1:0];
bit __in_finished; bit __in_finished;