From dca52ace0be76e04d3ee95f1a852d1ca36fa3bd7 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Mon, 10 Apr 2023 20:37:26 -0700 Subject: [PATCH] Fix verilog lint error --- src/main/resources/vsrc/SimMemTrace.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/resources/vsrc/SimMemTrace.v b/src/main/resources/vsrc/SimMemTrace.v index 9a91848..d5c5584 100644 --- a/src/main/resources/vsrc/SimMemTrace.v +++ b/src/main/resources/vsrc/SimMemTrace.v @@ -41,7 +41,7 @@ module SimMemTrace #(parameter FILENAME = "undefined", NUM_LANES = 4) ( longint __in_address[NUM_LANES-1:0]; bit __in_is_store[NUM_LANES-1:0]; - int __in_store_mask [NUM_LANES-1:0]; + logic [`MASK_WIDTH-1:0] __in_store_mask [NUM_LANES-1:0]; longint __in_data[NUM_LANES-1:0]; bit __in_finished;