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Add back LSUQ_SIZE logic

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Hansung Kim
2024-05-07 16:17:21 -07:00
parent 2bde4fa6ed
commit a0c7ce93d7
1 changed files with 0 additions and 1 deletions
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src/main/scala/radiance/tile/RadianceTile.scala
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@@ -193,7 +193,6 @@ class RadianceTile private (
} }
val imemTagWidth = UUID_WIDTH + NW_WIDTH val imemTagWidth = UUID_WIDTH + NW_WIDTH
// val LSUQ_SIZE = p(SIMTCoreKey).get.nSrcIds
require(numWarps >= numLsuLanes, require(numWarps >= numLsuLanes,
s"Vortex core requires numWarps (${numWarps}) >= numLsuLanes (${numLsuLanes})") s"Vortex core requires numWarps (${numWarps}) >= numLsuLanes (${numLsuLanes})")
val LSUQ_SIZE = 8 * (numCoreLanes / numLsuLanes) val LSUQ_SIZE = 8 * (numCoreLanes / numLsuLanes)