From a0c7ce93d7472cd01eee7fd1408474e4fb45be74 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Tue, 7 May 2024 16:17:21 -0700
Subject: [PATCH] Add back LSUQ_SIZE logic

---
 src/main/scala/radiance/tile/RadianceTile.scala | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/main/scala/radiance/tile/RadianceTile.scala b/src/main/scala/radiance/tile/RadianceTile.scala
index 6b0e842..534da44 100644
--- a/src/main/scala/radiance/tile/RadianceTile.scala
+++ b/src/main/scala/radiance/tile/RadianceTile.scala
@@ -193,7 +193,6 @@ class RadianceTile private (
   }
   val imemTagWidth = UUID_WIDTH + NW_WIDTH
 
-  // val LSUQ_SIZE = p(SIMTCoreKey).get.nSrcIds
   require(numWarps >= numLsuLanes,
           s"Vortex core requires numWarps (${numWarps}) >= numLsuLanes (${numLsuLanes})")
   val LSUQ_SIZE = 8 * (numCoreLanes / numLsuLanes)