Add back LSUQ_SIZE logic

2024-05-07 16:17:21 -07:00
parent 2bde4fa6ed
commit a0c7ce93d7
1 changed files with 0 additions and 1 deletions
--- a/src/main/scala/radiance/tile/RadianceTile.scala
+++ b/src/main/scala/radiance/tile/RadianceTile.scala
@@ -193,7 +193,6 @@ class RadianceTile private (
  }
  val imemTagWidth = UUID_WIDTH + NW_WIDTH

-  // val LSUQ_SIZE = p(SIMTCoreKey).get.nSrcIds
  require(numWarps >= numLsuLanes,
          s"Vortex core requires numWarps (${numWarps}) >= numLsuLanes (${numLsuLanes})")
  val LSUQ_SIZE = 8 * (numCoreLanes / numLsuLanes)