From 7e405b53559bf88c38f6c12782f4086c93a7176f Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Thu, 20 Apr 2023 21:11:12 -0700 Subject: [PATCH] Re-enable coalescer in TLRAMCoalescerLoggerTest Now that the driver and logger are working (kinda). --- src/main/scala/tilelink/Coalescing.scala | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 4c81b50..ecb8668 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -593,7 +593,7 @@ class MemTraceDriver(numLanes: Int = 4, filename: String = "vecadd.core1.thread4 val clientParam = Seq( TLMasterParameters.v1( name = "MemTraceDriver" + i.toString, - sourceId = IdRange(0, 0x1000) + sourceId = IdRange(0, 0x10) // visibility = Seq(AddressSet(0x0000, 0xffffff)) ) ) @@ -972,10 +972,10 @@ object TracePrintf { class TLRAMCoalescerLogger(implicit p: Parameters) extends LazyModule { // TODO: use parameters for numLanes val numLanes = 4 - // val coal = LazyModule(new CoalescingUnit(numLanes)) + val coal = LazyModule(new CoalescingUnit(numLanes)) val driver = LazyModule(new MemTraceDriver(numLanes)) - val logger = LazyModule(new MemTraceLogger(numLanes)) - val rams = Seq.fill(numLanes)( // +1 for coalesced edge + val logger = LazyModule(new MemTraceLogger(numLanes + 1)) + val rams = Seq.fill(numLanes + 1)( // +1 for coalesced edge LazyModule( // NOTE: beatBytes here sets the data bitwidth of the upstream TileLink // edges globally, by way of Diplomacy communicating the TL slave @@ -984,8 +984,7 @@ class TLRAMCoalescerLogger(implicit p: Parameters) extends LazyModule { ) ) - // logger.node :=* coal.node :=* driver.node - logger.node :=* driver.node + logger.node :=* coal.node :=* driver.node rams.foreach { r => r.node := logger.node } lazy val module = new Impl