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Fix module imports after rocket-chip bump

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Hansung Kim
2024-06-27 17:17:27 -07:00
parent e1342e431c
commit 7aad800a2d
5 changed files with 11 additions and 8 deletions
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2
src/main/scala/radiance/tile/AccNode.scala
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@@ -2,7 +2,7 @@ package radiance.tile;
import chisel3._
import chisel3.experimental.SourceInfo
import chisel3.util._
import freechips.rocketchip.diplomacy.BigIntHexContext
import freechips.rocketchip.resources.BigIntHexContext
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._

3
src/main/scala/radiance/tile/FuzzerTile.scala
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@@ -5,7 +5,8 @@ package radiance.tile
import chisel3._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, ClockCrossingType}
import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule}
import freechips.rocketchip.prci.ClockCrossingType
import freechips.rocketchip.rocket._
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._

5
src/main/scala/radiance/tile/GemminiTile.scala
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@@ -8,8 +8,9 @@ import chisel3.util._
import chisel3.experimental.BundleLiterals._
import org.chipsalliance.diplomacy.DisableMonitors
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, BigIntHexContext, ClockCrossingType, SimpleDevice}
import freechips.rocketchip.prci.ClockSinkParameters
import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice}
import freechips.rocketchip.resources.BigIntHexContext
import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters}
import freechips.rocketchip.regmapper.RegField
import freechips.rocketchip.rocket._
import freechips.rocketchip.subsystem.{CanAttachTile, HierarchicalElementCrossingParamsLike, RocketCrossingParams}

7
src/main/scala/radiance/tile/RadianceCluster.scala
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@@ -5,11 +5,12 @@ package radiance.tile
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy.{AddressSet, BigIntHexContext, BufferParams, ClockCrossingType, TransferSizes}
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.prci.ClockSinkParameters
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, TransferSizes}
import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters}
import freechips.rocketchip.resources.BigIntHexContext
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import org.chipsalliance.diplomacy.lazymodule._
import gemmini._
import midas.targetutils.SynthesizePrintf
import org.chipsalliance.cde.config.Parameters

2
src/main/scala/radiance/tile/RadianceTile.scala
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@@ -9,7 +9,7 @@ import chisel3.util._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.diplomacy.lazymodule.LazyModule
import freechips.rocketchip.prci.ClockSinkParameters
import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters, RationalCrossing}
import freechips.rocketchip.regmapper.RegField
import freechips.rocketchip.rocket._
import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike