diff --git a/src/main/scala/radiance/tile/AccNode.scala b/src/main/scala/radiance/tile/AccNode.scala
index 31a37d4..cc3e6f2 100644
--- a/src/main/scala/radiance/tile/AccNode.scala
+++ b/src/main/scala/radiance/tile/AccNode.scala
@@ -2,7 +2,7 @@ package radiance.tile;
 import chisel3._
 import chisel3.experimental.SourceInfo
 import chisel3.util._
-import freechips.rocketchip.diplomacy.BigIntHexContext
+import freechips.rocketchip.resources.BigIntHexContext
 import org.chipsalliance.cde.config.Parameters
 import org.chipsalliance.diplomacy._
 import org.chipsalliance.diplomacy.nodes._
diff --git a/src/main/scala/radiance/tile/FuzzerTile.scala b/src/main/scala/radiance/tile/FuzzerTile.scala
index c139744..138b0f8 100644
--- a/src/main/scala/radiance/tile/FuzzerTile.scala
+++ b/src/main/scala/radiance/tile/FuzzerTile.scala
@@ -5,7 +5,8 @@ package radiance.tile
 
 import chisel3._
 import org.chipsalliance.cde.config.{Parameters}
-import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, ClockCrossingType}
+import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule}
+import freechips.rocketchip.prci.ClockCrossingType
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
diff --git a/src/main/scala/radiance/tile/GemminiTile.scala b/src/main/scala/radiance/tile/GemminiTile.scala
index 82dd90a..9b32470 100644
--- a/src/main/scala/radiance/tile/GemminiTile.scala
+++ b/src/main/scala/radiance/tile/GemminiTile.scala
@@ -8,8 +8,9 @@ import chisel3.util._
 import chisel3.experimental.BundleLiterals._
 import org.chipsalliance.diplomacy.DisableMonitors
 import org.chipsalliance.diplomacy.lazymodule._
-import freechips.rocketchip.diplomacy.{AddressSet, BigIntHexContext, ClockCrossingType, SimpleDevice}
-import freechips.rocketchip.prci.ClockSinkParameters
+import freechips.rocketchip.diplomacy.{AddressSet, SimpleDevice}
+import freechips.rocketchip.resources.BigIntHexContext
+import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters}
 import freechips.rocketchip.regmapper.RegField
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.subsystem.{CanAttachTile, HierarchicalElementCrossingParamsLike, RocketCrossingParams}
diff --git a/src/main/scala/radiance/tile/RadianceCluster.scala b/src/main/scala/radiance/tile/RadianceCluster.scala
index 2e919e5..ec833a5 100644
--- a/src/main/scala/radiance/tile/RadianceCluster.scala
+++ b/src/main/scala/radiance/tile/RadianceCluster.scala
@@ -5,11 +5,12 @@ package radiance.tile
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.diplomacy.{AddressSet, BigIntHexContext, BufferParams, ClockCrossingType, TransferSizes}
-import org.chipsalliance.diplomacy.lazymodule._
-import freechips.rocketchip.prci.ClockSinkParameters
+import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, TransferSizes}
+import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters}
+import freechips.rocketchip.resources.BigIntHexContext
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink._
+import org.chipsalliance.diplomacy.lazymodule._
 import gemmini._
 import midas.targetutils.SynthesizePrintf
 import org.chipsalliance.cde.config.Parameters
diff --git a/src/main/scala/radiance/tile/RadianceTile.scala b/src/main/scala/radiance/tile/RadianceTile.scala
index df3d3e6..3e8b666 100644
--- a/src/main/scala/radiance/tile/RadianceTile.scala
+++ b/src/main/scala/radiance/tile/RadianceTile.scala
@@ -9,7 +9,7 @@ import chisel3.util._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import org.chipsalliance.diplomacy.lazymodule.LazyModule
-import freechips.rocketchip.prci.ClockSinkParameters
+import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters, RationalCrossing}
 import freechips.rocketchip.regmapper.RegField
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.subsystem.HierarchicalElementCrossingParamsLike