From 57874a564e0e06d3273551f25e0438bfec897566 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Wed, 12 Apr 2023 14:23:17 -0700
Subject: [PATCH] Set TL size according to trace from driver

Mask will be set accordingly by the TL generator methods (Get/Put).
---
 src/main/scala/tilelink/Coalescing.scala | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index d6fb6ff..32a7e0c 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -656,21 +656,29 @@ class MemTraceDriverImp(outer: MemTraceDriver, numLanes: Int, traceFile: String)
   (outer.laneNodes zip laneReqs).foreach { case (node, req) =>
     val (tlOut, edge) = node.out(0)
 
-    val size = 4.U // TODO: get proper size from the trace
     val (plegal, pbits) = edge.Put(
       fromSource = sourceIdCounter,
       toAddress = hashToValidPhyAddr(req.address),
-      lgSize = Log2(size),
+      lgSize = req.size, // trace line already holds log2(size)
       data = req.data
     )
     val (glegal, gbits) = edge.Get(
       fromSource = sourceIdCounter,
       toAddress = hashToValidPhyAddr(req.address),
-      lgSize = Log2(size)
+      lgSize = req.size
     )
     val legal = Mux(req.is_store, plegal, glegal)
     val bits = Mux(req.is_store, pbits, gbits)
 
+    when(tlOut.a.valid) {
+      printf(
+        "Get(): addr=%x, size=%x, mask=%x\n",
+        tlOut.a.bits.address,
+        tlOut.a.bits.size,
+        tlOut.a.bits.mask
+      );
+    }
+
     assert(legal, "illegal TL req gen")
     tlOut.a.valid := req.valid
     tlOut.a.bits := bits
@@ -772,8 +780,8 @@ class MemTraceLogger(numLanes: Int = 4, filename: String = "vecadd.core1.thread4
       req.address := tlIn.a.bits.address
       req.data := tlIn.a.bits.data
       req.is_store := false.B
-      when(tlIn.a.bits.opcode === 0.U || tlIn.a.bits.opcode === 1.U) {
-        // 0: PutFullData, 1: PutPartialData
+      when(tlIn.a.bits.opcode === 0.U) {
+        // 0: PutFullData, 1: PutPartialData but we don't support it
         req.is_store := true.B
       }.elsewhen(tlIn.a.bits.opcode === 4.U) {
         // 4: Get
@@ -784,10 +792,6 @@ class MemTraceLogger(numLanes: Int = 4, filename: String = "vecadd.core1.thread4
       }
       req.size := tlIn.a.bits.size
 
-      when(req.valid) {
-        printf("======== MemTraceLogger: req.size=%d\n", req.size)
-      }
-
     // responses on TL D channel
     // TODO
     }