Log both request and response in trace logger
Inside DPI code, have a vector of unique_ptrs that act as handles to multiple different trace logger instances. Each logger instance is instantiated in a single instance of the Verilog module, and multiple of these Verilog modules may be instantiated in the Chisel module (see simReq and simResp in MemTraceLogger).
This commit is contained in:
Hansung Kim
@@ -747,7 +747,11 @@ class SimMemTrace(filename: String, numLanes: Int)
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addResource("/csrc/SimMemTrace.h")
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}
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class MemTraceLogger(numLanes: Int = 4, filename: String = "vecadd.core1.thread4.out.trace")(implicit
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class MemTraceLogger(
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numLanes: Int = 4,
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reqFilename: String = "vecadd.core1.thread4.logger.req.trace",
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respFilename: String = "vecadd.core1.thread4.logger.resp.trace"
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)(implicit
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p: Parameters
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) extends LazyModule {
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val node = TLIdentityNode()
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@@ -775,98 +779,152 @@ class MemTraceLogger(numLanes: Int = 4, filename: String = "vecadd.core1.thread4
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lazy val module = new Impl
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class Impl extends LazyModuleImp(this) {
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val sim = Module(new SimMemTraceLogger(filename, numLanes))
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sim.io.clock := clock
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sim.io.reset := reset.asBool
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val simReq = Module(new SimMemTraceLogger(false, reqFilename, numLanes))
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val simResp = Module(new SimMemTraceLogger(true, respFilename, numLanes))
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simReq.io.clock := clock
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simReq.io.reset := reset.asBool
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simResp.io.clock := clock
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simResp.io.reset := reset.asBool
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val laneReqs = Wire(Vec(numLanes, new TraceReq))
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val laneResps = Wire(Vec(numLanes, new TraceReq))
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assert(
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numLanes == node.in.length,
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"`numLanes` does not match the number of TL edges connected to the MemTraceLogger"
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)
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def tlAOpcodeIsStore(opcode: UInt): Bool = {
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// 0: PutFullData, 1: PutPartialData but we don't support it
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// 4: Get
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assert(opcode === 0.U || opcode === 4.U, "unhandled TL A opcode found")
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opcode === 0.U
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}
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def tlDOpcodeIsStore(opcode: UInt): Bool = {
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// 0: AccessAck (Put), 1: AccessAckData (Get or Atomic)
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// See Table 13 of spec 1.8.1
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assert(opcode === 0.U || opcode === 1.U, "unhandled TL D opcode found")
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opcode === 0.U
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}
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// snoop on the TileLink edges to log traffic
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((node.in zip node.out) zip laneReqs).foreach { case (((tlIn, _), (tlOut, _)), req) =>
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tlOut.a <> tlIn.a
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tlIn.d <> tlOut.d
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((node.in zip node.out) zip (laneReqs zip laneResps)).foreach {
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case (((tlIn, _), (tlOut, _)), (req, resp)) =>
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tlOut.a <> tlIn.a
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tlIn.d <> tlOut.d
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// requests on TL A channel
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//
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req.valid := tlIn.a.valid
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req.size := tlIn.a.bits.size
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def tlOpcodeIsStore(opcode: UInt): Bool = {
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// 0: PutFullData, 1: PutPartialData but we don't support it
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// 4: Get
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assert(opcode === 0.U || opcode === 4.U, "unhandled TL opcode found in MemTraceLogger")
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tlIn.a.bits.opcode === 0.U
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}
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req.is_store := tlOpcodeIsStore(tlIn.a.bits.opcode)
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// TL always carries the exact unaligned address that the client
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// originally requested, so no postprocessing required
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req.address := tlIn.a.bits.address
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// requests on TL A channel
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//
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req.valid := tlIn.a.valid
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req.size := tlIn.a.bits.size
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req.is_store := tlAOpcodeIsStore(tlIn.a.bits.opcode)
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// TL always carries the exact unaligned address that the client
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// originally requested, so no postprocessing required
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req.address := tlIn.a.bits.address
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// TL data
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//
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// When tlIn.a.bits.size is smaller than the data bus width, need to
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// figure out which byte lanes we actually accessed so that
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// we can write that to the memory trace.
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// See Section 4.5 Byte Lanes in spec 1.8.1
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// TL data
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//
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// When tlIn.a.bits.size is smaller than the data bus width, need to
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// figure out which byte lanes we actually accessed so that
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// we can write that to the memory trace.
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// See Section 4.5 Byte Lanes in spec 1.8.1
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// This assert only holds true for PutFullData and not PutPartialData,
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// where HIGH bits in the mask may not be contiguous.
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assert(
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PopCount(tlIn.a.bits.mask) === (1.U << tlIn.a.bits.size),
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"mask HIGH bits do not match the TL size. This should have been handled by the TL generator logic"
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)
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val trailingZerosInMask = trailingZeros(tlIn.a.bits.mask)
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val mask = ~((~0.U) << (trailingZerosInMask * 8.U))
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req.data := mask & (tlIn.a.bits.data >> (trailingZerosInMask * 8.U))
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when(req.valid) {
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TracePrintf(
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"MemTraceLogger",
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tlIn.a.bits.address,
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tlIn.a.bits.size,
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tlIn.a.bits.mask,
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req.is_store,
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tlIn.a.bits.data,
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req.data
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// This assert only holds true for PutFullData and not PutPartialData,
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// where HIGH bits in the mask may not be contiguous.
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assert(
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PopCount(tlIn.a.bits.mask) === (1.U << tlIn.a.bits.size),
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"mask HIGH bits do not match the TL size. This should have been handled by the TL generator logic"
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)
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}
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val trailingZerosInMask = trailingZeros(tlIn.a.bits.mask)
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val mask = ~((~0.U) << (trailingZerosInMask * 8.U))
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req.data := mask & (tlIn.a.bits.data >> (trailingZerosInMask * 8.U))
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// responses on TL D channel
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// TODO
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when(req.valid) {
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TracePrintf(
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"MemTraceLogger",
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tlIn.a.bits.address,
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tlIn.a.bits.size,
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tlIn.a.bits.mask,
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req.is_store,
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tlIn.a.bits.data,
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req.data
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)
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}
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// responses on TL D channel
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//
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resp.valid := tlOut.d.valid
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resp.size := tlOut.d.bits.size
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resp.is_store := tlDOpcodeIsStore(tlOut.d.bits.opcode)
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// NOTE: TL D channel doesn't carry address nor mask, so there's no easy
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// way to figure out which bytes the master actually use. Since we
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// don't care too much about addresses in the trace anyway, just store
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// the entire bits.
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resp.address := 0.U
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resp.data := tlOut.d.bits.data
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}
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// clunky workaround of the fact that Chisel doesn't allow partial
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// assignment to a bitfield range of a wide signal.
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val laneValid = Wire(Vec(numLanes, Bool()))
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val laneAddress = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).address)))
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val laneIsStore = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).is_store)))
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val laneSize = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).size)))
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val laneData = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).data)))
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laneReqs.zipWithIndex.foreach { case (req, i) =>
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laneValid(i) := req.valid
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laneAddress(i) := req.address
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laneIsStore(i) := req.is_store
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laneSize(i) := req.size
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laneData(i) := req.data
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def flattenTrace(traceLogIO: Bundle with HasTraceReq, perLane: Vec[TraceReq]) = {
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val laneValid = Wire(Vec(numLanes, Bool()))
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val laneAddress = Wire(Vec(numLanes, chiselTypeOf(perLane(0).address)))
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val laneIsStore = Wire(Vec(numLanes, chiselTypeOf(perLane(0).is_store)))
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val laneSize = Wire(Vec(numLanes, chiselTypeOf(perLane(0).size)))
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val laneData = Wire(Vec(numLanes, chiselTypeOf(perLane(0).data)))
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perLane.zipWithIndex.foreach { case (req, i) =>
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laneValid(i) := req.valid
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laneAddress(i) := req.address
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laneIsStore(i) := req.is_store
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laneSize(i) := req.size
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laneData(i) := req.data
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}
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// flatten per-lane signals to the Verilog blackbox input
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traceLogIO.valid := laneValid.asUInt
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traceLogIO.address := laneAddress.asUInt
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traceLogIO.is_store := laneIsStore.asUInt
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traceLogIO.size := laneSize.asUInt
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traceLogIO.data := laneData.asUInt
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}
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// flatten per-lane signals to the Verilog blackbox input
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sim.io.trace_log.valid := laneValid.asUInt
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sim.io.trace_log.address := laneAddress.asUInt
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sim.io.trace_log.is_store := laneIsStore.asUInt
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sim.io.trace_log.size := laneSize.asUInt
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sim.io.trace_log.data := laneData.asUInt
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assert(sim.io.trace_log.ready === true.B, "MemTraceLogger is expected to be always ready")
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flattenTrace(simReq.io.trace_log, laneReqs)
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flattenTrace(simResp.io.trace_log, laneResps)
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assert(simReq.io.trace_log.ready === true.B, "MemTraceLogger is expected to be always ready")
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assert(simResp.io.trace_log.ready === true.B, "MemTraceLogger is expected to be always ready")
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// val laneValid = Wire(Vec(numLanes, Bool()))
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// val laneAddress = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).address)))
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// val laneIsStore = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).is_store)))
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// val laneSize = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).size)))
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// val laneData = Wire(Vec(numLanes, chiselTypeOf(laneReqs(0).data)))
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// laneReqs.zipWithIndex.foreach { case (req, i) =>
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// laneValid(i) := req.valid
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// laneAddress(i) := req.address
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// laneIsStore(i) := req.is_store
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// laneSize(i) := req.size
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// laneData(i) := req.data
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// }
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// // flatten per-lane signals to the Verilog blackbox input
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// simReq.io.trace_log.valid := laneValid.asUInt
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// simReq.io.trace_log.address := laneAddress.asUInt
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// simReq.io.trace_log.is_store := laneIsStore.asUInt
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// simReq.io.trace_log.size := laneSize.asUInt
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// simReq.io.trace_log.data := laneData.asUInt
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}
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}
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class SimMemTraceLogger(filename: String, numLanes: Int)
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// MemTraceLogger is bidirectional. The DPI module tells itself if it's logging
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// the request stream or the response stream by `isResponse`. This distinction
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// is needed because the response trace file will not contain certain columns
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// such as address.
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class SimMemTraceLogger(isResponse: Boolean, filename: String, numLanes: Int)
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extends BlackBox(
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Map("FILENAME" -> filename, "NUM_LANES" -> numLanes)
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Map(
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"IS_RESPONSE" -> (if (isResponse) 1 else 0),
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"FILENAME" -> filename,
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"NUM_LANES" -> numLanes
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)
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)
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with HasBlackBoxResource {
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val io = IO(new Bundle {
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