Add synthesizable unit test for tensor

This commit is contained in:
Hansung Kim
2024-10-14 19:47:00 -07:00
parent 327615e330
commit 3165108c8b
2 changed files with 62 additions and 7 deletions

View File

@@ -5,6 +5,8 @@ package radiance.core
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.unittest.UnitTest
case class TensorTilingParams( case class TensorTilingParams(
// Dimension of the SMEM tile // Dimension of the SMEM tile
@@ -62,7 +64,7 @@ class TensorCoreDecoupled(
// TODO: just transition every cycle for now // TODO: just transition every cycle for now
def nextState(state: TensorState.Type) = state match { def nextState(state: TensorState.Type) = state match {
case TensorState.idle => Mux(io.initiate.fire, TensorState.run, state) case TensorState.idle => Mux(io.initiate.fire, TensorState.run, state)
case TensorState.run => TensorState.finish case TensorState.run => TensorState.finish
case TensorState.finish => { case TensorState.finish => {
// hold until writeback is cleared // hold until writeback is cleared
@@ -136,3 +138,22 @@ class TensorMemResp(val dataWidth: Int) extends Bundle {
// TODO: tag // TODO: tag
val data = UInt(32.W) val data = UInt(32.W)
} }
// synthesizable unit tests
class TensorCoreDecoupledTest(timeout: Int = 500000)(implicit p: Parameters)
extends UnitTest(timeout) {
val dut = Module(new TensorCoreDecoupled(8, 8, TensorTilingParams()))
dut.io.initiate.valid := io.start
dut.io.initiate.bits.wid := 0.U
// TODO
dut.io.respA.valid := false.B
dut.io.respA.bits := DontCare
dut.io.respB.valid := false.B
dut.io.respB.bits := DontCare
dut.io.reqA.ready := true.B
dut.io.reqB.ready := true.B
dut.io.writeback.ready := true.B
io.finished := dut.io.writeback.valid
}

View File

@@ -1,6 +1,6 @@
// See LICENSE.SiFive for license details. // See LICENSE.SiFive for license details.
package radiance.memory package radiance.unittest
import chisel3._ import chisel3._
import org.chipsalliance.cde.config._ import org.chipsalliance.cde.config._
@@ -8,6 +8,8 @@ import freechips.rocketchip.subsystem.{BaseSubsystemConfig}
import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
import radiance.core.TensorCoreDecoupledTest
import radiance.memory._
import radiance.subsystem.WithSimtConfig import radiance.subsystem.WithSimtConfig
import freechips.rocketchip.unittest._ import freechips.rocketchip.unittest._
//import rocket.VortexFatBankTest //import rocket.VortexFatBankTest
@@ -17,6 +19,16 @@ case object TestDurationMultiplier extends Field[Int]
class WithTestDuration(x: Int) extends Config((site, here, up) => { class WithTestDuration(x: Int) extends Config((site, here, up) => {
case TestDurationMultiplier => x case TestDurationMultiplier => x
}) })
class WithTensorUnitTests extends Config((site, _, _) => {
case UnitTests => (q: Parameters) => {
implicit val p = q
val timeout = 50000 * site(TestDurationMultiplier)
Seq(
Module(new TensorCoreDecoupledTest(timeout=timeout)),
) }
})
class WithCoalescingUnitTests extends Config((site, _, _) => { class WithCoalescingUnitTests extends Config((site, _, _) => {
case UnitTests => (q: Parameters) => { case UnitTests => (q: Parameters) => {
implicit val p = q implicit val p = q
@@ -52,12 +64,34 @@ class WithCoalescingUnitSynthesisDummy(nLanes: Int) extends Config((site, _, _)
) } ) }
}) })
class CoalescingUnitTestConfig extends Config(new WithCoalescingUnitTests ++ new WithTestDuration(10) ++ new WithSimtConfig(nMemLanes=4) ++ new BaseSubsystemConfig) class TensorUnitTestConfig extends Config(
new WithTensorUnitTests ++
new WithTestDuration(10) ++
new BaseSubsystemConfig)
class CoalescingUnitTestConfig extends Config(
new WithCoalescingUnitTests ++
new WithTestDuration(10) ++
new WithSimtConfig(nMemLanes=4) ++
new BaseSubsystemConfig)
//class VortexFatBankUnitTestConfig extends Config(new WithVortexFatBankUnitTests ++ new WithTestDuration(10) ++ new WithSimtConfig(nLanes=4) ++ new BaseSubsystemConfig) //class VortexFatBankUnitTestConfig extends Config(new WithVortexFatBankUnitTests ++ new WithTestDuration(10) ++ new WithSimtConfig(nLanes=4) ++ new BaseSubsystemConfig)
// Dummy configs of various sizes for synthesis // Dummy configs of various sizes for synthesis
class CoalescingSynthesisDummyLane4Config extends Config(new WithCoalescingUnitSynthesisDummy(4) ++ new WithTestDuration(10) ++ new BaseSubsystemConfig) class CoalescingSynthesisDummyLane4Config extends Config(
class CoalescingSynthesisDummyLane8Config extends Config(new WithCoalescingUnitSynthesisDummy(8) ++ new WithTestDuration(10) ++ new BaseSubsystemConfig) new WithCoalescingUnitSynthesisDummy(4) ++
class CoalescingSynthesisDummyLane16Config extends Config(new WithCoalescingUnitSynthesisDummy(16) ++ new WithTestDuration(10) ++ new BaseSubsystemConfig) new WithTestDuration(10) ++
class CoalescingSynthesisDummyLane32Config extends Config(new WithCoalescingUnitSynthesisDummy(32) ++ new WithTestDuration(10) ++ new BaseSubsystemConfig) new BaseSubsystemConfig)
class CoalescingSynthesisDummyLane8Config extends Config(
new WithCoalescingUnitSynthesisDummy(8) ++
new WithTestDuration(10) ++
new BaseSubsystemConfig)
class CoalescingSynthesisDummyLane16Config extends Config(
new WithCoalescingUnitSynthesisDummy(16) ++
new WithTestDuration(10) ++
new BaseSubsystemConfig)
class CoalescingSynthesisDummyLane32Config extends Config(
new WithCoalescingUnitSynthesisDummy(32) ++
new WithTestDuration(10) ++
new BaseSubsystemConfig)