From 3165108c8bad0f968278c82ede73f850ae4deaa0 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Mon, 14 Oct 2024 19:47:00 -0700
Subject: [PATCH] Add synthesizable unit test for tensor

---
 .../radiance/core/TensorCoreDecoupled.scala   | 23 +++++++++-
 .../UnitTest.scala => unittest/Configs.scala} | 46 ++++++++++++++++---
 2 files changed, 62 insertions(+), 7 deletions(-)
 rename src/main/scala/radiance/{memory/UnitTest.scala => unittest/Configs.scala} (64%)

diff --git a/src/main/scala/radiance/core/TensorCoreDecoupled.scala b/src/main/scala/radiance/core/TensorCoreDecoupled.scala
index 87657d5..4744266 100644
--- a/src/main/scala/radiance/core/TensorCoreDecoupled.scala
+++ b/src/main/scala/radiance/core/TensorCoreDecoupled.scala
@@ -5,6 +5,8 @@ package radiance.core
 
 import chisel3._
 import chisel3.util._
+import org.chipsalliance.cde.config.Parameters
+import freechips.rocketchip.unittest.UnitTest
 
 case class TensorTilingParams(
   // Dimension of the SMEM tile
@@ -62,7 +64,7 @@ class TensorCoreDecoupled(
 
   // TODO: just transition every cycle for now
   def nextState(state: TensorState.Type) = state match {
-    case TensorState.idle      => Mux(io.initiate.fire, TensorState.run, state)
+    case TensorState.idle => Mux(io.initiate.fire, TensorState.run, state)
     case TensorState.run  => TensorState.finish
     case TensorState.finish => {
       // hold until writeback is cleared
@@ -136,3 +138,22 @@ class TensorMemResp(val dataWidth: Int) extends Bundle {
   // TODO: tag
   val data = UInt(32.W)
 }
+
+// synthesizable unit tests
+
+class TensorCoreDecoupledTest(timeout: Int = 500000)(implicit p: Parameters)
+    extends UnitTest(timeout) {
+  val dut = Module(new TensorCoreDecoupled(8, 8, TensorTilingParams()))
+  dut.io.initiate.valid := io.start
+  dut.io.initiate.bits.wid := 0.U
+  // TODO
+  dut.io.respA.valid := false.B
+  dut.io.respA.bits := DontCare
+  dut.io.respB.valid := false.B
+  dut.io.respB.bits := DontCare
+  dut.io.reqA.ready := true.B
+  dut.io.reqB.ready := true.B
+  dut.io.writeback.ready := true.B
+
+  io.finished := dut.io.writeback.valid
+}
diff --git a/src/main/scala/radiance/memory/UnitTest.scala b/src/main/scala/radiance/unittest/Configs.scala
similarity index 64%
rename from src/main/scala/radiance/memory/UnitTest.scala
rename to src/main/scala/radiance/unittest/Configs.scala
index c070ef4..065045c 100644
--- a/src/main/scala/radiance/memory/UnitTest.scala
+++ b/src/main/scala/radiance/unittest/Configs.scala
@@ -1,6 +1,6 @@
 // See LICENSE.SiFive for license details.
 
-package radiance.memory
+package radiance.unittest
 
 import chisel3._
 import org.chipsalliance.cde.config._
@@ -8,6 +8,8 @@ import freechips.rocketchip.subsystem.{BaseSubsystemConfig}
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
+import radiance.core.TensorCoreDecoupledTest
+import radiance.memory._
 import radiance.subsystem.WithSimtConfig
 import freechips.rocketchip.unittest._
 //import rocket.VortexFatBankTest
@@ -17,6 +19,16 @@ case object TestDurationMultiplier extends Field[Int]
 class WithTestDuration(x: Int) extends Config((site, here, up) => {
   case TestDurationMultiplier => x
 })
+
+class WithTensorUnitTests extends Config((site, _, _) => {
+  case UnitTests => (q: Parameters) => {
+    implicit val p = q
+    val timeout = 50000 * site(TestDurationMultiplier)
+    Seq(
+      Module(new TensorCoreDecoupledTest(timeout=timeout)),
+    ) }
+})
+
 class WithCoalescingUnitTests extends Config((site, _, _) => {
   case UnitTests => (q: Parameters) => {
     implicit val p = q
@@ -52,12 +64,34 @@ class WithCoalescingUnitSynthesisDummy(nLanes: Int) extends Config((site, _, _)
     ) }
 })
 
-class CoalescingUnitTestConfig extends Config(new WithCoalescingUnitTests ++ new WithTestDuration(10) ++ new WithSimtConfig(nMemLanes=4) ++ new BaseSubsystemConfig)
+class TensorUnitTestConfig extends Config(
+  new WithTensorUnitTests ++
+  new WithTestDuration(10) ++
+  new BaseSubsystemConfig)
+
+class CoalescingUnitTestConfig extends Config(
+  new WithCoalescingUnitTests ++
+  new WithTestDuration(10) ++
+  new WithSimtConfig(nMemLanes=4) ++
+  new BaseSubsystemConfig)
+
 //class VortexFatBankUnitTestConfig extends Config(new WithVortexFatBankUnitTests ++ new WithTestDuration(10) ++ new WithSimtConfig(nLanes=4) ++ new BaseSubsystemConfig)
 
 // Dummy configs of various sizes for synthesis
-class CoalescingSynthesisDummyLane4Config extends Config(new WithCoalescingUnitSynthesisDummy(4) ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
-class CoalescingSynthesisDummyLane8Config extends Config(new WithCoalescingUnitSynthesisDummy(8) ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
-class CoalescingSynthesisDummyLane16Config extends Config(new WithCoalescingUnitSynthesisDummy(16) ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
-class CoalescingSynthesisDummyLane32Config extends Config(new WithCoalescingUnitSynthesisDummy(32) ++ new WithTestDuration(10) ++ new BaseSubsystemConfig)
+class CoalescingSynthesisDummyLane4Config extends Config(
+  new WithCoalescingUnitSynthesisDummy(4) ++
+  new WithTestDuration(10) ++
+  new BaseSubsystemConfig)
+class CoalescingSynthesisDummyLane8Config extends Config(
+  new WithCoalescingUnitSynthesisDummy(8) ++
+  new WithTestDuration(10) ++
+  new BaseSubsystemConfig)
+class CoalescingSynthesisDummyLane16Config extends Config(
+  new WithCoalescingUnitSynthesisDummy(16) ++
+  new WithTestDuration(10) ++
+  new BaseSubsystemConfig)
+class CoalescingSynthesisDummyLane32Config extends Config(
+  new WithCoalescingUnitSynthesisDummy(32) ++
+  new WithTestDuration(10) ++
+  new BaseSubsystemConfig)