From 2d4e28e862ca270b3bcc4f37d8a8788cbc20fe31 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Mon, 8 May 2023 14:38:15 -0700 Subject: [PATCH] Use WithoutTLMonitors to slightly speed up chiseltests --- src/test/scala/coalescing/CoalescingUnitTest.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/test/scala/coalescing/CoalescingUnitTest.scala b/src/test/scala/coalescing/CoalescingUnitTest.scala index 08db521..5a48733 100644 --- a/src/test/scala/coalescing/CoalescingUnitTest.scala +++ b/src/test/scala/coalescing/CoalescingUnitTest.scala @@ -7,6 +7,7 @@ import org.scalatest.flatspec.AnyFlatSpec import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.MultiPortQueue import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.subsystem.WithoutTLMonitors import org.chipsalliance.cde.config.Parameters import chisel3.util.{DecoupledIO, Valid} import chisel3.util.experimental.BoringUtils @@ -230,7 +231,7 @@ class CoalescerUnitTest extends AnyFlatSpec with ChiselScalatestTester { } it should "coalesce fully consecutive accesses at size 4, only once" in { - test(LazyModule(new DummyCoalescingUnitTB()).module) + test(LazyModule(new DummyCoalescingUnitTB()(new WithoutTLMonitors())).module) .withAnnotations(Seq(VerilatorBackendAnnotation, VerilatorFlags(Seq("--coverage-line")), WriteFstAnnotation)) // .withAnnotations(Seq(VcsBackendAnnotation, WriteFsdbAnnotation)) { c => @@ -292,7 +293,7 @@ class CoalescerUnitTest extends AnyFlatSpec with ChiselScalatestTester { } it should "coalesce identical addresses (stride of 0)" in { - test(LazyModule(new DummyCoalescingUnitTB()).module) + test(LazyModule(new DummyCoalescingUnitTB()(new WithoutTLMonitors())).module) .withAnnotations(Seq(VerilatorBackendAnnotation)) { c => println(s"coalIO length = ${c.coalIOs(0).length}")