From 2bdaf3a0a866b614a6afa42978de3aa5b8204792 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 28 Nov 2023 22:49:48 -0800 Subject: [PATCH] Fix undefined {MEM,WORD}_ADDR_SIZE --- src/main/scala/rocket/VortexBank.scala | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/VortexBank.scala b/src/main/scala/rocket/VortexBank.scala index 0443ad4..5d82c0e 100644 --- a/src/main/scala/rocket/VortexBank.scala +++ b/src/main/scala/rocket/VortexBank.scala @@ -444,6 +444,11 @@ class VX_cache_top( log2Ceil(mshrSize) + log2Ceil(numBanks) val MEM_TAG_WIDTH = memTagWidth(MSHR_SIZE, 1/* NUM_BANKS */) + // These logic is fixed in VX_cache_define.vh + val memAddrWidth = 32 // FIXME hardcoded + val cacheWordAddrWidth = 32 - log2Ceil(WORD_SIZE) + val cacheMemAddrWidth = 32 - log2Ceil(CACHE_LINE_SIZE) + val io = IO(new Bundle { val clk = Input(Clock()) val reset = Input(Reset()) @@ -452,7 +457,7 @@ class VX_cache_top( val core_req_valid = Input(Bool()) val core_req_rw = Input(Bool()) val core_req_byteen = Input(UInt(WORD_SIZE.W)) - val core_req_addr = Input(UInt(WORD_ADDR_WIDTH.W)) + val core_req_addr = Input(UInt(cacheWordAddrWidth.W)) val core_req_data = Input(UInt((WORD_SIZE * 8).W)) val core_req_tag = Input(UInt(CORE_TAG_WIDTH.W)) val core_req_ready = Output(Bool()) @@ -466,7 +471,7 @@ class VX_cache_top( val mem_req_valid = Output(Bool()) val mem_req_rw = Output(Bool()) val mem_req_byteen = Output(UInt(CACHE_LINE_SIZE.W)) - val mem_req_addr = Output(UInt(MEM_ADDR_WIDTH.W)) + val mem_req_addr = Output(UInt(cacheMemAddrWidth.W)) val mem_req_data = Output(UInt((CACHE_LINE_SIZE * 8).W)) val mem_req_tag = Output(UInt(MEM_TAG_WIDTH.W)) val mem_req_ready = Input(Bool())