Merge branch 'main' of https://github.com/hansungk/radiance into main

.gitmodules

@@ -1,3 +1,6 @@
 [submodule "src/main/resources/vsrc/vortex"]
 	path = src/main/resources/vsrc/vortex
 	url = https://github.com/hansungk/vortex
+[submodule "radpie"]
+	path = radpie
+	url = git@github.com:hansungk/radpie.git

radiance.mk

@@ -0,0 +1,19 @@
+##############################################################
+# extra variables/targets ingested by the chipyard make system
+##############################################################
+
+##################################################################
+# THE FOLLOWING MUST BE += operators
+##################################################################
+
+RADPIE_SRC_DIR = $(base_dir)/generators/radiance/radpie
+RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release
+
+EXTRA_SIM_REQS += radpie
+EXTRA_SIM_LDFLAGS += -L$(RADPIE_BUILD_DIR) -Wl,-rpath,$(RADPIE_BUILD_DIR) -lradpie
+
+# cargo handles building of Rust files all on its own, so make this a PHONY
+# target to run cargo unconditionally
+.PHONY: radpie
+radpie:
+	cd $(RADPIE_SRC_DIR) && cargo build --release

src/main/scala/radiance/memory/CanHaveMemtraceCore.scala

@@ -22,56 +22,57 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
       )
     val numLanes = simtParam.nLanes
     val filename = param.tracefilename
-    val tracer = LazyModule(
-      new MemTraceDriver(config, filename, param.traceHasSource)(p)
-    )
-    val coreSideLogger = LazyModule(
-      new MemTraceLogger(numLanes, filename, loggerName = "coreside")
-    )
-    val memSideLogger = LazyModule(
-      new MemTraceLogger(numLanes + 1, filename, loggerName = "memside")
-    )
-    // Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
-    // when connecting to SBus
-    println(
-      s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]"
-    )
-    val coalescerNode = p(CoalescerKey) match {
-      case Some(coalParam) => {
-        val coal = LazyModule(new CoalescingUnit(coalParam))
-        coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes
-        memSideLogger.node :=* coal.aggregateNode            // N+1 lanes
-        memSideLogger.node
-      }
-      case None => tracer.node
-    }
-    val coalXbar = p(CoalXbarKey) match {
-      case Some(xbarParam) =>{
-        val coXbar = LazyModule(new TLXbar)
-        println(s"============ Using TLXBar for Coalescer Requests ")
-        coXbar.node :=* coalescerNode
-        coXbar.node
-      }
-      case None => coalescerNode
-    }
 
-    
+    // Need to explicitly generate clock domain; see rocket-chip 8881ccd
-    val vortexBank = coalXbar
+    val memtracerDomain = sbus.generateSynchronousDomain
-    
+    memtracerDomain {
-    
+      val tracer = LazyModule(
-    
+        new MemTraceDriver(config, filename, param.traceHasSource)(p)
-    //If there is only 1 bank, the code below is useless
+      )
-    val upstream = p(CoalXbarKey) match {
+      val coreSideLogger = LazyModule(
-      case Some(xbarParam) =>{
+        new MemTraceLogger(numLanes, filename, loggerName = "coreside")
-        val tileXbar = LazyModule(new TLXbar)
+      )
-        println(s"============ Using TLXBar for L1 Requests ")
+      val memSideLogger = LazyModule(
-        tileXbar.node :=* vortexBank
+        new MemTraceLogger(numLanes + 1, filename, loggerName = "memside")
-        tileXbar.node
+      )
+      // Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
+      // when connecting to SBus
+      println(
+        s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]"
+      )
+       val coalescerNode = p(CoalescerKey) match {
+         case Some(coalParam) => {
+           val coal = LazyModule(new CoalescingUnit(coalParam))
+           coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes
+           memSideLogger.node :=* coal.aggregateNode            // N+1 lanes
+           memSideLogger.node
+         }
+         case None => tracer.node
+       }
+      val coalXbar = p(CoalXbarKey) match {
+        case Some(xbarParam) =>{
+          val coXbar = LazyModule(new TLXbar)
+          println(s"============ Using TLXBar for Coalescer Requests ")
+          coXbar.node :=* coalescerNode
+          coXbar.node
+        }
+        case None => coalescerNode
       }
-      case None => vortexBank
-    }
-  
 
-    sbus.coupleFrom(s"gpu-tracer") { _ :=* upstream }
+      val vortexBank = coalXbar
+
+      //If there is only 1 bank, the code below is useless
+      val upstream = p(CoalXbarKey) match {
+        case Some(xbarParam) =>{
+          val tileXbar = LazyModule(new TLXbar)
+          println(s"============ Using TLXBar for L1 Requests ")
+          tileXbar.node :=* vortexBank
+          tileXbar.node
+        }
+        case None => vortexBank
+      }
+
+      sbus.coupleFrom(s"gpu-tracer") { _ :=* upstream }
+    }
   }
 }

src/main/scala/radiance/tile/VortexCore.scala

@@ -100,7 +100,7 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
   //val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
   //val trace = Output(new TraceBundle)
   //val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)))
-  val cease = Output(Bool())
+  val finished = Output(Bool())
   val wfi = Output(Bool())
   val traceStall = Input(Bool())
 }

src/main/scala/radiance/tile/VortexTile.scala

@@ -452,11 +452,11 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
   core.io.reset_vector := DontCare
 
   outer.regNode.regmap(
-    0x00 -> Seq(RegField.r(32, core.io.cease))
+    0x00 -> Seq(RegField.r(32, core.io.finished))
   )
 
-  // Report when the tile has ceased to retire instructions; for now the only cause is clock gating
+  // Report when the tile has ceased to retire instructions
-  outer.reportCease(outer.vortexParams.core.clockGate.option(core.io.cease))
+  outer.reportCease(Some(core.io.finished))
 
   outer.reportWFI(Some(core.io.wfi))