From 78075e51484ee6960cc06a8e9039a9ae791ee0da Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Thu, 25 Jan 2024 23:24:05 -0800 Subject: [PATCH 1/8] Bump vortex --- src/main/resources/vsrc/vortex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/resources/vsrc/vortex b/src/main/resources/vsrc/vortex index 60d4180..c9d1275 160000 --- a/src/main/resources/vsrc/vortex +++ b/src/main/resources/vsrc/vortex @@ -1 +1 @@ -Subproject commit 60d4180249e1f4b043d388a278f3aae029ab8f8a +Subproject commit c9d1275f0eebc522c64c3b8b467889e842b950c4 From cfce029b70fdb857bb1fd59fe4a445bff466c9cf Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 26 Jan 2024 00:13:14 -0800 Subject: [PATCH 2/8] Generate explicit clock domain in CanHaveMemtraceCore --- .../radiance/memory/CanHaveMemtraceCore.scala | 97 ++++++++++--------- 1 file changed, 49 insertions(+), 48 deletions(-) diff --git a/src/main/scala/radiance/memory/CanHaveMemtraceCore.scala b/src/main/scala/radiance/memory/CanHaveMemtraceCore.scala index 9f132a6..ae803d5 100644 --- a/src/main/scala/radiance/memory/CanHaveMemtraceCore.scala +++ b/src/main/scala/radiance/memory/CanHaveMemtraceCore.scala @@ -22,56 +22,57 @@ trait CanHaveMemtraceCore { this: BaseSubsystem => ) val numLanes = simtParam.nLanes val filename = param.tracefilename - val tracer = LazyModule( - new MemTraceDriver(config, filename, param.traceHasSource)(p) - ) - val coreSideLogger = LazyModule( - new MemTraceLogger(numLanes, filename, loggerName = "coreside") - ) - val memSideLogger = LazyModule( - new MemTraceLogger(numLanes + 1, filename, loggerName = "memside") - ) - // Must use :=* to ensure the N edges from Tracer doesn't get merged into 1 - // when connecting to SBus - println( - s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]" - ) - val coalescerNode = p(CoalescerKey) match { - case Some(coalParam) => { - val coal = LazyModule(new CoalescingUnit(coalParam)) - coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes - memSideLogger.node :=* coal.aggregateNode // N+1 lanes - memSideLogger.node - } - case None => tracer.node - } - val coalXbar = p(CoalXbarKey) match { - case Some(xbarParam) =>{ - val coXbar = LazyModule(new TLXbar) - println(s"============ Using TLXBar for Coalescer Requests ") - coXbar.node :=* coalescerNode - coXbar.node - } - case None => coalescerNode - } - - val vortexBank = coalXbar - - - - //If there is only 1 bank, the code below is useless - val upstream = p(CoalXbarKey) match { - case Some(xbarParam) =>{ - val tileXbar = LazyModule(new TLXbar) - println(s"============ Using TLXBar for L1 Requests ") - tileXbar.node :=* vortexBank - tileXbar.node + // Need to explicitly generate clock domain; see rocket-chip 8881ccd + val memtracerDomain = sbus.generateSynchronousDomain + memtracerDomain { + val tracer = LazyModule( + new MemTraceDriver(config, filename, param.traceHasSource)(p) + ) + val coreSideLogger = LazyModule( + new MemTraceLogger(numLanes, filename, loggerName = "coreside") + ) + val memSideLogger = LazyModule( + new MemTraceLogger(numLanes + 1, filename, loggerName = "memside") + ) + // Must use :=* to ensure the N edges from Tracer doesn't get merged into 1 + // when connecting to SBus + println( + s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]" + ) + val coalescerNode = p(CoalescerKey) match { + case Some(coalParam) => { + val coal = LazyModule(new CoalescingUnit(coalParam)) + coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes + memSideLogger.node :=* coal.aggregateNode // N+1 lanes + memSideLogger.node + } + case None => tracer.node + } + val coalXbar = p(CoalXbarKey) match { + case Some(xbarParam) =>{ + val coXbar = LazyModule(new TLXbar) + println(s"============ Using TLXBar for Coalescer Requests ") + coXbar.node :=* coalescerNode + coXbar.node + } + case None => coalescerNode } - case None => vortexBank - } - - sbus.coupleFrom(s"gpu-tracer") { _ :=* upstream } + val vortexBank = coalXbar + + //If there is only 1 bank, the code below is useless + val upstream = p(CoalXbarKey) match { + case Some(xbarParam) =>{ + val tileXbar = LazyModule(new TLXbar) + println(s"============ Using TLXBar for L1 Requests ") + tileXbar.node :=* vortexBank + tileXbar.node + } + case None => vortexBank + } + + sbus.coupleFrom(s"gpu-tracer") { _ :=* upstream } + } } } From 16c4292e577de0da4ffdea1079e0ae64d5aaa514 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 26 Jan 2024 14:25:12 -0800 Subject: [PATCH 3/8] Rename core.io.cease to finished; bump vortex --- src/main/resources/vsrc/vortex | 2 +- src/main/scala/radiance/tile/VortexCore.scala | 2 +- src/main/scala/radiance/tile/VortexTile.scala | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/main/resources/vsrc/vortex b/src/main/resources/vsrc/vortex index c9d1275..4643edf 160000 --- a/src/main/resources/vsrc/vortex +++ b/src/main/resources/vsrc/vortex @@ -1 +1 @@ -Subproject commit c9d1275f0eebc522c64c3b8b467889e842b950c4 +Subproject commit 4643edf3e9ac94bc7aa994dd5969ee9626dc1511 diff --git a/src/main/scala/radiance/tile/VortexCore.scala b/src/main/scala/radiance/tile/VortexCore.scala index 55568ec..faa837a 100644 --- a/src/main/scala/radiance/tile/VortexCore.scala +++ b/src/main/scala/radiance/tile/VortexCore.scala @@ -100,7 +100,7 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle //val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs)) //val trace = Output(new TraceBundle) //val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth))) - val cease = Output(Bool()) + val finished = Output(Bool()) val wfi = Output(Bool()) val traceStall = Input(Bool()) } diff --git a/src/main/scala/radiance/tile/VortexTile.scala b/src/main/scala/radiance/tile/VortexTile.scala index 068b82b..a09150c 100644 --- a/src/main/scala/radiance/tile/VortexTile.scala +++ b/src/main/scala/radiance/tile/VortexTile.scala @@ -451,11 +451,11 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) { core.io.reset_vector := DontCare outer.regNode.regmap( - 0x00 -> Seq(RegField.r(32, core.io.cease)) + 0x00 -> Seq(RegField.r(32, core.io.finished)) ) - // Report when the tile has ceased to retire instructions; for now the only cause is clock gating - outer.reportCease(outer.vortexParams.core.clockGate.option(core.io.cease)) + // Report when the tile has ceased to retire instructions + outer.reportCease(Some(core.io.finished)) outer.reportWFI(Some(core.io.wfi)) From 149f8b193e6707187fbbc51c09e460f33b0f0573 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Mon, 29 Jan 2024 13:18:58 -0800 Subject: [PATCH 4/8] Add memfuzzer DPI library as submodule --- .gitmodules | 3 +++ radpie | 1 + 2 files changed, 4 insertions(+) create mode 160000 radpie diff --git a/.gitmodules b/.gitmodules index b8ea3f9..9b50b6b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "src/main/resources/vsrc/vortex"] path = src/main/resources/vsrc/vortex url = https://github.com/hansungk/vortex +[submodule "radpie"] + path = radpie + url = git@github.com:hansungk/radpie.git diff --git a/radpie b/radpie new file mode 160000 index 0000000..dd9bcec --- /dev/null +++ b/radpie @@ -0,0 +1 @@ +Subproject commit dd9bcec4e3953bf49149e90d64d6a769c1e468e2 From 2c7d8650d4e853424b12f65c5478b25ef54b50ec Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Mon, 29 Jan 2024 13:58:34 -0800 Subject: [PATCH 5/8] Bump radpie --- radpie | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radpie b/radpie index dd9bcec..20b6de9 160000 --- a/radpie +++ b/radpie @@ -1 +1 @@ -Subproject commit dd9bcec4e3953bf49149e90d64d6a769c1e468e2 +Subproject commit 20b6de91558f1964e80bdf165f8fc236770b9393 From dc86d69da4dfc8dd3c5d852ed7b606df83ea736d Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Mon, 29 Jan 2024 15:40:15 -0800 Subject: [PATCH 6/8] Add make fragment --- radiance.mk | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 radiance.mk diff --git a/radiance.mk b/radiance.mk new file mode 100644 index 0000000..40a4932 --- /dev/null +++ b/radiance.mk @@ -0,0 +1,19 @@ +############################################################## +# extra variables/targets ingested by the chipyard make system +############################################################## + +################################################################## +# THE FOLLOWING MUST BE += operators +################################################################## + +RADPIE_SRC_DIR = $(base_dir)/generators/radiance/radpie +RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release + +EXTRA_SIM_REQS += radpie +EXTRA_SIM_LDFLAGS += -L$(RADPIE_BUILD_DIR) -Wl,-rpath,$(RADPIE_BUILD_DIR) -lradpie + +# cargo handles building of Rust files all on its own, so make this a PHONY +# target to run cargo unconditionally +.PHONY: radpie +radpie: + cd $(RADPIE_SRC_DIR) && cargo build --release From a648b388ef5a5830f40dfe5864a1b51a9115c80e Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 30 Jan 2024 18:01:19 -0800 Subject: [PATCH 7/8] Bump radpie --- radpie | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/radpie b/radpie index 20b6de9..493b8e1 160000 --- a/radpie +++ b/radpie @@ -1 +1 @@ -Subproject commit 20b6de91558f1964e80bdf165f8fc236770b9393 +Subproject commit 493b8e10a5116385946deaaef1a82f6597d7b8a2 From 2aab555f0a169414abe23926480508c040f05c42 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 30 Jan 2024 18:01:32 -0800 Subject: [PATCH 8/8] Connect unified_mem_node from Gemmini --- src/main/scala/radiance/tile/VortexTile.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/radiance/tile/VortexTile.scala b/src/main/scala/radiance/tile/VortexTile.scala index a09150c..169baed 100644 --- a/src/main/scala/radiance/tile/VortexTile.scala +++ b/src/main/scala/radiance/tile/VortexTile.scala @@ -350,6 +350,7 @@ class VortexTile private ( tlOtherMastersNode :=* gemmini.tlNode gemmini.stlNode :=* TLWidthWidget(4) :=* smemXbar.node + gemmini.unified_mem_node :=* TLWidthWidget(4) :=* smemXbar.node /* below are copied from rocket */