diff --git a/.gitmodules b/.gitmodules
index b8ea3f9..9b50b6b 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,6 @@
 [submodule "src/main/resources/vsrc/vortex"]
 	path = src/main/resources/vsrc/vortex
 	url = https://github.com/hansungk/vortex
+[submodule "radpie"]
+	path = radpie
+	url = git@github.com:hansungk/radpie.git
diff --git a/radiance.mk b/radiance.mk
new file mode 100644
index 0000000..40a4932
--- /dev/null
+++ b/radiance.mk
@@ -0,0 +1,19 @@
+##############################################################
+# extra variables/targets ingested by the chipyard make system
+##############################################################
+
+##################################################################
+# THE FOLLOWING MUST BE += operators
+##################################################################
+
+RADPIE_SRC_DIR = $(base_dir)/generators/radiance/radpie
+RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release
+
+EXTRA_SIM_REQS += radpie
+EXTRA_SIM_LDFLAGS += -L$(RADPIE_BUILD_DIR) -Wl,-rpath,$(RADPIE_BUILD_DIR) -lradpie
+
+# cargo handles building of Rust files all on its own, so make this a PHONY
+# target to run cargo unconditionally
+.PHONY: radpie
+radpie:
+	cd $(RADPIE_SRC_DIR) && cargo build --release
diff --git a/radpie b/radpie
new file mode 160000
index 0000000..493b8e1
--- /dev/null
+++ b/radpie
@@ -0,0 +1 @@
+Subproject commit 493b8e10a5116385946deaaef1a82f6597d7b8a2
diff --git a/src/main/resources/vsrc/vortex b/src/main/resources/vsrc/vortex
index 60d4180..4643edf 160000
--- a/src/main/resources/vsrc/vortex
+++ b/src/main/resources/vsrc/vortex
@@ -1 +1 @@
-Subproject commit 60d4180249e1f4b043d388a278f3aae029ab8f8a
+Subproject commit 4643edf3e9ac94bc7aa994dd5969ee9626dc1511
diff --git a/src/main/scala/radiance/memory/CanHaveMemtraceCore.scala b/src/main/scala/radiance/memory/CanHaveMemtraceCore.scala
index 9f132a6..ae803d5 100644
--- a/src/main/scala/radiance/memory/CanHaveMemtraceCore.scala
+++ b/src/main/scala/radiance/memory/CanHaveMemtraceCore.scala
@@ -22,56 +22,57 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
       )
     val numLanes = simtParam.nLanes
     val filename = param.tracefilename
-    val tracer = LazyModule(
-      new MemTraceDriver(config, filename, param.traceHasSource)(p)
-    )
-    val coreSideLogger = LazyModule(
-      new MemTraceLogger(numLanes, filename, loggerName = "coreside")
-    )
-    val memSideLogger = LazyModule(
-      new MemTraceLogger(numLanes + 1, filename, loggerName = "memside")
-    )
-    // Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
-    // when connecting to SBus
-    println(
-      s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]"
-    )
-    val coalescerNode = p(CoalescerKey) match {
-      case Some(coalParam) => {
-        val coal = LazyModule(new CoalescingUnit(coalParam))
-        coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes
-        memSideLogger.node :=* coal.aggregateNode            // N+1 lanes
-        memSideLogger.node
-      }
-      case None => tracer.node
-    }
-    val coalXbar = p(CoalXbarKey) match {
-      case Some(xbarParam) =>{
-        val coXbar = LazyModule(new TLXbar)
-        println(s"============ Using TLXBar for Coalescer Requests ")
-        coXbar.node :=* coalescerNode
-        coXbar.node
-      }
-      case None => coalescerNode
-    }
 
-    
-    val vortexBank = coalXbar
-    
-    
-    
-    //If there is only 1 bank, the code below is useless
-    val upstream = p(CoalXbarKey) match {
-      case Some(xbarParam) =>{
-        val tileXbar = LazyModule(new TLXbar)
-        println(s"============ Using TLXBar for L1 Requests ")
-        tileXbar.node :=* vortexBank
-        tileXbar.node
+    // Need to explicitly generate clock domain; see rocket-chip 8881ccd
+    val memtracerDomain = sbus.generateSynchronousDomain
+    memtracerDomain {
+      val tracer = LazyModule(
+        new MemTraceDriver(config, filename, param.traceHasSource)(p)
+      )
+      val coreSideLogger = LazyModule(
+        new MemTraceLogger(numLanes, filename, loggerName = "coreside")
+      )
+      val memSideLogger = LazyModule(
+        new MemTraceLogger(numLanes + 1, filename, loggerName = "memside")
+      )
+      // Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
+      // when connecting to SBus
+      println(
+        s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]"
+      )
+       val coalescerNode = p(CoalescerKey) match {
+         case Some(coalParam) => {
+           val coal = LazyModule(new CoalescingUnit(coalParam))
+           coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes
+           memSideLogger.node :=* coal.aggregateNode            // N+1 lanes
+           memSideLogger.node
+         }
+         case None => tracer.node
+       }
+      val coalXbar = p(CoalXbarKey) match {
+        case Some(xbarParam) =>{
+          val coXbar = LazyModule(new TLXbar)
+          println(s"============ Using TLXBar for Coalescer Requests ")
+          coXbar.node :=* coalescerNode
+          coXbar.node
+        }
+        case None => coalescerNode
       }
-      case None => vortexBank
-    }
-  
 
-    sbus.coupleFrom(s"gpu-tracer") { _ :=* upstream }
+      val vortexBank = coalXbar
+
+      //If there is only 1 bank, the code below is useless
+      val upstream = p(CoalXbarKey) match {
+        case Some(xbarParam) =>{
+          val tileXbar = LazyModule(new TLXbar)
+          println(s"============ Using TLXBar for L1 Requests ")
+          tileXbar.node :=* vortexBank
+          tileXbar.node
+        }
+        case None => vortexBank
+      }
+
+      sbus.coupleFrom(s"gpu-tracer") { _ :=* upstream }
+    }
   }
 }
diff --git a/src/main/scala/radiance/tile/VortexCore.scala b/src/main/scala/radiance/tile/VortexCore.scala
index 55568ec..faa837a 100644
--- a/src/main/scala/radiance/tile/VortexCore.scala
+++ b/src/main/scala/radiance/tile/VortexCore.scala
@@ -100,7 +100,7 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
   //val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
   //val trace = Output(new TraceBundle)
   //val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)))
-  val cease = Output(Bool())
+  val finished = Output(Bool())
   val wfi = Output(Bool())
   val traceStall = Input(Bool())
 }
diff --git a/src/main/scala/radiance/tile/VortexTile.scala b/src/main/scala/radiance/tile/VortexTile.scala
index 3740e4a..d7bc3fe 100644
--- a/src/main/scala/radiance/tile/VortexTile.scala
+++ b/src/main/scala/radiance/tile/VortexTile.scala
@@ -452,11 +452,11 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
   core.io.reset_vector := DontCare
 
   outer.regNode.regmap(
-    0x00 -> Seq(RegField.r(32, core.io.cease))
+    0x00 -> Seq(RegField.r(32, core.io.finished))
   )
 
-  // Report when the tile has ceased to retire instructions; for now the only cause is clock gating
-  outer.reportCease(outer.vortexParams.core.clockGate.option(core.io.cease))
+  // Report when the tile has ceased to retire instructions
+  outer.reportCease(Some(core.io.finished))
 
   outer.reportWFI(Some(core.io.wfi))