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Store UInt instead of ChiselEnum in entry; pass tests

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Scala isn't happy with storing ChiselEnum type for some reason
This commit is contained in:
Hansung Kim
2023-04-23 15:28:12 -07:00
parent 8cee61a591
commit 0f2e4ee8aa
2 changed files with 41 additions and 25 deletions
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22
src/main/scala/tilelink/Coalescing.scala
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@@ -456,7 +456,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
// but the width of the size enum
val newEntry = Wire(
new InflightCoalReqTableEntry(config.NUM_LANES, numPerLaneReqs, sourceWidth, offsetBits,
config.SizeEnum)
config.SizeEnum.getWidth)
)
println(s"=========== table sourceWidth: ${sourceWidth}")
// println(s"=========== table sizeEnumBits: ${newEntry.sizeEnumBits}")
@@ -472,7 +472,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
r.valid := false.B
r.source := origReqs(i).source
r.offset := (origReqs(i).address % (1 << config.MAX_SIZE).U) >> config.WORD_WIDTH
r.sizeEnum := config.SizeEnum.logSizeToEnum(origReqs(i).size)
r.sizeEnum := config.SizeEnum.logSizeToEnum(origReqs(i).size).asUInt
}
}
newEntry.lanes(0).reqs(0).valid := true.B
@@ -601,14 +601,10 @@ class UncoalescingUnit(config: CoalescerConfig) extends Module {
ioOldReq.valid := false.B
ioOldReq.bits := DontCare
when(inflightTable.io.lookup.valid) {
when(inflightTable.io.lookup.valid && oldReq.valid) {
ioOldReq.valid := oldReq.valid
ioOldReq.bits.source := oldReq.source
// FIXME: this is janky. We can't use config.SizeEnum.enumToLogSize for
// some reason because type checker complains that config.SizeEnum.Type
// is different from found.sizeEnumType.type
// val logSize = config.SizeEnum.enumToLogSize(oldReq.sizeEnum)
val logSize = found.sizeEnumType.enumToLogSize(oldReq.sizeEnum)
val logSize = config.SizeEnum.enumToLogSize(config.SizeEnum(oldReq.sizeEnum))
ioOldReq.bits.size := logSize
ioOldReq.bits.data :=
getCoalescedDataChunk(io.coalResp.bits.data, io.coalResp.bits.data.getWidth, oldReq.offset, logSize)
@@ -626,7 +622,7 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module {
val offsetBits = 4 // FIXME hardcoded
val sizeBits = 2 // FIXME hardcoded
val entryT = new InflightCoalReqTableEntry(config.NUM_LANES, config.DEPTH,
log2Ceil(config.NUM_OLD_IDS), config.MAX_SIZE, config.SizeEnum)
log2Ceil(config.NUM_OLD_IDS), config.MAX_SIZE, config.SizeEnum.getWidth)
val entries = config.NUM_NEW_IDS
val sourceWidth = log2Ceil(config.NUM_OLD_IDS)
@@ -655,7 +651,7 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module {
r.valid := false.B
r.source := 0.U
r.offset := 0.U
r.sizeEnum := config.SizeEnum.INVALID
r.sizeEnum := config.SizeEnum.INVALID.asUInt
}
}
}
@@ -703,14 +699,14 @@ class InflightCoalReqTableEntry(
val numPerLaneReqs: Int,
val sourceWidth: Int,
val offsetBits: Int,
val sizeEnumType: InFlightTableSizeEnum
val sizeEnumBits: Int
) extends Bundle {
class PerCoreReq extends Bundle {
val valid = Bool()
val valid = Bool() // FIXME: delete this
// FIXME: oldId and newId shares the same width
val source = UInt(sourceWidth.W)
val offset = UInt(offsetBits.W)
val sizeEnum = sizeEnumType()
val sizeEnum = UInt(sizeEnumBits.W)
}
class PerLane extends Bundle {
val reqs = Vec(numPerLaneReqs, new PerCoreReq)