diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 1806b0b..dc0631e 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -456,7 +456,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends // but the width of the size enum val newEntry = Wire( new InflightCoalReqTableEntry(config.NUM_LANES, numPerLaneReqs, sourceWidth, offsetBits, - config.SizeEnum) + config.SizeEnum.getWidth) ) println(s"=========== table sourceWidth: ${sourceWidth}") // println(s"=========== table sizeEnumBits: ${newEntry.sizeEnumBits}") @@ -472,7 +472,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends r.valid := false.B r.source := origReqs(i).source r.offset := (origReqs(i).address % (1 << config.MAX_SIZE).U) >> config.WORD_WIDTH - r.sizeEnum := config.SizeEnum.logSizeToEnum(origReqs(i).size) + r.sizeEnum := config.SizeEnum.logSizeToEnum(origReqs(i).size).asUInt } } newEntry.lanes(0).reqs(0).valid := true.B @@ -601,14 +601,10 @@ class UncoalescingUnit(config: CoalescerConfig) extends Module { ioOldReq.valid := false.B ioOldReq.bits := DontCare - when(inflightTable.io.lookup.valid) { + when(inflightTable.io.lookup.valid && oldReq.valid) { ioOldReq.valid := oldReq.valid ioOldReq.bits.source := oldReq.source - // FIXME: this is janky. We can't use config.SizeEnum.enumToLogSize for - // some reason because type checker complains that config.SizeEnum.Type - // is different from found.sizeEnumType.type - // val logSize = config.SizeEnum.enumToLogSize(oldReq.sizeEnum) - val logSize = found.sizeEnumType.enumToLogSize(oldReq.sizeEnum) + val logSize = config.SizeEnum.enumToLogSize(config.SizeEnum(oldReq.sizeEnum)) ioOldReq.bits.size := logSize ioOldReq.bits.data := getCoalescedDataChunk(io.coalResp.bits.data, io.coalResp.bits.data.getWidth, oldReq.offset, logSize) @@ -626,7 +622,7 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module { val offsetBits = 4 // FIXME hardcoded val sizeBits = 2 // FIXME hardcoded val entryT = new InflightCoalReqTableEntry(config.NUM_LANES, config.DEPTH, - log2Ceil(config.NUM_OLD_IDS), config.MAX_SIZE, config.SizeEnum) + log2Ceil(config.NUM_OLD_IDS), config.MAX_SIZE, config.SizeEnum.getWidth) val entries = config.NUM_NEW_IDS val sourceWidth = log2Ceil(config.NUM_OLD_IDS) @@ -655,7 +651,7 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module { r.valid := false.B r.source := 0.U r.offset := 0.U - r.sizeEnum := config.SizeEnum.INVALID + r.sizeEnum := config.SizeEnum.INVALID.asUInt } } } @@ -703,14 +699,14 @@ class InflightCoalReqTableEntry( val numPerLaneReqs: Int, val sourceWidth: Int, val offsetBits: Int, - val sizeEnumType: InFlightTableSizeEnum + val sizeEnumBits: Int ) extends Bundle { class PerCoreReq extends Bundle { - val valid = Bool() + val valid = Bool() // FIXME: delete this // FIXME: oldId and newId shares the same width val source = UInt(sourceWidth.W) val offset = UInt(offsetBits.W) - val sizeEnum = sizeEnumType() + val sizeEnum = UInt(sizeEnumBits.W) } class PerLane extends Bundle { val reqs = Vec(numPerLaneReqs, new PerCoreReq) diff --git a/src/test/scala/coalescing/CoalescingUnitTest.scala b/src/test/scala/coalescing/CoalescingUnitTest.scala index c37396c..bf9a249 100644 --- a/src/test/scala/coalescing/CoalescingUnitTest.scala +++ b/src/test/scala/coalescing/CoalescingUnitTest.scala @@ -254,6 +254,22 @@ class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester { } } +object testConfig extends CoalescerConfig( + MAX_SIZE = 4, // maximum coalesced size + DEPTH = 2, // request window per lane + WAIT_TIMEOUT = 8, // max cycles to wait before forced fifo dequeue, per lane + ADDR_WIDTH = 24, // assume <= 32 + DATA_BUS_SIZE = 4, // 2^4=16 bytes, 128 bit bus + NUM_LANES = 4, + // WATERMARK = 2, // minimum buffer occupancy to start coalescing + WORD_SIZE = 4, // 32-bit system + WORD_WIDTH = 2, // log(WORD_SIZE) + NUM_OLD_IDS = 16, // num of outstanding requests per lane, from processor + NUM_NEW_IDS = 4, // num of outstanding coalesced requests + COAL_SIZES = Seq(3), + SizeEnum = DefaultInFlightTableSizeEnum +) + class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester { behavior of "uncoalescer" val numLanes = 4 @@ -265,7 +281,7 @@ class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester { val numInflightCoalRequests = 4 it should "work" in { - test(new UncoalescingUnit(defaultConfig)) + test(new UncoalescingUnit(testConfig)) // vcs helps with simulation time, but sometimes errors with // "mutation occurred during iteration" java error // .withAnnotations(Seq(VcsBackendAnnotation)) @@ -276,19 +292,21 @@ class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester { c.io.newEntry.lanes(0).reqs(0).valid.poke(true.B) c.io.newEntry.lanes(0).reqs(0).source.poke(1.U) c.io.newEntry.lanes(0).reqs(0).offset.poke(1.U) - c.io.newEntry.lanes(0).reqs(0).size.poke(2.U) + c.io.newEntry.lanes(0).reqs(0).sizeEnum.poke(1.U) // 1.U is FOUR c.io.newEntry.lanes(0).reqs(1).valid.poke(true.B) c.io.newEntry.lanes(0).reqs(1).source.poke(2.U) - c.io.newEntry.lanes(0).reqs(1).offset.poke(1.U) - c.io.newEntry.lanes(0).reqs(1).size.poke(2.U) + c.io.newEntry.lanes(0).reqs(1).offset.poke(0.U) + c.io.newEntry.lanes(0).reqs(1).sizeEnum.poke(1.U) + c.io.newEntry.lanes(1).reqs(0).valid.poke(false.B) c.io.newEntry.lanes(2).reqs(0).valid.poke(true.B) - c.io.newEntry.lanes(2).reqs(0).source.poke(1.U) + c.io.newEntry.lanes(2).reqs(0).source.poke(2.U) c.io.newEntry.lanes(2).reqs(0).offset.poke(2.U) - c.io.newEntry.lanes(2).reqs(0).size.poke(1.U) + c.io.newEntry.lanes(2).reqs(0).sizeEnum.poke(1.U) c.io.newEntry.lanes(2).reqs(1).valid.poke(true.B) c.io.newEntry.lanes(2).reqs(1).source.poke(2.U) - c.io.newEntry.lanes(2).reqs(1).offset.poke(0.U) - c.io.newEntry.lanes(2).reqs(1).size.poke(2.U) + c.io.newEntry.lanes(2).reqs(1).offset.poke(3.U) + c.io.newEntry.lanes(2).reqs(1).sizeEnum.poke(1.U) + c.io.newEntry.lanes(3).reqs(0).valid.poke(false.B) c.clock.step() @@ -299,6 +317,7 @@ class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester { c.io.coalResp.valid.poke(true.B) c.io.coalResp.bits.source.poke(sourceId) val lit = (BigInt(0x0123456789abcdefL) << 64) | BigInt(0x5ca1ab1edeadbeefL) + // val lit = BigInt(0x0123456789abcdefL) c.io.coalResp.bits.data.poke(lit.U) // table lookup is combinational at the same cycle @@ -307,12 +326,13 @@ class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester { c.io.uncoalResps(2)(0).valid.expect(true.B) c.io.uncoalResps(3)(0).valid.expect(false.B) - c.io.uncoalResps(0)(0).bits.data.expect(0x89abcdefL.U) + // offset is counting from LSB + c.io.uncoalResps(0)(0).bits.data.expect(0x5ca1ab1eL.U) c.io.uncoalResps(0)(0).bits.source.expect(1.U) - c.io.uncoalResps(0)(1).bits.data.expect(0x89abcdefL.U) + c.io.uncoalResps(0)(1).bits.data.expect(0xdeadbeefL.U) c.io.uncoalResps(0)(1).bits.source.expect(2.U) - c.io.uncoalResps(2)(0).bits.data.expect(0x5ca1ab1eL.U) - c.io.uncoalResps(2)(0).bits.source.expect(1.U) + c.io.uncoalResps(2)(0).bits.data.expect(0x89abcdefL.U) + c.io.uncoalResps(2)(0).bits.source.expect(2.U) c.io.uncoalResps(2)(1).bits.data.expect(0x01234567L.U) c.io.uncoalResps(2)(1).bits.source.expect(2.U) }