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Make numOldSrcIds and numNewSrcIds parameters of SoC

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This commit is contained in:
Vamber Yang
2023-05-19 17:47:18 -07:00
parent ab3ce82aff
commit 0d96d81968
2 changed files with 8 additions and 2 deletions
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4
src/main/scala/tilelink/Coalescing.scala
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@@ -11,7 +11,9 @@ import freechips.rocketchip.util.MultiPortQueue
import freechips.rocketchip.unittest._ import freechips.rocketchip.unittest._
// TODO: find better place for these // TODO: find better place for these
case class SIMTCoreParams(nLanes: Int = 4)
// Note: numNewSrcId is not a part of CoreParam, because the SIMT core should be agnostic to how inflight coalesced request can be genertated
case class SIMTCoreParams(nLanes: Int = 4, nSrcIds: Int = 8)
case class MemtraceCoreParams(tracefilename: String = "undefined", traceHasSource: Boolean = false) case class MemtraceCoreParams(tracefilename: String = "undefined", traceHasSource: Boolean = false)
case class CoalXbarParam() case class CoalXbarParam()

6
src/main/scala/tilelink/TracerSystemMem.scala
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@@ -12,7 +12,10 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
p(MemtraceCoreKey).map { param => p(MemtraceCoreKey).map { param =>
// Safe to use get as WithMemtraceCore requires WithNLanes to be defined // Safe to use get as WithMemtraceCore requires WithNLanes to be defined
val simtParam = p(SIMTCoreKey).get val simtParam = p(SIMTCoreKey).get
val config = defaultConfig.copy(numLanes = simtParam.nLanes) val config = defaultConfig.copy(
numLanes = simtParam.nLanes,
numOldSrcIds = simtParam.nSrcIds
)
val numLanes = simtParam.nLanes val numLanes = simtParam.nLanes
val filename = param.tracefilename val filename = param.tracefilename
val tracer = LazyModule( val tracer = LazyModule(
@@ -33,6 +36,7 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
case Some(coalParam) => { case Some(coalParam) => {
val coal = LazyModule(new CoalescingUnit(coalParam)) val coal = LazyModule(new CoalescingUnit(coalParam))
println(s"============ CoalescingUnit instantiated [numLanes=${coalParam.numLanes}]") println(s"============ CoalescingUnit instantiated [numLanes=${coalParam.numLanes}]")
println(s"============ numOldSrcId and numNewSrc are (${coalParam.numOldSrcIds},${coalParam.numNewSrcIds})")
coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes
memSideLogger.node :=* coal.aggregateNode // N+1 lanes memSideLogger.node :=* coal.aggregateNode // N+1 lanes
memSideLogger.node memSideLogger.node