From 0d96d819680a94723de1b8a65c04449b75444b66 Mon Sep 17 00:00:00 2001 From: Vamber Yang Date: Fri, 19 May 2023 17:47:18 -0700 Subject: [PATCH] Make numOldSrcIds and numNewSrcIds parameters of SoC --- src/main/scala/tilelink/Coalescing.scala | 4 +++- src/main/scala/tilelink/TracerSystemMem.scala | 6 +++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 13c0d89..0ac4e14 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -11,7 +11,9 @@ import freechips.rocketchip.util.MultiPortQueue import freechips.rocketchip.unittest._ // TODO: find better place for these -case class SIMTCoreParams(nLanes: Int = 4) + +// Note: numNewSrcId is not a part of CoreParam, because the SIMT core should be agnostic to how inflight coalesced request can be genertated +case class SIMTCoreParams(nLanes: Int = 4, nSrcIds: Int = 8) case class MemtraceCoreParams(tracefilename: String = "undefined", traceHasSource: Boolean = false) case class CoalXbarParam() diff --git a/src/main/scala/tilelink/TracerSystemMem.scala b/src/main/scala/tilelink/TracerSystemMem.scala index 151ea27..d9d1682 100644 --- a/src/main/scala/tilelink/TracerSystemMem.scala +++ b/src/main/scala/tilelink/TracerSystemMem.scala @@ -12,7 +12,10 @@ trait CanHaveMemtraceCore { this: BaseSubsystem => p(MemtraceCoreKey).map { param => // Safe to use get as WithMemtraceCore requires WithNLanes to be defined val simtParam = p(SIMTCoreKey).get - val config = defaultConfig.copy(numLanes = simtParam.nLanes) + val config = defaultConfig.copy( + numLanes = simtParam.nLanes, + numOldSrcIds = simtParam.nSrcIds + ) val numLanes = simtParam.nLanes val filename = param.tracefilename val tracer = LazyModule( @@ -33,6 +36,7 @@ trait CanHaveMemtraceCore { this: BaseSubsystem => case Some(coalParam) => { val coal = LazyModule(new CoalescingUnit(coalParam)) println(s"============ CoalescingUnit instantiated [numLanes=${coalParam.numLanes}]") + println(s"============ numOldSrcId and numNewSrc are (${coalParam.numOldSrcIds},${coalParam.numNewSrcIds})") coal.cpuNode :=* coreSideLogger.node :=* tracer.node // N lanes memSideLogger.node :=* coal.aggregateNode // N+1 lanes memSideLogger.node