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felsabbagh3 b3f464dd89 Barriers impl + tested
2019-10-22 01:47:39 -04:00
emulator
Added Bug coments
2019-06-12 08:26:04 -07:00
kernel
Barriers impl + tested
2019-10-22 01:47:39 -04:00
models/memory
Generated memory blocks for data cache (data), data cache (tag), shared memory
2019-10-20 14:52:28 -04:00
rtl
Barriers impl + tested
2019-10-22 01:47:39 -04:00
syn
Finished synthesis with no optimization, cell count increasts to 100k
2019-10-21 17:53:51 -04:00
.DS_Store
ram stdint + Quartus Files
2019-06-11 21:13:30 -07:00
.gitignore
New Warp Scheduler + VCD Enable
2019-09-15 00:12:41 -04:00
README.md
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2019-03-22 04:29:24 -04:00
results.txt
Less expensive but slower fetch logic
2019-05-05 22:55:47 -04:00
TODO
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2019-03-31 05:22:42 -04:00

README.md

Vortex RISC-V GPGPU

Vortex currently supported RV32IM.

./Kernel is a demo of exposing the warps and threads to a program. (Stable)

./emulator is an emulator for RV32IM with warp and thread support. (Stable)

./rtl is verilog for the processor. Currently supports RV32IM and passes all tests.

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Readme Apache-2.0 323 MiB
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