Generated memory blocks for data cache (data), data cache (tag), shared memory
This commit is contained in:
Lingjun Zhu
129
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.bitmap
Normal file
129
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.bitmap
Normal file
File diff suppressed because one or more lines are too long
69
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.cpf
Normal file
69
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.cpf
Normal file
File diff suppressed because one or more lines are too long
1324
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.ctl
Normal file
1324
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.ctl
Normal file
File diff suppressed because it is too large
Load Diff
32824
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.lef
Normal file
32824
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.lef
Normal file
File diff suppressed because it is too large
Load Diff
2754
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.mdt
Normal file
2754
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.mdt
Normal file
File diff suppressed because it is too large
Load Diff
359
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.memlib
Normal file
359
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.memlib
Normal file
@@ -0,0 +1,359 @@
|
||||
/* logicvision_memcomp Version: c0.1.2-beta */
|
||||
/* common_memcomp Version: c0.1.0-EAC */
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||||
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
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||||
//
|
||||
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
//
|
||||
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
//
|
||||
// Use of this Software is subject to the terms and conditions of the
|
||||
// applicable license agreement with ARM Physical IP, Inc.
|
||||
// In addition, this Software is protected by patents, copyright law
|
||||
// and international treaties.
|
||||
//
|
||||
// The copyright notice(s) in this Software does not indicate actual or
|
||||
// intended publication of this Software.
|
||||
//
|
||||
// logicvision model for High Density Two Port Register File SVT MVT Compiler
|
||||
//
|
||||
// Instance Name: rf2_128x128_wm1
|
||||
// Words: 128
|
||||
// Bits: 128
|
||||
// Mux: 2
|
||||
// Drive: 6
|
||||
// Write Mask: On
|
||||
// Extra Margin Adjustment: On
|
||||
// Redundant Rows: 0
|
||||
// Redundant Columns: 2
|
||||
// Test Muxes On
|
||||
//
|
||||
// Creation Date: Sun Oct 20 14:48:39 2019
|
||||
// Version: r4p0
|
||||
//
|
||||
// Modeling Assumptions:
|
||||
//
|
||||
// Modeling Limitations: None
|
||||
//
|
||||
// Known Bugs: None.
|
||||
//
|
||||
// Known Work Arounds: N/A
|
||||
//
|
||||
MemoryTemplate (rf2_128x128_wm1) {
|
||||
Algorithm : SmarchChkbvcd;
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||||
DataOutStage : None;
|
||||
LogicalPorts : 1R1W;
|
||||
BitGrouping : 1;
|
||||
MemoryType : SRAM;
|
||||
MinHold : 0.5;
|
||||
OperationSet : SyncWRvcd;
|
||||
SelectDuringWriteThru : Off;
|
||||
ShadowRead : On;
|
||||
ShadowWrite : On;
|
||||
TransparentMode : None;
|
||||
ObservationLogic: On;
|
||||
InternalScanLogic: On;
|
||||
CellName : rf2_128x128_wm1;
|
||||
NumberOfWords : 128;
|
||||
AddressCounter{
|
||||
Function (Address) {
|
||||
LogicalAddressMap{
|
||||
ColumnAddress[0] : Address[0];
|
||||
RowAddress[5:0] : Address[6:1];
|
||||
}
|
||||
}
|
||||
Function (ColumnAddress) {
|
||||
CountRange [0:1];
|
||||
}
|
||||
Function (RowAddress) {
|
||||
CountRange [0:63];
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||||
}
|
||||
}
|
||||
PhysicalAddressMap{
|
||||
ColumnAddress[0] : c[0];
|
||||
RowAddress[0] : r[0];
|
||||
RowAddress[1] : r[1];
|
||||
RowAddress[2] : r[2];
|
||||
RowAddress[3] : r[3];
|
||||
RowAddress[4] : r[4];
|
||||
RowAddress[5] : r[5];
|
||||
}
|
||||
PhysicalDataMap{
|
||||
Data[0] : NOT d[0];
|
||||
Data[1] : NOT d[1];
|
||||
Data[2] : NOT d[2];
|
||||
Data[3] : NOT d[3];
|
||||
Data[4] : NOT d[4];
|
||||
Data[5] : NOT d[5];
|
||||
Data[6] : NOT d[6];
|
||||
Data[7] : NOT d[7];
|
||||
Data[8] : NOT d[8];
|
||||
Data[9] : NOT d[9];
|
||||
Data[10] : NOT d[10];
|
||||
Data[11] : NOT d[11];
|
||||
Data[12] : NOT d[12];
|
||||
Data[13] : NOT d[13];
|
||||
Data[14] : NOT d[14];
|
||||
Data[15] : NOT d[15];
|
||||
Data[16] : NOT d[16];
|
||||
Data[17] : NOT d[17];
|
||||
Data[18] : NOT d[18];
|
||||
Data[19] : NOT d[19];
|
||||
Data[20] : NOT d[20];
|
||||
Data[21] : NOT d[21];
|
||||
Data[22] : NOT d[22];
|
||||
Data[23] : NOT d[23];
|
||||
Data[24] : NOT d[24];
|
||||
Data[25] : NOT d[25];
|
||||
Data[26] : NOT d[26];
|
||||
Data[27] : NOT d[27];
|
||||
Data[28] : NOT d[28];
|
||||
Data[29] : NOT d[29];
|
||||
Data[30] : NOT d[30];
|
||||
Data[31] : NOT d[31];
|
||||
Data[32] : NOT d[32];
|
||||
Data[33] : NOT d[33];
|
||||
Data[34] : NOT d[34];
|
||||
Data[35] : NOT d[35];
|
||||
Data[36] : NOT d[36];
|
||||
Data[37] : NOT d[37];
|
||||
Data[38] : NOT d[38];
|
||||
Data[39] : NOT d[39];
|
||||
Data[40] : NOT d[40];
|
||||
Data[41] : NOT d[41];
|
||||
Data[42] : NOT d[42];
|
||||
Data[43] : NOT d[43];
|
||||
Data[44] : NOT d[44];
|
||||
Data[45] : NOT d[45];
|
||||
Data[46] : NOT d[46];
|
||||
Data[47] : NOT d[47];
|
||||
Data[48] : NOT d[48];
|
||||
Data[49] : NOT d[49];
|
||||
Data[50] : NOT d[50];
|
||||
Data[51] : NOT d[51];
|
||||
Data[52] : NOT d[52];
|
||||
Data[53] : NOT d[53];
|
||||
Data[54] : NOT d[54];
|
||||
Data[55] : NOT d[55];
|
||||
Data[56] : NOT d[56];
|
||||
Data[57] : NOT d[57];
|
||||
Data[58] : NOT d[58];
|
||||
Data[59] : NOT d[59];
|
||||
Data[60] : NOT d[60];
|
||||
Data[61] : NOT d[61];
|
||||
Data[62] : NOT d[62];
|
||||
Data[63] : NOT d[63];
|
||||
Data[64] : d[64];
|
||||
Data[65] : d[65];
|
||||
Data[66] : d[66];
|
||||
Data[67] : d[67];
|
||||
Data[68] : d[68];
|
||||
Data[69] : d[69];
|
||||
Data[70] : d[70];
|
||||
Data[71] : d[71];
|
||||
Data[72] : d[72];
|
||||
Data[73] : d[73];
|
||||
Data[74] : d[74];
|
||||
Data[75] : d[75];
|
||||
Data[76] : d[76];
|
||||
Data[77] : d[77];
|
||||
Data[78] : d[78];
|
||||
Data[79] : d[79];
|
||||
Data[80] : d[80];
|
||||
Data[81] : d[81];
|
||||
Data[82] : d[82];
|
||||
Data[83] : d[83];
|
||||
Data[84] : d[84];
|
||||
Data[85] : d[85];
|
||||
Data[86] : d[86];
|
||||
Data[87] : d[87];
|
||||
Data[88] : d[88];
|
||||
Data[89] : d[89];
|
||||
Data[90] : d[90];
|
||||
Data[91] : d[91];
|
||||
Data[92] : d[92];
|
||||
Data[93] : d[93];
|
||||
Data[94] : d[94];
|
||||
Data[95] : d[95];
|
||||
Data[96] : d[96];
|
||||
Data[97] : d[97];
|
||||
Data[98] : d[98];
|
||||
Data[99] : d[99];
|
||||
Data[100] : d[100];
|
||||
Data[101] : d[101];
|
||||
Data[102] : d[102];
|
||||
Data[103] : d[103];
|
||||
Data[104] : d[104];
|
||||
Data[105] : d[105];
|
||||
Data[106] : d[106];
|
||||
Data[107] : d[107];
|
||||
Data[108] : d[108];
|
||||
Data[109] : d[109];
|
||||
Data[110] : d[110];
|
||||
Data[111] : d[111];
|
||||
Data[112] : d[112];
|
||||
Data[113] : d[113];
|
||||
Data[114] : d[114];
|
||||
Data[115] : d[115];
|
||||
Data[116] : d[116];
|
||||
Data[117] : d[117];
|
||||
Data[118] : d[118];
|
||||
Data[119] : d[119];
|
||||
Data[120] : d[120];
|
||||
Data[121] : d[121];
|
||||
Data[122] : d[122];
|
||||
Data[123] : d[123];
|
||||
Data[124] : d[124];
|
||||
Data[125] : d[125];
|
||||
Data[126] : d[126];
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||||
Data[127] : d[127];
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||||
}
|
||||
Port (AA[6:0]) {
|
||||
Function : Address;
|
||||
LogicalPort : A;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TAA[6:0];
|
||||
TestOutput : AYA[6:0];
|
||||
}
|
||||
}
|
||||
Port (QA[127:0]) {
|
||||
Function : Data;
|
||||
Direction : output;
|
||||
LogicalPort : A;
|
||||
}
|
||||
Port (CENA) {
|
||||
Function : ReadEnable;
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||||
LogicalPort : A;
|
||||
Polarity : ActiveLow;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TCENA;
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||||
TestOutput : CENYA;
|
||||
}
|
||||
}
|
||||
Port (TENA) {
|
||||
Function : BISTOn;
|
||||
Direction : Input;
|
||||
LogicalPort : A;
|
||||
Polarity : ActiveLow;
|
||||
}
|
||||
Port (CLKA) {
|
||||
Function : Clock;
|
||||
LogicalPort : A;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (EMAA[2:0]) {
|
||||
Function : None;
|
||||
SafeValue : 0;
|
||||
Direction : Input;
|
||||
LogicalPort : A;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (EMASA) {
|
||||
Function : None;
|
||||
SafeValue : 0;
|
||||
Direction : Input;
|
||||
LogicalPort : A;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SEA){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 0;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SIA[1:0]){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 0;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SOA[1:0]){
|
||||
Function : None;
|
||||
Direction : Output;
|
||||
}
|
||||
port (DFTRAMBYP){
|
||||
Function : ScanTest;
|
||||
Direction : Input;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (AB[6:0]) {
|
||||
Function : Address;
|
||||
LogicalPort : B;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TAB[6:0];
|
||||
TestOutput : AYB[6:0];
|
||||
}
|
||||
}
|
||||
Port (DB[127:0]) {
|
||||
Function : Data;
|
||||
Direction : input;
|
||||
LogicalPort : B;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TDB[127:0];
|
||||
}
|
||||
}
|
||||
Port (WENB[127:0]) {
|
||||
Function : GroupWriteEnable;
|
||||
BitsPerWriteEnable: 1;
|
||||
LogicalPort : B;
|
||||
Polarity : ActiveLow;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TWENB[127:0];
|
||||
TestOutput : WENYB[127:0];
|
||||
}
|
||||
}
|
||||
Port (CENB) {
|
||||
Function : WriteEnable;
|
||||
LogicalPort : B;
|
||||
Polarity : ActiveLow;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TCENB;
|
||||
TestOutput : CENYB;
|
||||
}
|
||||
}
|
||||
Port (TENB) {
|
||||
Function : BISTOn;
|
||||
Direction : Input;
|
||||
LogicalPort : B;
|
||||
Polarity : ActiveLow;
|
||||
}
|
||||
Port (CLKB) {
|
||||
Function : Clock;
|
||||
LogicalPort : B;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (EMAB[2:0]) {
|
||||
Function : None;
|
||||
SafeValue : 0;
|
||||
Direction : Input;
|
||||
LogicalPort : B;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (COLLDISN) {
|
||||
Function : None;
|
||||
SafeValue : 1;
|
||||
Direction : Input;
|
||||
Polarity : ActiveLow;
|
||||
}
|
||||
port (SEB){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 0;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SIB[1:0]){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 0;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SOB[1:0]){
|
||||
Function : None;
|
||||
Direction : Output;
|
||||
}
|
||||
port (RET1N){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 1;
|
||||
Polarity : Activelow;
|
||||
}
|
||||
}
|
||||
2459
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.tv
Normal file
2459
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.tv
Normal file
File diff suppressed because it is too large
Load Diff
30207
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v
Normal file
30207
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v
Normal file
File diff suppressed because it is too large
Load Diff
1137
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_antenna.clf
Normal file
1137
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_antenna.clf
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,162 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:45:53 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_128x128_wm1
|
||||
# Number of Words: 128
|
||||
# Number of Bits: 128
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: on
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: avm
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# avm_memcomp Version: 2.1.1-EAC
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
rf2_128x128_wm1 {
|
||||
MEMORY_TYPE RegFile
|
||||
EQUIV_GATE_COUNT 18022
|
||||
VDD_PIN VDDCE VDDPE
|
||||
GND_PIN VSSE
|
||||
#This file is for PROCESS FF, CORNER FF_0P99V_0P99V_125C
|
||||
#However, RedHawk needs the process to be specified as 'PROCESS XX'
|
||||
PROCESS XX
|
||||
Cload 3.5e-05nF
|
||||
VDD 0.99 0.99
|
||||
|
||||
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
|
||||
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
|
||||
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
|
||||
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
|
||||
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
|
||||
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
|
||||
|
||||
Cpd avm_into_lowpwr {
|
||||
VDDCE VSSE 1.02612e-04nF
|
||||
VDDPE VSSE 6.12732e-04nF
|
||||
}
|
||||
PEAK_I avm_into_lowpwr {
|
||||
VDDCE VSSE 3.08056mA
|
||||
VDDPE VSSE 8.89592mA
|
||||
}
|
||||
Cpd avm_outof_lowpwr {
|
||||
VDDCE VSSE 1.12874e-04nF
|
||||
VDDPE VSSE 1.10761e-02nF
|
||||
}
|
||||
PEAK_I avm_outof_lowpwr {
|
||||
VDDCE VSSE 3.38862mA
|
||||
VDDPE VSSE 96.55176mA
|
||||
}
|
||||
Cpd avm_read_write {
|
||||
VDDCE VSSE 3.50286e-04nF
|
||||
VDDPE VSSE 9.97299e-03nF
|
||||
}
|
||||
PEAK_I avm_read_write {
|
||||
VDDCE VSSE 8.09467mA
|
||||
VDDPE VSSE 101.37935mA
|
||||
}
|
||||
Cpd avm_read_desel {
|
||||
VDDCE VSSE 1.00598e-04nF
|
||||
VDDPE VSSE 4.46207e-03nF
|
||||
}
|
||||
PEAK_I avm_read_desel {
|
||||
VDDCE VSSE 2.28932mA
|
||||
VDDPE VSSE 60.92520mA
|
||||
}
|
||||
Cpd avm_desel_write {
|
||||
VDDCE VSSE 2.49688e-04nF
|
||||
VDDPE VSSE 5.51093e-03nF
|
||||
}
|
||||
PEAK_I avm_desel_write {
|
||||
VDDCE VSSE 5.32434mA
|
||||
VDDPE VSSE 89.27310mA
|
||||
}
|
||||
Cpd avm_scan_capture {
|
||||
VDDCE VSSE 8.09457e-06nF
|
||||
VDDPE VSSE 1.07376e-02nF
|
||||
}
|
||||
PEAK_I avm_scan_capture {
|
||||
VDDCE VSSE 0.43640mA
|
||||
VDDPE VSSE 39.07064mA
|
||||
}
|
||||
Cpd avm_scan_shift {
|
||||
VDDCE VSSE 8.09457e-06nF
|
||||
VDDPE VSSE 1.07376e-02nF
|
||||
}
|
||||
PEAK_I avm_scan_shift {
|
||||
VDDCE VSSE 0.43640mA
|
||||
VDDPE VSSE 39.07064mA
|
||||
}
|
||||
Cpd standby_trig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.95501e-05nF
|
||||
}
|
||||
Cpd standby_ntrig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 2.17223e-05nF
|
||||
}
|
||||
LEAKAGE_I {
|
||||
VDDCE VSSE 0.89726mA
|
||||
VDDPE VSSE 1.79810mA
|
||||
}
|
||||
tsu 0.102996ns
|
||||
ck2q_delay 0.553048ns
|
||||
tr_q 0.013743ns
|
||||
tf_q 0.015878ns
|
||||
CHARACTERIZATION_MODE accurate
|
||||
}
|
||||
@@ -0,0 +1,334 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:46:18 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_128x128_wm1
|
||||
# Number of Words: 128
|
||||
# Number of Bits: 128
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: on
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: datatable
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# datatable_memcomp Version: 1.3.0-amci
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
# Units used in Datatable :
|
||||
# geomx: micron
|
||||
# geomy: micron
|
||||
# Voltage: volts
|
||||
# Temprature: Degree Celsius
|
||||
# Current: mA
|
||||
# Time: ns
|
||||
#
|
||||
name ff_0p99v_0p99v_125c
|
||||
S N
|
||||
geomx 34.1250
|
||||
geomy 414.8600
|
||||
volt 0.9900
|
||||
temp 125.0000
|
||||
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
|
||||
tcenacenya 0.0917
|
||||
ttcenacenya 0.0905
|
||||
ttenacenyapu 0.1191
|
||||
ttenacenyanu 0.1400
|
||||
tdftrambypcenya 0.1299
|
||||
taaaya 0.0751
|
||||
ttaaaya 0.0751
|
||||
ttenaayapu 0.1377
|
||||
ttenaayanu 0.1338
|
||||
tdftrambypaya 0.1197
|
||||
tcenbcenyb 0.0947
|
||||
ttcenbcenyb 0.0939
|
||||
ttenbcenybpu 0.1236
|
||||
ttenbcenybnu 0.1996
|
||||
tdftrambypcenyb 0.1226
|
||||
twenbwenyb 0.0927
|
||||
ttwenbwenyb 0.0930
|
||||
ttenbwenybpu 0.2539
|
||||
ttenbwenybnu 0.2667
|
||||
tdftrambypwenyb 0.1651
|
||||
tabayb 0.0753
|
||||
ttabayb 0.0779
|
||||
ttenbaybpu 0.1929
|
||||
ttenbaybnu 0.1969
|
||||
tdftrambypayb 0.1194
|
||||
taccqa_rd0 0.5372
|
||||
taccqa_rd1 0.5462
|
||||
taccqa_rd2 0.5490
|
||||
taccqa_rd3 0.5530
|
||||
taccqa_rd4 0.5979
|
||||
taccqa_rd5 0.6317
|
||||
taccqa_rd6 0.6718
|
||||
taccqa_rd7 0.7078
|
||||
taccqa_scan0 0.5372
|
||||
taccqa_scan1 0.5462
|
||||
taccqa_scan2 0.5490
|
||||
taccqa_scan3 0.5530
|
||||
taccqa_scan4 0.5979
|
||||
taccqa_scan5 0.6317
|
||||
taccqa_scan6 0.6718
|
||||
taccqa_scan7 0.7078
|
||||
tclkasoa_rd0 0.5506
|
||||
tclkasoa_rd1 0.5596
|
||||
tclkasoa_rd2 0.5624
|
||||
tclkasoa_rd3 0.5665
|
||||
tclkasoa_rd4 0.6114
|
||||
tclkasoa_rd5 0.6452
|
||||
tclkasoa_rd6 0.6853
|
||||
tclkasoa_rd7 0.7213
|
||||
tclkasoa_scan0 0.5506
|
||||
tclkasoa_scan1 0.5596
|
||||
tclkasoa_scan2 0.5624
|
||||
tclkasoa_scan3 0.5665
|
||||
tclkasoa_scan4 0.6114
|
||||
tclkasoa_scan5 0.6452
|
||||
tclkasoa_scan6 0.6853
|
||||
tclkasoa_scan7 0.7213
|
||||
tclkbsob 0.2290
|
||||
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
|
||||
kload_cenya 1.7116
|
||||
kload_aya 1.4236
|
||||
kload_cenyb 1.6712
|
||||
kload_wenyb 1.4498
|
||||
kload_ayb 1.4006
|
||||
kload_qa 0.5053
|
||||
kload_soa 1.3720
|
||||
kload_sob 1.4400
|
||||
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
|
||||
tcyca_ema0 0.7585
|
||||
tcyca_ema1 0.7676
|
||||
tcyca_ema2 0.7705
|
||||
tcyca_ema3 0.7746
|
||||
tcyca_ema4 0.8201
|
||||
tcyca_ema5 0.8545
|
||||
tcyca_ema6 0.8951
|
||||
tcyca_ema7 0.9317
|
||||
tcycb_ema0 0.8745
|
||||
tcycb_ema1 0.9245
|
||||
tcycb_ema2 0.9393
|
||||
tcycb_ema3 0.9716
|
||||
tcycb_ema4 1.0232
|
||||
tcycb_ema5 1.0589
|
||||
tcycb_ema6 1.1078
|
||||
tcycb_ema7 1.1429
|
||||
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
|
||||
tcracwb_rd0 0.5419
|
||||
tcracwb_rd1 0.5509
|
||||
tcracwb_rd2 0.5537
|
||||
tcracwb_rd3 0.5577
|
||||
tcracwb_rd4 0.6026
|
||||
tcracwb_rd5 0.6364
|
||||
tcracwb_rd6 0.6765
|
||||
tcracwb_rd7 0.7125
|
||||
tcwbcra_wr0 0.6577
|
||||
tcwbcra_wr1 0.7069
|
||||
tcwbcra_wr2 0.7215
|
||||
tcwbcra_wr3 0.7533
|
||||
tcwbcra_wr4 0.8041
|
||||
tcwbcra_wr5 0.8394
|
||||
tcwbcra_wr6 0.8875
|
||||
tcwbcra_wr7 0.9221
|
||||
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
|
||||
tckah 0.0927
|
||||
tckal 0.0899
|
||||
tckbh 0.0959
|
||||
tckbl 0.0907
|
||||
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
|
||||
tcenas 0.0902
|
||||
taas 0.1030
|
||||
tcenbs 0.0963
|
||||
twenbs 0.0150
|
||||
tabs 0.1100
|
||||
tdbs 0.0228
|
||||
temaas 0.7999
|
||||
temasas 0.7999
|
||||
temabs 0.9969
|
||||
ttenas 0.1840
|
||||
ttcenas 0.0905
|
||||
ttaas 0.1051
|
||||
ttenbs 0.3881
|
||||
ttcenbs 0.0968
|
||||
ttwenbs 0.0151
|
||||
ttabs 0.1137
|
||||
ttdbs 0.0237
|
||||
tsias 0.2024
|
||||
tseas 0.2024
|
||||
tdftrambypas 0.2266
|
||||
tdftrambypbs 0.2266
|
||||
tsibs 0.0228
|
||||
tsebs 0.3881
|
||||
tcolldisnas 0.7999
|
||||
tcolldisnbs 0.9969
|
||||
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
|
||||
tcenah 0.0403
|
||||
tcenaf_ret1nfh 1.0066
|
||||
tcenaf_ret1nrh 0.3610
|
||||
taah 0.0702
|
||||
tcenbh 0.0423
|
||||
tcenbf_ret1nfh 1.0066
|
||||
tcenbf_ret1nrh 0.3610
|
||||
twenbh 0.1736
|
||||
tabh 0.0649
|
||||
tdbh 0.1710
|
||||
temaah 1.0210
|
||||
temasah 1.0210
|
||||
temabh 1.1778
|
||||
ttenah 0.0772
|
||||
ttcenah 0.0416
|
||||
ttcenaf_ret1nfh 1.0066
|
||||
ttcenaf_ret1nrh 0.3610
|
||||
ttaah 0.0702
|
||||
ttenbh 0.1918
|
||||
ttcenbh 0.0436
|
||||
ttcenbf_ret1nfh 1.0066
|
||||
ttcenbf_ret1nrh 0.3610
|
||||
ttwenbh 0.1743
|
||||
ttabh 0.0649
|
||||
ttdbh 0.1710
|
||||
tret1nf_dftrambypfh 0.0242
|
||||
tret1nr_dftrambypfh 1.0066
|
||||
tret1nf_cenbrh 0.0242
|
||||
tret1nf_cenarh 0.0226
|
||||
tret1nf_tcenarh 0.0226
|
||||
tret1nf_tcenbrh 0.0242
|
||||
tret1nr_tcenbrh 1.0066
|
||||
tret1nr_tcenarh 0.8096
|
||||
tret1nr_cenbrh 1.0066
|
||||
tret1nr_cenarh 0.8096
|
||||
tsiah 0.0756
|
||||
tseah 1.0210
|
||||
tdftrambypah 1.0210
|
||||
tdftrambypbh 1.0066
|
||||
tdftrambypr_ret1nfh 1.0066
|
||||
tdftrambypr_ret1nrh 0.3610
|
||||
tsibh 0.1710
|
||||
tsebh 0.1918
|
||||
tcolldisnah 1.0210
|
||||
tcolldisnbh 1.1778
|
||||
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
|
||||
icap_clka 0.0105
|
||||
icap_cena 0.0018
|
||||
icap_aa 0.0012
|
||||
icap_clkb 0.0106
|
||||
icap_cenb 0.0015
|
||||
icap_wenb 0.0017
|
||||
icap_ab 0.0012
|
||||
icap_db 0.0019
|
||||
icap_emaa 0.0059
|
||||
icap_emasa 0.0021
|
||||
icap_emab 0.0057
|
||||
icap_tena 0.0010
|
||||
icap_tcena 0.0016
|
||||
icap_taa 0.0014
|
||||
icap_tenb 0.0012
|
||||
icap_tcenb 0.0016
|
||||
icap_twenb 0.0015
|
||||
icap_tab 0.0014
|
||||
icap_tdb 0.0016
|
||||
icap_sia 0.0015
|
||||
icap_sea 0.0019
|
||||
icap_dftrambyp 0.0021
|
||||
icap_sib 0.0056
|
||||
icap_seb 0.0019
|
||||
icap_colldisn 0.0024
|
||||
icap_ret1n 0.0035
|
||||
# High Density Two Port Register File SVT MVT Compiler : current specific information.
|
||||
icc_standby_c_chipdisable 0.897263
|
||||
icc_standby_p_chipdisable 1.798096
|
||||
icc_standby_c_ret1 1.033638
|
||||
icc_standby_p_ret1 0.183674
|
||||
icc_standby_c_selective_precharge 0.880166
|
||||
icc_standby_p_selective_precharge 1.478917
|
||||
icc_c_rd0_a 9.867e-05
|
||||
icc_c_rd1_a 9.873e-05
|
||||
icc_c_rd2_a 9.948e-05
|
||||
icc_c_rd3_a 9.959e-05
|
||||
icc_c_rd4_a 1.012e-04
|
||||
icc_c_rd5_a 1.022e-04
|
||||
icc_c_rd6_a 1.039e-04
|
||||
icc_c_rd7_a 1.052e-04
|
||||
icc_p_rd0_a 4.364e-03
|
||||
icc_p_rd1_a 4.405e-03
|
||||
icc_p_rd2_a 4.405e-03
|
||||
icc_p_rd3_a 4.417e-03
|
||||
icc_p_rd4_a 4.533e-03
|
||||
icc_p_rd5_a 4.575e-03
|
||||
icc_p_rd6_a 4.604e-03
|
||||
icc_p_rd7_a 4.616e-03
|
||||
icc_c_wr0_b 2.463e-04
|
||||
icc_c_wr1_b 2.463e-04
|
||||
icc_c_wr2_b 2.471e-04
|
||||
icc_c_wr3_b 2.472e-04
|
||||
icc_c_wr4_b 2.488e-04
|
||||
icc_c_wr5_b 2.498e-04
|
||||
icc_c_wr6_b 2.515e-04
|
||||
icc_c_wr7_b 2.528e-04
|
||||
icc_p_wr0_b 5.403e-03
|
||||
icc_p_wr1_b 5.444e-03
|
||||
icc_p_wr2_b 5.444e-03
|
||||
icc_p_wr3_b 5.456e-03
|
||||
icc_p_wr4_b 5.572e-03
|
||||
icc_p_wr5_b 5.613e-03
|
||||
icc_p_wr6_b 5.643e-03
|
||||
icc_p_wr7_b 5.655e-03
|
||||
icc_c_desela 0.000e+00
|
||||
icc_p_desela 8.252e-05
|
||||
icc_c_deselb 0.000e+00
|
||||
icc_p_deselb 1.180e-03
|
||||
icc_c_peak 8.094665
|
||||
icc_p_peak 101.379348
|
||||
icc_c_inrush 3.629571
|
||||
icc_p_inrush 96.55176
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
275
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_rtl.v
Normal file
275
models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1_rtl.v
Normal file
@@ -0,0 +1,275 @@
|
||||
/* verilog_rtl_memcomp Version: 4.0.5-beta11 */
|
||||
/* common_memcomp Version: 4.0.5.2-amci */
|
||||
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
|
||||
//
|
||||
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
//
|
||||
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
//
|
||||
// Use of this Software is subject to the terms and conditions of the
|
||||
// applicable license agreement with ARM Physical IP, Inc.
|
||||
// In addition, this Software is protected by patents, copyright law
|
||||
// and international treaties.
|
||||
//
|
||||
// The copyright notice(s) in this Software does not indicate actual or
|
||||
// intended publication of this Software.
|
||||
//
|
||||
// Repair Verilog RTL for High Density Two Port Register File SVT MVT Compiler
|
||||
//
|
||||
// Instance Name: rf2_128x128_wm1_rtl_top
|
||||
// Words: 128
|
||||
// User Bits: 128
|
||||
// Mux: 2
|
||||
// Drive: 6
|
||||
// Write Mask: On
|
||||
// Extra Margin Adjustment: On
|
||||
// Redundancy: off
|
||||
// Redundant Rows: 0
|
||||
// Redundant Columns: 2
|
||||
// Test Muxes On
|
||||
// Ser: none
|
||||
// Retention: on
|
||||
// Power Gating: off
|
||||
//
|
||||
// Creation Date: Sun Oct 20 14:49:15 2019
|
||||
// Version: r4p0
|
||||
//
|
||||
// Verified
|
||||
//
|
||||
// Known Bugs: None.
|
||||
//
|
||||
// Known Work Arounds: N/A
|
||||
//
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module rf2_128x128_wm1_rtl_top (
|
||||
CENYA,
|
||||
AYA,
|
||||
CENYB,
|
||||
WENYB,
|
||||
AYB,
|
||||
QA,
|
||||
SOA,
|
||||
SOB,
|
||||
CLKA,
|
||||
CENA,
|
||||
AA,
|
||||
CLKB,
|
||||
CENB,
|
||||
WENB,
|
||||
AB,
|
||||
DB,
|
||||
EMAA,
|
||||
EMASA,
|
||||
EMAB,
|
||||
TENA,
|
||||
TCENA,
|
||||
TAA,
|
||||
TENB,
|
||||
TCENB,
|
||||
TWENB,
|
||||
TAB,
|
||||
TDB,
|
||||
RET1N,
|
||||
SIA,
|
||||
SEA,
|
||||
DFTRAMBYP,
|
||||
SIB,
|
||||
SEB,
|
||||
COLLDISN
|
||||
);
|
||||
|
||||
output CENYA;
|
||||
output [6:0] AYA;
|
||||
output CENYB;
|
||||
output [127:0] WENYB;
|
||||
output [6:0] AYB;
|
||||
output [127:0] QA;
|
||||
output [1:0] SOA;
|
||||
output [1:0] SOB;
|
||||
input CLKA;
|
||||
input CENA;
|
||||
input [6:0] AA;
|
||||
input CLKB;
|
||||
input CENB;
|
||||
input [127:0] WENB;
|
||||
input [6:0] AB;
|
||||
input [127:0] DB;
|
||||
input [2:0] EMAA;
|
||||
input EMASA;
|
||||
input [2:0] EMAB;
|
||||
input TENA;
|
||||
input TCENA;
|
||||
input [6:0] TAA;
|
||||
input TENB;
|
||||
input TCENB;
|
||||
input [127:0] TWENB;
|
||||
input [6:0] TAB;
|
||||
input [127:0] TDB;
|
||||
input RET1N;
|
||||
input [1:0] SIA;
|
||||
input SEA;
|
||||
input DFTRAMBYP;
|
||||
input [1:0] SIB;
|
||||
input SEB;
|
||||
input COLLDISN;
|
||||
wire [127:0] QOA;
|
||||
wire [127:0] DIB;
|
||||
|
||||
assign QA = QOA;
|
||||
assign DIB = DB;
|
||||
rf2_128x128_wm1_fr_top u0 (
|
||||
.CENYA(CENYA),
|
||||
.AYA(AYA),
|
||||
.CENYB(CENYB),
|
||||
.WENYB(WENYB),
|
||||
.AYB(AYB),
|
||||
.QOA(QOA),
|
||||
.SOA(SOA),
|
||||
.SOB(SOB),
|
||||
.CLKA(CLKA),
|
||||
.CENA(CENA),
|
||||
.AA(AA),
|
||||
.CLKB(CLKB),
|
||||
.CENB(CENB),
|
||||
.WENB(WENB),
|
||||
.AB(AB),
|
||||
.DIB(DIB),
|
||||
.EMAA(EMAA),
|
||||
.EMASA(EMASA),
|
||||
.EMAB(EMAB),
|
||||
.TENA(TENA),
|
||||
.TCENA(TCENA),
|
||||
.TAA(TAA),
|
||||
.TENB(TENB),
|
||||
.TCENB(TCENB),
|
||||
.TWENB(TWENB),
|
||||
.TAB(TAB),
|
||||
.TDB(TDB),
|
||||
.RET1N(RET1N),
|
||||
.SIA(SIA),
|
||||
.SEA(SEA),
|
||||
.DFTRAMBYP(DFTRAMBYP),
|
||||
.SIB(SIB),
|
||||
.SEB(SEB),
|
||||
.COLLDISN(COLLDISN)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
module rf2_128x128_wm1_fr_top (
|
||||
CENYA,
|
||||
AYA,
|
||||
CENYB,
|
||||
WENYB,
|
||||
AYB,
|
||||
QOA,
|
||||
SOA,
|
||||
SOB,
|
||||
CLKA,
|
||||
CENA,
|
||||
AA,
|
||||
CLKB,
|
||||
CENB,
|
||||
WENB,
|
||||
AB,
|
||||
DIB,
|
||||
EMAA,
|
||||
EMASA,
|
||||
EMAB,
|
||||
TENA,
|
||||
TCENA,
|
||||
TAA,
|
||||
TENB,
|
||||
TCENB,
|
||||
TWENB,
|
||||
TAB,
|
||||
TDB,
|
||||
RET1N,
|
||||
SIA,
|
||||
SEA,
|
||||
DFTRAMBYP,
|
||||
SIB,
|
||||
SEB,
|
||||
COLLDISN
|
||||
);
|
||||
|
||||
output CENYA;
|
||||
output [6:0] AYA;
|
||||
output CENYB;
|
||||
output [127:0] WENYB;
|
||||
output [6:0] AYB;
|
||||
output [127:0] QOA;
|
||||
output [1:0] SOA;
|
||||
output [1:0] SOB;
|
||||
input CLKA;
|
||||
input CENA;
|
||||
input [6:0] AA;
|
||||
input CLKB;
|
||||
input CENB;
|
||||
input [127:0] WENB;
|
||||
input [6:0] AB;
|
||||
input [127:0] DIB;
|
||||
input [2:0] EMAA;
|
||||
input EMASA;
|
||||
input [2:0] EMAB;
|
||||
input TENA;
|
||||
input TCENA;
|
||||
input [6:0] TAA;
|
||||
input TENB;
|
||||
input TCENB;
|
||||
input [127:0] TWENB;
|
||||
input [6:0] TAB;
|
||||
input [127:0] TDB;
|
||||
input RET1N;
|
||||
input [1:0] SIA;
|
||||
input SEA;
|
||||
input DFTRAMBYP;
|
||||
input [1:0] SIB;
|
||||
input SEB;
|
||||
input COLLDISN;
|
||||
|
||||
wire [127:0] DB;
|
||||
wire [127:0] QA;
|
||||
|
||||
assign DB=DIB;
|
||||
assign QOA=QA;
|
||||
rf2_128x128_wm1 u0 (
|
||||
.CENYA(CENYA),
|
||||
.AYA(AYA),
|
||||
.CENYB(CENYB),
|
||||
.WENYB(WENYB),
|
||||
.AYB(AYB),
|
||||
.QA(QA),
|
||||
.SOA(SOA),
|
||||
.SOB(SOB),
|
||||
.CLKA(CLKA),
|
||||
.CENA(CENA),
|
||||
.AA(AA),
|
||||
.CLKB(CLKB),
|
||||
.CENB(CENB),
|
||||
.WENB(WENB),
|
||||
.AB(AB),
|
||||
.DB(DB),
|
||||
.EMAA(EMAA),
|
||||
.EMASA(EMASA),
|
||||
.EMAB(EMAB),
|
||||
.TENA(TENA),
|
||||
.TCENA(TCENA),
|
||||
.TAA(TAA),
|
||||
.TENB(TENB),
|
||||
.TCENB(TCENB),
|
||||
.TWENB(TWENB),
|
||||
.TAB(TAB),
|
||||
.TDB(TDB),
|
||||
.RET1N(RET1N),
|
||||
.SIA(SIA),
|
||||
.SEA(SEA),
|
||||
.DFTRAMBYP(DFTRAMBYP),
|
||||
.SIB(SIB),
|
||||
.SEB(SEB),
|
||||
.COLLDISN(COLLDISN)
|
||||
);
|
||||
|
||||
endmodule // rf2_128x128_wm1_fr_top
|
||||
|
||||
@@ -0,0 +1,162 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:45:59 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_128x128_wm1
|
||||
# Number of Words: 128
|
||||
# Number of Bits: 128
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: on
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: avm
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# avm_memcomp Version: 2.1.1-EAC
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
rf2_128x128_wm1 {
|
||||
MEMORY_TYPE RegFile
|
||||
EQUIV_GATE_COUNT 18022
|
||||
VDD_PIN VDDCE VDDPE
|
||||
GND_PIN VSSE
|
||||
#This file is for PROCESS SS, CORNER SS_0P81V_0P81V_M40C
|
||||
#However, RedHawk needs the process to be specified as 'PROCESS XX'
|
||||
PROCESS XX
|
||||
Cload 3.5e-05nF
|
||||
VDD 0.81 0.81
|
||||
|
||||
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
|
||||
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
|
||||
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
|
||||
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
|
||||
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
|
||||
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
|
||||
|
||||
Cpd avm_into_lowpwr {
|
||||
VDDCE VSSE 8.73321e-05nF
|
||||
VDDPE VSSE 5.62911e-04nF
|
||||
}
|
||||
PEAK_I avm_into_lowpwr {
|
||||
VDDCE VSSE 1.03174mA
|
||||
VDDPE VSSE 3.05451mA
|
||||
}
|
||||
Cpd avm_outof_lowpwr {
|
||||
VDDCE VSSE 9.60653e-05nF
|
||||
VDDPE VSSE 1.11025e-02nF
|
||||
}
|
||||
PEAK_I avm_outof_lowpwr {
|
||||
VDDCE VSSE 1.13492mA
|
||||
VDDPE VSSE 35.83421mA
|
||||
}
|
||||
Cpd avm_read_write {
|
||||
VDDCE VSSE 2.73427e-04nF
|
||||
VDDPE VSSE 9.30121e-03nF
|
||||
}
|
||||
PEAK_I avm_read_write {
|
||||
VDDCE VSSE 2.40131mA
|
||||
VDDPE VSSE 37.53301mA
|
||||
}
|
||||
Cpd avm_read_desel {
|
||||
VDDCE VSSE 9.86438e-05nF
|
||||
VDDPE VSSE 4.13502e-03nF
|
||||
}
|
||||
PEAK_I avm_read_desel {
|
||||
VDDCE VSSE 0.82264mA
|
||||
VDDPE VSSE 23.27139mA
|
||||
}
|
||||
Cpd avm_desel_write {
|
||||
VDDCE VSSE 1.74783e-04nF
|
||||
VDDPE VSSE 5.16619e-03nF
|
||||
}
|
||||
PEAK_I avm_desel_write {
|
||||
VDDCE VSSE 1.64015mA
|
||||
VDDPE VSSE 28.88487mA
|
||||
}
|
||||
Cpd avm_scan_capture {
|
||||
VDDCE VSSE 8.14454e-06nF
|
||||
VDDPE VSSE 9.88468e-03nF
|
||||
}
|
||||
PEAK_I avm_scan_capture {
|
||||
VDDCE VSSE 0.14129mA
|
||||
VDDPE VSSE 13.03296mA
|
||||
}
|
||||
Cpd avm_scan_shift {
|
||||
VDDCE VSSE 8.14454e-06nF
|
||||
VDDPE VSSE 9.88468e-03nF
|
||||
}
|
||||
PEAK_I avm_scan_shift {
|
||||
VDDCE VSSE 0.14129mA
|
||||
VDDPE VSSE 13.03296mA
|
||||
}
|
||||
Cpd standby_trig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.69190e-05nF
|
||||
}
|
||||
Cpd standby_ntrig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.87989e-05nF
|
||||
}
|
||||
LEAKAGE_I {
|
||||
VDDCE VSSE 7.44800e-04mA
|
||||
VDDPE VSSE 6.15800e-04mA
|
||||
}
|
||||
tsu 0.30495ns
|
||||
ck2q_delay 1.15737ns
|
||||
tr_q 0.034819ns
|
||||
tf_q 0.039764ns
|
||||
CHARACTERIZATION_MODE accurate
|
||||
}
|
||||
@@ -0,0 +1,334 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:46:22 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_128x128_wm1
|
||||
# Number of Words: 128
|
||||
# Number of Bits: 128
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: on
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: datatable
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# datatable_memcomp Version: 1.3.0-amci
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
# Units used in Datatable :
|
||||
# geomx: micron
|
||||
# geomy: micron
|
||||
# Voltage: volts
|
||||
# Temprature: Degree Celsius
|
||||
# Current: mA
|
||||
# Time: ns
|
||||
#
|
||||
name ss_0p81v_0p81v_m40c
|
||||
S N
|
||||
geomx 34.1250
|
||||
geomy 414.8600
|
||||
volt 0.8100
|
||||
temp -40.0000
|
||||
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
|
||||
tcenacenya 0.2145
|
||||
ttcenacenya 0.2108
|
||||
ttenacenyapu 0.3026
|
||||
ttenacenyanu 0.3541
|
||||
tdftrambypcenya 0.3853
|
||||
taaaya 0.2110
|
||||
ttaaaya 0.2184
|
||||
ttenaayapu 0.3904
|
||||
ttenaayanu 0.3751
|
||||
tdftrambypaya 0.3736
|
||||
tcenbcenyb 0.2113
|
||||
ttcenbcenyb 0.2108
|
||||
ttenbcenybpu 0.3045
|
||||
ttenbcenybnu 0.5445
|
||||
tdftrambypcenyb 0.3738
|
||||
twenbwenyb 0.2952
|
||||
ttwenbwenyb 0.2956
|
||||
ttenbwenybpu 0.6920
|
||||
ttenbwenybnu 0.7096
|
||||
tdftrambypwenyb 0.4014
|
||||
tabayb 0.2105
|
||||
ttabayb 0.2161
|
||||
ttenbaybpu 0.5881
|
||||
ttenbaybnu 0.5463
|
||||
tdftrambypayb 0.3669
|
||||
taccqa_rd0 1.0918
|
||||
taccqa_rd1 1.1323
|
||||
taccqa_rd2 1.1395
|
||||
taccqa_rd3 1.1574
|
||||
taccqa_rd4 1.2715
|
||||
taccqa_rd5 1.3886
|
||||
taccqa_rd6 1.5144
|
||||
taccqa_rd7 1.6367
|
||||
taccqa_scan0 1.0918
|
||||
taccqa_scan1 1.1323
|
||||
taccqa_scan2 1.1395
|
||||
taccqa_scan3 1.1574
|
||||
taccqa_scan4 1.2715
|
||||
taccqa_scan5 1.3886
|
||||
taccqa_scan6 1.5144
|
||||
taccqa_scan7 1.6367
|
||||
tclkasoa_rd0 1.1973
|
||||
tclkasoa_rd1 1.2379
|
||||
tclkasoa_rd2 1.2450
|
||||
tclkasoa_rd3 1.2630
|
||||
tclkasoa_rd4 1.3770
|
||||
tclkasoa_rd5 1.4941
|
||||
tclkasoa_rd6 1.6199
|
||||
tclkasoa_rd7 1.7422
|
||||
tclkasoa_scan0 1.1973
|
||||
tclkasoa_scan1 1.2379
|
||||
tclkasoa_scan2 1.2450
|
||||
tclkasoa_scan3 1.2630
|
||||
tclkasoa_scan4 1.3770
|
||||
tclkasoa_scan5 1.4941
|
||||
tclkasoa_scan6 1.6199
|
||||
tclkasoa_scan7 1.7422
|
||||
tclkbsob 0.5273
|
||||
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
|
||||
kload_cenya 3.3060
|
||||
kload_aya 2.7500
|
||||
kload_cenyb 3.3440
|
||||
kload_wenyb 3.0700
|
||||
kload_ayb 2.7720
|
||||
kload_qa 1.0935
|
||||
kload_soa 2.7600
|
||||
kload_sob 3.1660
|
||||
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
|
||||
tcyca_ema0 1.6357
|
||||
tcyca_ema1 1.6768
|
||||
tcyca_ema2 1.6841
|
||||
tcyca_ema3 1.7023
|
||||
tcyca_ema4 1.8181
|
||||
tcyca_ema5 1.9370
|
||||
tcyca_ema6 2.0647
|
||||
tcyca_ema7 2.1887
|
||||
tcycb_ema0 1.8156
|
||||
tcycb_ema1 1.9565
|
||||
tcycb_ema2 2.0117
|
||||
tcycb_ema3 2.1102
|
||||
tcycb_ema4 2.2402
|
||||
tcycb_ema5 2.3606
|
||||
tcycb_ema6 2.5131
|
||||
tcycb_ema7 2.6295
|
||||
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
|
||||
tcracwb_rd0 0.8953
|
||||
tcracwb_rd1 0.9358
|
||||
tcracwb_rd2 0.9430
|
||||
tcracwb_rd3 0.9609
|
||||
tcracwb_rd4 1.0750
|
||||
tcracwb_rd5 1.1921
|
||||
tcracwb_rd6 1.3178
|
||||
tcracwb_rd7 1.4401
|
||||
tcwbcra_wr0 1.2617
|
||||
tcwbcra_wr1 1.4005
|
||||
tcwbcra_wr2 1.4549
|
||||
tcwbcra_wr3 1.5519
|
||||
tcwbcra_wr4 1.6800
|
||||
tcwbcra_wr5 1.7986
|
||||
tcwbcra_wr6 1.9488
|
||||
tcwbcra_wr7 2.0636
|
||||
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
|
||||
tckah 0.1789
|
||||
tckal 0.1936
|
||||
tckbh 0.1810
|
||||
tckbl 0.1760
|
||||
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
|
||||
tcenas 0.2347
|
||||
taas 0.3049
|
||||
tcenbs 0.2335
|
||||
twenbs 0.0857
|
||||
tabs 0.3105
|
||||
tdbs 0.1681
|
||||
temaas 1.7857
|
||||
temasas 1.7857
|
||||
temabs 2.1935
|
||||
ttenas 0.4955
|
||||
ttcenas 0.2359
|
||||
ttaas 0.3136
|
||||
ttenbs 0.8276
|
||||
ttcenbs 0.2341
|
||||
ttwenbs 0.0862
|
||||
ttabs 0.3176
|
||||
ttdbs 0.1738
|
||||
tsias 0.5450
|
||||
tseas 0.5450
|
||||
tdftrambypas 0.6851
|
||||
tdftrambypbs 0.6851
|
||||
tsibs 0.1681
|
||||
tsebs 0.8276
|
||||
tcolldisnas 1.7857
|
||||
tcolldisnbs 2.1935
|
||||
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
|
||||
tcenah 0.0852
|
||||
tcenaf_ret1nfh 2.1743
|
||||
tcenaf_ret1nrh 0.8350
|
||||
taah 0.1420
|
||||
tcenbh 0.0853
|
||||
tcenbf_ret1nfh 2.1743
|
||||
tcenbf_ret1nrh 0.8350
|
||||
twenbh 0.3114
|
||||
tabh 0.1304
|
||||
tdbh 0.3013
|
||||
temaah 2.4447
|
||||
temasah 2.4447
|
||||
temabh 2.6937
|
||||
ttenah 0.1562
|
||||
ttcenah 0.0869
|
||||
ttcenaf_ret1nfh 2.1743
|
||||
ttcenaf_ret1nrh 0.8350
|
||||
ttaah 0.1420
|
||||
ttenbh 0.3425
|
||||
ttcenbh 0.0866
|
||||
ttcenbf_ret1nfh 2.1743
|
||||
ttcenbf_ret1nrh 0.8350
|
||||
ttwenbh 0.3114
|
||||
ttabh 0.1304
|
||||
ttdbh 0.3013
|
||||
tret1nf_dftrambypfh 0.0590
|
||||
tret1nr_dftrambypfh 2.1743
|
||||
tret1nf_cenbrh 0.0585
|
||||
tret1nf_cenarh 0.0590
|
||||
tret1nf_tcenarh 0.0590
|
||||
tret1nf_tcenbrh 0.0585
|
||||
tret1nr_tcenbrh 2.1743
|
||||
tret1nr_tcenarh 1.7665
|
||||
tret1nr_cenbrh 2.1743
|
||||
tret1nr_cenarh 1.7665
|
||||
tsiah 0.1246
|
||||
tseah 2.4447
|
||||
tdftrambypah 2.4447
|
||||
tdftrambypbh 2.1743
|
||||
tdftrambypr_ret1nfh 2.1743
|
||||
tdftrambypr_ret1nrh 0.8350
|
||||
tsibh 0.3013
|
||||
tsebh 0.3425
|
||||
tcolldisnah 2.4447
|
||||
tcolldisnbh 2.6937
|
||||
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
|
||||
icap_clka 0.0087
|
||||
icap_cena 0.0014
|
||||
icap_aa 0.0017
|
||||
icap_clkb 0.0088
|
||||
icap_cenb 0.0011
|
||||
icap_wenb 0.0016
|
||||
icap_ab 0.0015
|
||||
icap_db 0.0018
|
||||
icap_emaa 0.0056
|
||||
icap_emasa 0.0021
|
||||
icap_emab 0.0054
|
||||
icap_tena 0.0008
|
||||
icap_tcena 0.0012
|
||||
icap_taa 0.0016
|
||||
icap_tenb 0.0009
|
||||
icap_tcenb 0.0012
|
||||
icap_twenb 0.0014
|
||||
icap_tab 0.0014
|
||||
icap_tdb 0.0015
|
||||
icap_sia 0.0011
|
||||
icap_sea 0.0016
|
||||
icap_dftrambyp 0.0016
|
||||
icap_sib 0.0054
|
||||
icap_seb 0.0017
|
||||
icap_colldisn 0.0021
|
||||
icap_ret1n 0.0032
|
||||
# High Density Two Port Register File SVT MVT Compiler : current specific information.
|
||||
icc_standby_c_chipdisable 7.448e-04
|
||||
icc_standby_p_chipdisable 6.158e-04
|
||||
icc_standby_c_ret1 7.390e-04
|
||||
icc_standby_p_ret1 4.217e-06
|
||||
icc_standby_c_selective_precharge 7.374e-04
|
||||
icc_standby_p_selective_precharge 2.993e-04
|
||||
icc_c_rd0_a 7.956e-05
|
||||
icc_c_rd1_a 7.990e-05
|
||||
icc_c_rd2_a 7.990e-05
|
||||
icc_c_rd3_a 7.990e-05
|
||||
icc_c_rd4_a 8.153e-05
|
||||
icc_c_rd5_a 8.273e-05
|
||||
icc_c_rd6_a 8.288e-05
|
||||
icc_c_rd7_a 8.288e-05
|
||||
icc_p_rd0_a 3.278e-03
|
||||
icc_p_rd1_a 3.333e-03
|
||||
icc_p_rd2_a 3.333e-03
|
||||
icc_p_rd3_a 3.349e-03
|
||||
icc_p_rd4_a 3.423e-03
|
||||
icc_p_rd5_a 3.447e-03
|
||||
icc_p_rd6_a 3.475e-03
|
||||
icc_p_rd7_a 3.475e-03
|
||||
icc_c_wr0_b 1.412e-04
|
||||
icc_c_wr1_b 1.416e-04
|
||||
icc_c_wr2_b 1.416e-04
|
||||
icc_c_wr3_b 1.416e-04
|
||||
icc_c_wr4_b 1.432e-04
|
||||
icc_c_wr5_b 1.444e-04
|
||||
icc_c_wr6_b 1.446e-04
|
||||
icc_c_wr7_b 1.446e-04
|
||||
icc_p_wr0_b 4.113e-03
|
||||
icc_p_wr1_b 4.168e-03
|
||||
icc_p_wr2_b 4.168e-03
|
||||
icc_p_wr3_b 4.185e-03
|
||||
icc_p_wr4_b 4.258e-03
|
||||
icc_p_wr5_b 4.282e-03
|
||||
icc_p_wr6_b 4.310e-03
|
||||
icc_p_wr7_b 4.310e-03
|
||||
icc_c_desela 0.000e+00
|
||||
icc_p_desela 5.764e-05
|
||||
icc_c_deselb 0.000e+00
|
||||
icc_p_deselb 8.893e-04
|
||||
icc_c_peak 2.401311
|
||||
icc_p_peak 37.533005
|
||||
icc_c_inrush 1.111213
|
||||
icc_p_inrush 35.745719
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,162 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:46:06 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_128x128_wm1
|
||||
# Number of Words: 128
|
||||
# Number of Bits: 128
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: on
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: avm
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# avm_memcomp Version: 2.1.1-EAC
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
rf2_128x128_wm1 {
|
||||
MEMORY_TYPE RegFile
|
||||
EQUIV_GATE_COUNT 18022
|
||||
VDD_PIN VDDCE VDDPE
|
||||
GND_PIN VSSE
|
||||
#This file is for PROCESS TT, CORNER TT_0P90V_0P90V_25C
|
||||
#However, RedHawk needs the process to be specified as 'PROCESS XX'
|
||||
PROCESS XX
|
||||
Cload 3.5e-05nF
|
||||
VDD 0.9 0.9
|
||||
|
||||
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
|
||||
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
|
||||
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
|
||||
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
|
||||
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
|
||||
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
|
||||
|
||||
Cpd avm_into_lowpwr {
|
||||
VDDCE VSSE 9.28407e-05nF
|
||||
VDDPE VSSE 5.69523e-04nF
|
||||
}
|
||||
PEAK_I avm_into_lowpwr {
|
||||
VDDCE VSSE 1.89595mA
|
||||
VDDPE VSSE 5.29014mA
|
||||
}
|
||||
Cpd avm_outof_lowpwr {
|
||||
VDDCE VSSE 1.02125e-04nF
|
||||
VDDPE VSSE 1.14681e-02nF
|
||||
}
|
||||
PEAK_I avm_outof_lowpwr {
|
||||
VDDCE VSSE 2.08555mA
|
||||
VDDPE VSSE 63.53755mA
|
||||
}
|
||||
Cpd avm_read_write {
|
||||
VDDCE VSSE 3.13542e-04nF
|
||||
VDDPE VSSE 9.52395e-03nF
|
||||
}
|
||||
PEAK_I avm_read_write {
|
||||
VDDCE VSSE 4.53049mA
|
||||
VDDPE VSSE 66.71443mA
|
||||
}
|
||||
Cpd avm_read_desel {
|
||||
VDDCE VSSE 1.00162e-04nF
|
||||
VDDPE VSSE 4.27128e-03nF
|
||||
}
|
||||
PEAK_I avm_read_desel {
|
||||
VDDCE VSSE 1.38012mA
|
||||
VDDPE VSSE 39.33253mA
|
||||
}
|
||||
Cpd avm_desel_write {
|
||||
VDDCE VSSE 2.13380e-04nF
|
||||
VDDPE VSSE 5.25267e-03nF
|
||||
}
|
||||
PEAK_I avm_desel_write {
|
||||
VDDCE VSSE 3.15716mA
|
||||
VDDPE VSSE 55.27448mA
|
||||
}
|
||||
Cpd avm_scan_capture {
|
||||
VDDCE VSSE 8.56193e-06nF
|
||||
VDDPE VSSE 1.02363e-02nF
|
||||
}
|
||||
PEAK_I avm_scan_capture {
|
||||
VDDCE VSSE 0.27530mA
|
||||
VDDPE VSSE 24.42748mA
|
||||
}
|
||||
Cpd avm_scan_shift {
|
||||
VDDCE VSSE 8.56193e-06nF
|
||||
VDDPE VSSE 1.02363e-02nF
|
||||
}
|
||||
PEAK_I avm_scan_shift {
|
||||
VDDCE VSSE 0.27530mA
|
||||
VDDPE VSSE 24.42748mA
|
||||
}
|
||||
Cpd standby_trig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.77000e-05nF
|
||||
}
|
||||
Cpd standby_ntrig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.96666e-05nF
|
||||
}
|
||||
LEAKAGE_I {
|
||||
VDDCE VSSE 6.50200e-03mA
|
||||
VDDPE VSSE 1.13860e-02mA
|
||||
}
|
||||
tsu 0.145088ns
|
||||
ck2q_delay 0.68828ns
|
||||
tr_q 0.01885ns
|
||||
tf_q 0.022375ns
|
||||
CHARACTERIZATION_MODE accurate
|
||||
}
|
||||
@@ -0,0 +1,334 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:46:27 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_128x128_wm1
|
||||
# Number of Words: 128
|
||||
# Number of Bits: 128
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: on
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: datatable
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# datatable_memcomp Version: 1.3.0-amci
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
# Units used in Datatable :
|
||||
# geomx: micron
|
||||
# geomy: micron
|
||||
# Voltage: volts
|
||||
# Temprature: Degree Celsius
|
||||
# Current: mA
|
||||
# Time: ns
|
||||
#
|
||||
name tt_0p90v_0p90v_25c
|
||||
S N
|
||||
geomx 34.1250
|
||||
geomy 414.8600
|
||||
volt 0.9000
|
||||
temp 25.0000
|
||||
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
|
||||
tcenacenya 0.1187
|
||||
ttcenacenya 0.1176
|
||||
ttenacenyapu 0.1613
|
||||
ttenacenyanu 0.1885
|
||||
tdftrambypcenya 0.1900
|
||||
taaaya 0.1038
|
||||
ttaaaya 0.1082
|
||||
ttenaayapu 0.1877
|
||||
ttenaayanu 0.1835
|
||||
tdftrambypaya 0.1776
|
||||
tcenbcenyb 0.1195
|
||||
ttcenbcenyb 0.1185
|
||||
ttenbcenybpu 0.1658
|
||||
ttenbcenybnu 0.2823
|
||||
tdftrambypcenyb 0.1824
|
||||
twenbwenyb 0.1351
|
||||
ttwenbwenyb 0.1341
|
||||
ttenbwenybpu 0.3463
|
||||
ttenbwenybnu 0.3615
|
||||
tdftrambypwenyb 0.2183
|
||||
tabayb 0.1040
|
||||
ttabayb 0.1062
|
||||
ttenbaybpu 0.2796
|
||||
ttenbaybnu 0.2792
|
||||
tdftrambypayb 0.1779
|
||||
taccqa_rd0 0.6543
|
||||
taccqa_rd1 0.6758
|
||||
taccqa_rd2 0.6787
|
||||
taccqa_rd3 0.6883
|
||||
taccqa_rd4 0.7447
|
||||
taccqa_rd5 0.7988
|
||||
taccqa_rd6 0.8541
|
||||
taccqa_rd7 0.9079
|
||||
taccqa_scan0 0.6543
|
||||
taccqa_scan1 0.6758
|
||||
taccqa_scan2 0.6787
|
||||
taccqa_scan3 0.6883
|
||||
taccqa_scan4 0.7447
|
||||
taccqa_scan5 0.7988
|
||||
taccqa_scan6 0.8541
|
||||
taccqa_scan7 0.9079
|
||||
tclkasoa_rd0 0.6847
|
||||
tclkasoa_rd1 0.7062
|
||||
tclkasoa_rd2 0.7091
|
||||
tclkasoa_rd3 0.7187
|
||||
tclkasoa_rd4 0.7751
|
||||
tclkasoa_rd5 0.8292
|
||||
tclkasoa_rd6 0.8845
|
||||
tclkasoa_rd7 0.9383
|
||||
tclkasoa_scan0 0.6847
|
||||
tclkasoa_scan1 0.7062
|
||||
tclkasoa_scan2 0.7091
|
||||
tclkasoa_scan3 0.7187
|
||||
tclkasoa_scan4 0.7751
|
||||
tclkasoa_scan5 0.8292
|
||||
tclkasoa_scan6 0.8845
|
||||
tclkasoa_scan7 0.9383
|
||||
tclkbsob 0.2967
|
||||
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
|
||||
kload_cenya 2.0800
|
||||
kload_aya 1.6620
|
||||
kload_cenyb 1.9640
|
||||
kload_wenyb 1.7940
|
||||
kload_ayb 1.6740
|
||||
kload_qa 0.6365
|
||||
kload_soa 1.7020
|
||||
kload_sob 1.8420
|
||||
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
|
||||
tcyca_ema0 0.9522
|
||||
tcyca_ema1 0.9740
|
||||
tcyca_ema2 0.9769
|
||||
tcyca_ema3 0.9867
|
||||
tcyca_ema4 1.0440
|
||||
tcyca_ema5 1.0989
|
||||
tcyca_ema6 1.1550
|
||||
tcyca_ema7 1.2096
|
||||
tcycb_ema0 1.0059
|
||||
tcycb_ema1 1.0742
|
||||
tcycb_ema2 1.0979
|
||||
tcycb_ema3 1.1427
|
||||
tcycb_ema4 1.2141
|
||||
tcycb_ema5 1.2663
|
||||
tcycb_ema6 1.3352
|
||||
tcycb_ema7 1.3854
|
||||
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
|
||||
tcracwb_rd0 0.6349
|
||||
tcracwb_rd1 0.6563
|
||||
tcracwb_rd2 0.6593
|
||||
tcracwb_rd3 0.6689
|
||||
tcracwb_rd4 0.7252
|
||||
tcracwb_rd5 0.7794
|
||||
tcracwb_rd6 0.8347
|
||||
tcracwb_rd7 0.8885
|
||||
tcwbcra_wr0 0.7842
|
||||
tcwbcra_wr1 0.8515
|
||||
tcwbcra_wr2 0.8748
|
||||
tcwbcra_wr3 0.9189
|
||||
tcwbcra_wr4 0.9892
|
||||
tcwbcra_wr5 1.0406
|
||||
tcwbcra_wr6 1.1085
|
||||
tcwbcra_wr7 1.1581
|
||||
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
|
||||
tckah 0.1135
|
||||
tckal 0.1131
|
||||
tckbh 0.1160
|
||||
tckbl 0.1128
|
||||
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
|
||||
tcenas 0.1224
|
||||
taas 0.1451
|
||||
tcenbs 0.1250
|
||||
twenbs 0.0225
|
||||
tabs 0.1537
|
||||
tdbs 0.0487
|
||||
temaas 1.0264
|
||||
temasas 1.0264
|
||||
temabs 1.1825
|
||||
ttenas 0.2524
|
||||
ttcenas 0.1224
|
||||
ttaas 0.1495
|
||||
ttenbs 0.4747
|
||||
ttcenbs 0.1262
|
||||
ttwenbs 0.0225
|
||||
ttabs 0.1572
|
||||
ttdbs 0.0509
|
||||
tsias 0.2777
|
||||
tseas 0.2777
|
||||
tdftrambypas 0.3304
|
||||
tdftrambypbs 0.3304
|
||||
tsibs 0.0487
|
||||
tsebs 0.4747
|
||||
tcolldisnas 1.0264
|
||||
tcolldisnbs 1.1825
|
||||
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
|
||||
tcenah 0.0495
|
||||
tcenaf_ret1nfh 1.1859
|
||||
tcenaf_ret1nrh 0.4629
|
||||
taah 0.0840
|
||||
tcenbh 0.0496
|
||||
tcenbf_ret1nfh 1.1859
|
||||
tcenbf_ret1nrh 0.4629
|
||||
twenbh 0.2057
|
||||
tabh 0.0791
|
||||
tdbh 0.1941
|
||||
temaah 1.3375
|
||||
temasah 1.3375
|
||||
temabh 1.4286
|
||||
ttenah 0.0924
|
||||
ttcenah 0.0524
|
||||
ttcenaf_ret1nfh 1.1859
|
||||
ttcenaf_ret1nrh 0.4629
|
||||
ttaah 0.0840
|
||||
ttenbh 0.2271
|
||||
ttcenbh 0.0510
|
||||
ttcenbf_ret1nfh 1.1859
|
||||
ttcenbf_ret1nrh 0.4629
|
||||
ttwenbh 0.2065
|
||||
ttabh 0.0791
|
||||
ttdbh 0.1941
|
||||
tret1nf_dftrambypfh 0.0315
|
||||
tret1nr_dftrambypfh 1.1859
|
||||
tret1nf_cenbrh 0.0315
|
||||
tret1nf_cenarh 0.0306
|
||||
tret1nf_tcenarh 0.0306
|
||||
tret1nf_tcenbrh 0.0315
|
||||
tret1nr_tcenbrh 1.1859
|
||||
tret1nr_tcenarh 1.0299
|
||||
tret1nr_cenbrh 1.1859
|
||||
tret1nr_cenarh 1.0299
|
||||
tsiah 0.0817
|
||||
tseah 1.3375
|
||||
tdftrambypah 1.3375
|
||||
tdftrambypbh 1.1859
|
||||
tdftrambypr_ret1nfh 1.1859
|
||||
tdftrambypr_ret1nrh 0.4629
|
||||
tsibh 0.1941
|
||||
tsebh 0.2271
|
||||
tcolldisnah 1.3375
|
||||
tcolldisnbh 1.4286
|
||||
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
|
||||
icap_clka 0.0091
|
||||
icap_cena 0.0013
|
||||
icap_aa 0.0016
|
||||
icap_clkb 0.0097
|
||||
icap_cenb 0.0013
|
||||
icap_wenb 0.0014
|
||||
icap_ab 0.0016
|
||||
icap_db 0.0019
|
||||
icap_emaa 0.0058
|
||||
icap_emasa 0.0025
|
||||
icap_emab 0.0056
|
||||
icap_tena 0.0009
|
||||
icap_tcena 0.0014
|
||||
icap_taa 0.0015
|
||||
icap_tenb 0.0010
|
||||
icap_tcenb 0.0014
|
||||
icap_twenb 0.0012
|
||||
icap_tab 0.0016
|
||||
icap_tdb 0.0016
|
||||
icap_sia 0.0012
|
||||
icap_sea 0.0016
|
||||
icap_dftrambyp 0.0021
|
||||
icap_sib 0.0058
|
||||
icap_seb 0.0019
|
||||
icap_colldisn 0.0021
|
||||
icap_ret1n 0.0034
|
||||
# High Density Two Port Register File SVT MVT Compiler : current specific information.
|
||||
icc_standby_c_chipdisable 6.502e-03
|
||||
icc_standby_p_chipdisable 0.011386
|
||||
icc_standby_c_ret1 6.767e-03
|
||||
icc_standby_p_ret1 7.153e-04
|
||||
icc_standby_c_selective_precharge 6.351e-03
|
||||
icc_standby_p_selective_precharge 9.266e-03
|
||||
icc_c_rd0_a 8.934e-05
|
||||
icc_c_rd1_a 9.015e-05
|
||||
icc_c_rd2_a 9.015e-05
|
||||
icc_c_rd3_a 9.015e-05
|
||||
icc_c_rd4_a 9.237e-05
|
||||
icc_c_rd5_a 9.357e-05
|
||||
icc_c_rd6_a 9.515e-05
|
||||
icc_c_rd7_a 9.515e-05
|
||||
icc_p_rd0_a 3.756e-03
|
||||
icc_p_rd1_a 3.815e-03
|
||||
icc_p_rd2_a 3.821e-03
|
||||
icc_p_rd3_a 3.844e-03
|
||||
icc_p_rd4_a 3.951e-03
|
||||
icc_p_rd5_a 4.016e-03
|
||||
icc_p_rd6_a 4.024e-03
|
||||
icc_p_rd7_a 4.035e-03
|
||||
icc_c_wr0_b 1.912e-04
|
||||
icc_c_wr1_b 1.920e-04
|
||||
icc_c_wr2_b 1.920e-04
|
||||
icc_c_wr3_b 1.920e-04
|
||||
icc_c_wr4_b 1.943e-04
|
||||
icc_c_wr5_b 1.955e-04
|
||||
icc_c_wr6_b 1.971e-04
|
||||
icc_c_wr7_b 1.971e-04
|
||||
icc_p_wr0_b 4.639e-03
|
||||
icc_p_wr1_b 4.698e-03
|
||||
icc_p_wr2_b 4.704e-03
|
||||
icc_p_wr3_b 4.727e-03
|
||||
icc_p_wr4_b 4.834e-03
|
||||
icc_p_wr5_b 4.899e-03
|
||||
icc_p_wr6_b 4.907e-03
|
||||
icc_p_wr7_b 4.918e-03
|
||||
icc_c_desela 0.000e+00
|
||||
icc_p_desela 6.716e-05
|
||||
icc_c_deselb 0.000e+00
|
||||
icc_p_deselb 1.019e-03
|
||||
icc_c_peak 4.530492
|
||||
icc_p_peak 66.714427
|
||||
icc_c_inrush 2.342644
|
||||
icc_p_inrush 63.53755
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
257
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.bitmap
Normal file
257
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.bitmap
Normal file
File diff suppressed because one or more lines are too long
69
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.cpf
Normal file
69
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.cpf
Normal file
File diff suppressed because one or more lines are too long
1330
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.ctl
Normal file
1330
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.ctl
Normal file
File diff suppressed because it is too large
Load Diff
36718
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.lef
Normal file
36718
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.lef
Normal file
File diff suppressed because it is too large
Load Diff
2779
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.mdt
Normal file
2779
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.mdt
Normal file
File diff suppressed because it is too large
Load Diff
360
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.memlib
Normal file
360
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.memlib
Normal file
@@ -0,0 +1,360 @@
|
||||
/* logicvision_memcomp Version: c0.1.2-beta */
|
||||
/* common_memcomp Version: c0.1.0-EAC */
|
||||
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
|
||||
//
|
||||
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
//
|
||||
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
//
|
||||
// Use of this Software is subject to the terms and conditions of the
|
||||
// applicable license agreement with ARM Physical IP, Inc.
|
||||
// In addition, this Software is protected by patents, copyright law
|
||||
// and international treaties.
|
||||
//
|
||||
// The copyright notice(s) in this Software does not indicate actual or
|
||||
// intended publication of this Software.
|
||||
//
|
||||
// logicvision model for High Density Two Port Register File SVT MVT Compiler
|
||||
//
|
||||
// Instance Name: rf2_256x128_wm1
|
||||
// Words: 256
|
||||
// Bits: 128
|
||||
// Mux: 2
|
||||
// Drive: 6
|
||||
// Write Mask: On
|
||||
// Extra Margin Adjustment: On
|
||||
// Redundant Rows: 0
|
||||
// Redundant Columns: 2
|
||||
// Test Muxes On
|
||||
//
|
||||
// Creation Date: Sun Oct 20 14:37:44 2019
|
||||
// Version: r4p0
|
||||
//
|
||||
// Modeling Assumptions:
|
||||
//
|
||||
// Modeling Limitations: None
|
||||
//
|
||||
// Known Bugs: None.
|
||||
//
|
||||
// Known Work Arounds: N/A
|
||||
//
|
||||
MemoryTemplate (rf2_256x128_wm1) {
|
||||
Algorithm : SmarchChkbvcd;
|
||||
DataOutStage : None;
|
||||
LogicalPorts : 1R1W;
|
||||
BitGrouping : 1;
|
||||
MemoryType : SRAM;
|
||||
MinHold : 0.5;
|
||||
OperationSet : SyncWRvcd;
|
||||
SelectDuringWriteThru : Off;
|
||||
ShadowRead : On;
|
||||
ShadowWrite : On;
|
||||
TransparentMode : None;
|
||||
ObservationLogic: On;
|
||||
InternalScanLogic: On;
|
||||
CellName : rf2_256x128_wm1;
|
||||
NumberOfWords : 256;
|
||||
AddressCounter{
|
||||
Function (Address) {
|
||||
LogicalAddressMap{
|
||||
ColumnAddress[0] : Address[0];
|
||||
RowAddress[6:0] : Address[7:1];
|
||||
}
|
||||
}
|
||||
Function (ColumnAddress) {
|
||||
CountRange [0:1];
|
||||
}
|
||||
Function (RowAddress) {
|
||||
CountRange [0:127];
|
||||
}
|
||||
}
|
||||
PhysicalAddressMap{
|
||||
ColumnAddress[0] : c[0];
|
||||
RowAddress[0] : r[0];
|
||||
RowAddress[1] : r[1];
|
||||
RowAddress[2] : r[2];
|
||||
RowAddress[3] : r[3];
|
||||
RowAddress[4] : r[4];
|
||||
RowAddress[5] : r[5];
|
||||
RowAddress[6] : r[6];
|
||||
}
|
||||
PhysicalDataMap{
|
||||
Data[0] : NOT d[0];
|
||||
Data[1] : NOT d[1];
|
||||
Data[2] : NOT d[2];
|
||||
Data[3] : NOT d[3];
|
||||
Data[4] : NOT d[4];
|
||||
Data[5] : NOT d[5];
|
||||
Data[6] : NOT d[6];
|
||||
Data[7] : NOT d[7];
|
||||
Data[8] : NOT d[8];
|
||||
Data[9] : NOT d[9];
|
||||
Data[10] : NOT d[10];
|
||||
Data[11] : NOT d[11];
|
||||
Data[12] : NOT d[12];
|
||||
Data[13] : NOT d[13];
|
||||
Data[14] : NOT d[14];
|
||||
Data[15] : NOT d[15];
|
||||
Data[16] : NOT d[16];
|
||||
Data[17] : NOT d[17];
|
||||
Data[18] : NOT d[18];
|
||||
Data[19] : NOT d[19];
|
||||
Data[20] : NOT d[20];
|
||||
Data[21] : NOT d[21];
|
||||
Data[22] : NOT d[22];
|
||||
Data[23] : NOT d[23];
|
||||
Data[24] : NOT d[24];
|
||||
Data[25] : NOT d[25];
|
||||
Data[26] : NOT d[26];
|
||||
Data[27] : NOT d[27];
|
||||
Data[28] : NOT d[28];
|
||||
Data[29] : NOT d[29];
|
||||
Data[30] : NOT d[30];
|
||||
Data[31] : NOT d[31];
|
||||
Data[32] : NOT d[32];
|
||||
Data[33] : NOT d[33];
|
||||
Data[34] : NOT d[34];
|
||||
Data[35] : NOT d[35];
|
||||
Data[36] : NOT d[36];
|
||||
Data[37] : NOT d[37];
|
||||
Data[38] : NOT d[38];
|
||||
Data[39] : NOT d[39];
|
||||
Data[40] : NOT d[40];
|
||||
Data[41] : NOT d[41];
|
||||
Data[42] : NOT d[42];
|
||||
Data[43] : NOT d[43];
|
||||
Data[44] : NOT d[44];
|
||||
Data[45] : NOT d[45];
|
||||
Data[46] : NOT d[46];
|
||||
Data[47] : NOT d[47];
|
||||
Data[48] : NOT d[48];
|
||||
Data[49] : NOT d[49];
|
||||
Data[50] : NOT d[50];
|
||||
Data[51] : NOT d[51];
|
||||
Data[52] : NOT d[52];
|
||||
Data[53] : NOT d[53];
|
||||
Data[54] : NOT d[54];
|
||||
Data[55] : NOT d[55];
|
||||
Data[56] : NOT d[56];
|
||||
Data[57] : NOT d[57];
|
||||
Data[58] : NOT d[58];
|
||||
Data[59] : NOT d[59];
|
||||
Data[60] : NOT d[60];
|
||||
Data[61] : NOT d[61];
|
||||
Data[62] : NOT d[62];
|
||||
Data[63] : NOT d[63];
|
||||
Data[64] : d[64];
|
||||
Data[65] : d[65];
|
||||
Data[66] : d[66];
|
||||
Data[67] : d[67];
|
||||
Data[68] : d[68];
|
||||
Data[69] : d[69];
|
||||
Data[70] : d[70];
|
||||
Data[71] : d[71];
|
||||
Data[72] : d[72];
|
||||
Data[73] : d[73];
|
||||
Data[74] : d[74];
|
||||
Data[75] : d[75];
|
||||
Data[76] : d[76];
|
||||
Data[77] : d[77];
|
||||
Data[78] : d[78];
|
||||
Data[79] : d[79];
|
||||
Data[80] : d[80];
|
||||
Data[81] : d[81];
|
||||
Data[82] : d[82];
|
||||
Data[83] : d[83];
|
||||
Data[84] : d[84];
|
||||
Data[85] : d[85];
|
||||
Data[86] : d[86];
|
||||
Data[87] : d[87];
|
||||
Data[88] : d[88];
|
||||
Data[89] : d[89];
|
||||
Data[90] : d[90];
|
||||
Data[91] : d[91];
|
||||
Data[92] : d[92];
|
||||
Data[93] : d[93];
|
||||
Data[94] : d[94];
|
||||
Data[95] : d[95];
|
||||
Data[96] : d[96];
|
||||
Data[97] : d[97];
|
||||
Data[98] : d[98];
|
||||
Data[99] : d[99];
|
||||
Data[100] : d[100];
|
||||
Data[101] : d[101];
|
||||
Data[102] : d[102];
|
||||
Data[103] : d[103];
|
||||
Data[104] : d[104];
|
||||
Data[105] : d[105];
|
||||
Data[106] : d[106];
|
||||
Data[107] : d[107];
|
||||
Data[108] : d[108];
|
||||
Data[109] : d[109];
|
||||
Data[110] : d[110];
|
||||
Data[111] : d[111];
|
||||
Data[112] : d[112];
|
||||
Data[113] : d[113];
|
||||
Data[114] : d[114];
|
||||
Data[115] : d[115];
|
||||
Data[116] : d[116];
|
||||
Data[117] : d[117];
|
||||
Data[118] : d[118];
|
||||
Data[119] : d[119];
|
||||
Data[120] : d[120];
|
||||
Data[121] : d[121];
|
||||
Data[122] : d[122];
|
||||
Data[123] : d[123];
|
||||
Data[124] : d[124];
|
||||
Data[125] : d[125];
|
||||
Data[126] : d[126];
|
||||
Data[127] : d[127];
|
||||
}
|
||||
Port (AA[7:0]) {
|
||||
Function : Address;
|
||||
LogicalPort : A;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TAA[7:0];
|
||||
TestOutput : AYA[7:0];
|
||||
}
|
||||
}
|
||||
Port (QA[127:0]) {
|
||||
Function : Data;
|
||||
Direction : output;
|
||||
LogicalPort : A;
|
||||
}
|
||||
Port (CENA) {
|
||||
Function : ReadEnable;
|
||||
LogicalPort : A;
|
||||
Polarity : ActiveLow;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TCENA;
|
||||
TestOutput : CENYA;
|
||||
}
|
||||
}
|
||||
Port (TENA) {
|
||||
Function : BISTOn;
|
||||
Direction : Input;
|
||||
LogicalPort : A;
|
||||
Polarity : ActiveLow;
|
||||
}
|
||||
Port (CLKA) {
|
||||
Function : Clock;
|
||||
LogicalPort : A;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (EMAA[2:0]) {
|
||||
Function : None;
|
||||
SafeValue : 0;
|
||||
Direction : Input;
|
||||
LogicalPort : A;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (EMASA) {
|
||||
Function : None;
|
||||
SafeValue : 0;
|
||||
Direction : Input;
|
||||
LogicalPort : A;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SEA){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 0;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SIA[1:0]){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 0;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SOA[1:0]){
|
||||
Function : None;
|
||||
Direction : Output;
|
||||
}
|
||||
port (DFTRAMBYP){
|
||||
Function : ScanTest;
|
||||
Direction : Input;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (AB[7:0]) {
|
||||
Function : Address;
|
||||
LogicalPort : B;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TAB[7:0];
|
||||
TestOutput : AYB[7:0];
|
||||
}
|
||||
}
|
||||
Port (DB[127:0]) {
|
||||
Function : Data;
|
||||
Direction : input;
|
||||
LogicalPort : B;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TDB[127:0];
|
||||
}
|
||||
}
|
||||
Port (WENB[127:0]) {
|
||||
Function : GroupWriteEnable;
|
||||
BitsPerWriteEnable: 1;
|
||||
LogicalPort : B;
|
||||
Polarity : ActiveLow;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TWENB[127:0];
|
||||
TestOutput : WENYB[127:0];
|
||||
}
|
||||
}
|
||||
Port (CENB) {
|
||||
Function : WriteEnable;
|
||||
LogicalPort : B;
|
||||
Polarity : ActiveLow;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TCENB;
|
||||
TestOutput : CENYB;
|
||||
}
|
||||
}
|
||||
Port (TENB) {
|
||||
Function : BISTOn;
|
||||
Direction : Input;
|
||||
LogicalPort : B;
|
||||
Polarity : ActiveLow;
|
||||
}
|
||||
Port (CLKB) {
|
||||
Function : Clock;
|
||||
LogicalPort : B;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (EMAB[2:0]) {
|
||||
Function : None;
|
||||
SafeValue : 0;
|
||||
Direction : Input;
|
||||
LogicalPort : B;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (COLLDISN) {
|
||||
Function : None;
|
||||
SafeValue : 1;
|
||||
Direction : Input;
|
||||
Polarity : ActiveLow;
|
||||
}
|
||||
port (SEB){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 0;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SIB[1:0]){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 0;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SOB[1:0]){
|
||||
Function : None;
|
||||
Direction : Output;
|
||||
}
|
||||
port (RET1N){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 1;
|
||||
Polarity : Activelow;
|
||||
}
|
||||
}
|
||||
2483
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.tv
Normal file
2483
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.tv
Normal file
File diff suppressed because it is too large
Load Diff
30335
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v
Normal file
30335
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v
Normal file
File diff suppressed because it is too large
Load Diff
1145
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_antenna.clf
Normal file
1145
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_antenna.clf
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,162 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:34:36 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_256x128_wm1
|
||||
# Number of Words: 256
|
||||
# Number of Bits: 128
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: on
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: avm
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# avm_memcomp Version: 2.1.1-EAC
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
rf2_256x128_wm1 {
|
||||
MEMORY_TYPE RegFile
|
||||
EQUIV_GATE_COUNT 36045
|
||||
VDD_PIN VDDCE VDDPE
|
||||
GND_PIN VSSE
|
||||
#This file is for PROCESS FF, CORNER FF_0P99V_0P99V_125C
|
||||
#However, RedHawk needs the process to be specified as 'PROCESS XX'
|
||||
PROCESS XX
|
||||
Cload 3.5e-05nF
|
||||
VDD 0.99 0.99
|
||||
|
||||
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
|
||||
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
|
||||
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
|
||||
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
|
||||
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
|
||||
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
|
||||
|
||||
Cpd avm_into_lowpwr {
|
||||
VDDCE VSSE 1.60894e-04nF
|
||||
VDDPE VSSE 6.29227e-04nF
|
||||
}
|
||||
PEAK_I avm_into_lowpwr {
|
||||
VDDCE VSSE 4.02515mA
|
||||
VDDPE VSSE 9.87592mA
|
||||
}
|
||||
Cpd avm_outof_lowpwr {
|
||||
VDDCE VSSE 1.76983e-04nF
|
||||
VDDPE VSSE 2.00800e-02nF
|
||||
}
|
||||
PEAK_I avm_outof_lowpwr {
|
||||
VDDCE VSSE 4.42767mA
|
||||
VDDPE VSSE 157.25220mA
|
||||
}
|
||||
Cpd avm_read_write {
|
||||
VDDCE VSSE 3.67895e-04nF
|
||||
VDDPE VSSE 1.19867e-02nF
|
||||
}
|
||||
PEAK_I avm_read_write {
|
||||
VDDCE VSSE 10.77517mA
|
||||
VDDPE VSSE 165.11481mA
|
||||
}
|
||||
Cpd avm_read_desel {
|
||||
VDDCE VSSE 1.15700e-04nF
|
||||
VDDPE VSSE 5.15571e-03nF
|
||||
}
|
||||
PEAK_I avm_read_desel {
|
||||
VDDCE VSSE 3.18528mA
|
||||
VDDPE VSSE 68.18280mA
|
||||
}
|
||||
Cpd avm_desel_write {
|
||||
VDDCE VSSE 2.52195e-04nF
|
||||
VDDPE VSSE 6.83102e-03nF
|
||||
}
|
||||
PEAK_I avm_desel_write {
|
||||
VDDCE VSSE 8.13593mA
|
||||
VDDPE VSSE 101.54025mA
|
||||
}
|
||||
Cpd avm_scan_capture {
|
||||
VDDCE VSSE 8.09457e-06nF
|
||||
VDDPE VSSE 1.07376e-02nF
|
||||
}
|
||||
PEAK_I avm_scan_capture {
|
||||
VDDCE VSSE 0.43640mA
|
||||
VDDPE VSSE 39.07064mA
|
||||
}
|
||||
Cpd avm_scan_shift {
|
||||
VDDCE VSSE 8.09457e-06nF
|
||||
VDDPE VSSE 1.07376e-02nF
|
||||
}
|
||||
PEAK_I avm_scan_shift {
|
||||
VDDCE VSSE 0.43640mA
|
||||
VDDPE VSSE 39.07064mA
|
||||
}
|
||||
Cpd standby_trig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.95501e-05nF
|
||||
}
|
||||
Cpd standby_ntrig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 2.17223e-05nF
|
||||
}
|
||||
LEAKAGE_I {
|
||||
VDDCE VSSE 1.76745mA
|
||||
VDDPE VSSE 2.45881mA
|
||||
}
|
||||
tsu 0.105188ns
|
||||
ck2q_delay 0.580755ns
|
||||
tr_q 0.013792ns
|
||||
tf_q 0.015916ns
|
||||
CHARACTERIZATION_MODE accurate
|
||||
}
|
||||
@@ -0,0 +1,334 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:35:01 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_256x128_wm1
|
||||
# Number of Words: 256
|
||||
# Number of Bits: 128
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: on
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: datatable
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# datatable_memcomp Version: 1.3.0-amci
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
# Units used in Datatable :
|
||||
# geomx: micron
|
||||
# geomy: micron
|
||||
# Voltage: volts
|
||||
# Temprature: Degree Celsius
|
||||
# Current: mA
|
||||
# Time: ns
|
||||
#
|
||||
name ff_0p99v_0p99v_125c
|
||||
S N
|
||||
geomx 51.4050
|
||||
geomy 414.8600
|
||||
volt 0.9900
|
||||
temp 125.0000
|
||||
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
|
||||
tcenacenya 0.0917
|
||||
ttcenacenya 0.0905
|
||||
ttenacenyapu 0.1191
|
||||
ttenacenyanu 0.1400
|
||||
tdftrambypcenya 0.1299
|
||||
taaaya 0.0751
|
||||
ttaaaya 0.0751
|
||||
ttenaayapu 0.1377
|
||||
ttenaayanu 0.1338
|
||||
tdftrambypaya 0.1197
|
||||
tcenbcenyb 0.0947
|
||||
ttcenbcenyb 0.0939
|
||||
ttenbcenybpu 0.1236
|
||||
ttenbcenybnu 0.1996
|
||||
tdftrambypcenyb 0.1226
|
||||
twenbwenyb 0.0927
|
||||
ttwenbwenyb 0.0930
|
||||
ttenbwenybpu 0.2539
|
||||
ttenbwenybnu 0.2667
|
||||
tdftrambypwenyb 0.1651
|
||||
tabayb 0.0753
|
||||
ttabayb 0.0779
|
||||
ttenbaybpu 0.1929
|
||||
ttenbaybnu 0.1969
|
||||
tdftrambypayb 0.1194
|
||||
taccqa_rd0 0.5539
|
||||
taccqa_rd1 0.5691
|
||||
taccqa_rd2 0.5750
|
||||
taccqa_rd3 0.5808
|
||||
taccqa_rd4 0.6241
|
||||
taccqa_rd5 0.6590
|
||||
taccqa_rd6 0.7002
|
||||
taccqa_rd7 0.7351
|
||||
taccqa_scan0 0.5539
|
||||
taccqa_scan1 0.5691
|
||||
taccqa_scan2 0.5750
|
||||
taccqa_scan3 0.5808
|
||||
taccqa_scan4 0.6241
|
||||
taccqa_scan5 0.6590
|
||||
taccqa_scan6 0.7002
|
||||
taccqa_scan7 0.7351
|
||||
tclkasoa_rd0 0.5668
|
||||
tclkasoa_rd1 0.5820
|
||||
tclkasoa_rd2 0.5879
|
||||
tclkasoa_rd3 0.5936
|
||||
tclkasoa_rd4 0.6370
|
||||
tclkasoa_rd5 0.6719
|
||||
tclkasoa_rd6 0.7131
|
||||
tclkasoa_rd7 0.7480
|
||||
tclkasoa_scan0 0.5668
|
||||
tclkasoa_scan1 0.5820
|
||||
tclkasoa_scan2 0.5879
|
||||
tclkasoa_scan3 0.5936
|
||||
tclkasoa_scan4 0.6370
|
||||
tclkasoa_scan5 0.6719
|
||||
tclkasoa_scan6 0.7131
|
||||
tclkasoa_scan7 0.7480
|
||||
tclkbsob 0.2292
|
||||
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
|
||||
kload_cenya 1.7116
|
||||
kload_aya 1.4236
|
||||
kload_cenyb 1.6712
|
||||
kload_wenyb 1.4498
|
||||
kload_ayb 1.4006
|
||||
kload_qa 0.5053
|
||||
kload_soa 1.3720
|
||||
kload_sob 1.4400
|
||||
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
|
||||
tcyca_ema0 0.7742
|
||||
tcyca_ema1 0.7897
|
||||
tcyca_ema2 0.7957
|
||||
tcyca_ema3 0.8015
|
||||
tcyca_ema4 0.8455
|
||||
tcyca_ema5 0.8809
|
||||
tcyca_ema6 0.9227
|
||||
tcyca_ema7 0.9581
|
||||
tcycb_ema0 0.9048
|
||||
tcycb_ema1 0.9678
|
||||
tcycb_ema2 0.9867
|
||||
tcycb_ema3 1.0287
|
||||
tcycb_ema4 1.0812
|
||||
tcycb_ema5 1.1156
|
||||
tcycb_ema6 1.1654
|
||||
tcycb_ema7 1.2004
|
||||
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
|
||||
tcracwb_rd0 0.5748
|
||||
tcracwb_rd1 0.5900
|
||||
tcracwb_rd2 0.5959
|
||||
tcracwb_rd3 0.6016
|
||||
tcracwb_rd4 0.6450
|
||||
tcracwb_rd5 0.6799
|
||||
tcracwb_rd6 0.7211
|
||||
tcracwb_rd7 0.7560
|
||||
tcwbcra_wr0 0.6982
|
||||
tcwbcra_wr1 0.7603
|
||||
tcwbcra_wr2 0.7789
|
||||
tcwbcra_wr3 0.8202
|
||||
tcwbcra_wr4 0.8720
|
||||
tcwbcra_wr5 0.9059
|
||||
tcwbcra_wr6 0.9549
|
||||
tcwbcra_wr7 0.9894
|
||||
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
|
||||
tckah 0.0927
|
||||
tckal 0.0899
|
||||
tckbh 0.0959
|
||||
tckbl 0.0907
|
||||
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
|
||||
tcenas 0.1050
|
||||
taas 0.1052
|
||||
tcenbs 0.1076
|
||||
twenbs 0.0150
|
||||
tabs 0.1109
|
||||
tdbs 0.0228
|
||||
temaas 0.8268
|
||||
temasas 0.8268
|
||||
temabs 1.0540
|
||||
ttenas 0.1862
|
||||
ttcenas 0.1053
|
||||
ttaas 0.1072
|
||||
ttenbs 0.3890
|
||||
ttcenbs 0.1081
|
||||
ttwenbs 0.0151
|
||||
ttabs 0.1146
|
||||
ttdbs 0.0237
|
||||
tsias 0.2048
|
||||
tseas 0.2048
|
||||
tdftrambypas 0.2426
|
||||
tdftrambypbs 0.2426
|
||||
tsibs 0.0228
|
||||
tsebs 0.3890
|
||||
tcolldisnas 0.8268
|
||||
tcolldisnbs 1.0540
|
||||
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
|
||||
tcenah 0.0403
|
||||
tcenaf_ret1nfh 1.0637
|
||||
tcenaf_ret1nrh 0.4338
|
||||
taah 0.0702
|
||||
tcenbh 0.0423
|
||||
tcenbf_ret1nfh 1.0637
|
||||
tcenbf_ret1nrh 0.4338
|
||||
twenbh 0.1736
|
||||
tabh 0.0649
|
||||
tdbh 0.1710
|
||||
temaah 1.0484
|
||||
temasah 1.0484
|
||||
temabh 1.2354
|
||||
ttenah 0.0772
|
||||
ttcenah 0.0415
|
||||
ttcenaf_ret1nfh 1.0637
|
||||
ttcenaf_ret1nrh 0.4338
|
||||
ttaah 0.0702
|
||||
ttenbh 0.1918
|
||||
ttcenbh 0.0436
|
||||
ttcenbf_ret1nfh 1.0637
|
||||
ttcenbf_ret1nrh 0.4338
|
||||
ttwenbh 0.1743
|
||||
ttabh 0.0649
|
||||
ttdbh 0.1710
|
||||
tret1nf_dftrambypfh 0.0270
|
||||
tret1nr_dftrambypfh 1.0637
|
||||
tret1nf_cenbrh 0.0270
|
||||
tret1nf_cenarh 0.0263
|
||||
tret1nf_tcenarh 0.0263
|
||||
tret1nf_tcenbrh 0.0270
|
||||
tret1nr_tcenbrh 1.0637
|
||||
tret1nr_tcenarh 0.8365
|
||||
tret1nr_cenbrh 1.0637
|
||||
tret1nr_cenarh 0.8365
|
||||
tsiah 0.0756
|
||||
tseah 1.0484
|
||||
tdftrambypah 1.0484
|
||||
tdftrambypbh 1.0637
|
||||
tdftrambypr_ret1nfh 1.0637
|
||||
tdftrambypr_ret1nrh 0.4338
|
||||
tsibh 0.1710
|
||||
tsebh 0.1918
|
||||
tcolldisnah 1.0484
|
||||
tcolldisnbh 1.2354
|
||||
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
|
||||
icap_clka 0.0105
|
||||
icap_cena 0.0018
|
||||
icap_aa 0.0012
|
||||
icap_clkb 0.0106
|
||||
icap_cenb 0.0015
|
||||
icap_wenb 0.0017
|
||||
icap_ab 0.0012
|
||||
icap_db 0.0019
|
||||
icap_emaa 0.0059
|
||||
icap_emasa 0.0021
|
||||
icap_emab 0.0057
|
||||
icap_tena 0.0010
|
||||
icap_tcena 0.0016
|
||||
icap_taa 0.0014
|
||||
icap_tenb 0.0012
|
||||
icap_tcenb 0.0016
|
||||
icap_twenb 0.0015
|
||||
icap_tab 0.0014
|
||||
icap_tdb 0.0016
|
||||
icap_sia 0.0015
|
||||
icap_sea 0.0019
|
||||
icap_dftrambyp 0.0021
|
||||
icap_sib 0.0056
|
||||
icap_seb 0.0019
|
||||
icap_colldisn 0.0024
|
||||
icap_ret1n 0.0035
|
||||
# High Density Two Port Register File SVT MVT Compiler : current specific information.
|
||||
icc_standby_c_chipdisable 1.767455
|
||||
icc_standby_p_chipdisable 2.458812
|
||||
icc_standby_c_ret1 2.056615
|
||||
icc_standby_p_ret1 0.26801
|
||||
icc_standby_c_selective_precharge 1.749951
|
||||
icc_standby_p_selective_precharge 1.823619
|
||||
icc_c_rd0_a 1.119e-04
|
||||
icc_c_rd1_a 1.134e-04
|
||||
icc_c_rd2_a 1.145e-04
|
||||
icc_c_rd3_a 1.145e-04
|
||||
icc_c_rd4_a 1.153e-04
|
||||
icc_c_rd5_a 1.159e-04
|
||||
icc_c_rd6_a 1.159e-04
|
||||
icc_c_rd7_a 1.174e-04
|
||||
icc_p_rd0_a 4.977e-03
|
||||
icc_p_rd1_a 5.064e-03
|
||||
icc_p_rd2_a 5.064e-03
|
||||
icc_p_rd3_a 5.104e-03
|
||||
icc_p_rd4_a 5.334e-03
|
||||
icc_p_rd5_a 5.493e-03
|
||||
icc_p_rd6_a 5.653e-03
|
||||
icc_p_rd7_a 5.738e-03
|
||||
icc_c_wr0_b 2.470e-04
|
||||
icc_c_wr1_b 2.485e-04
|
||||
icc_c_wr2_b 2.497e-04
|
||||
icc_c_wr3_b 2.497e-04
|
||||
icc_c_wr4_b 2.504e-04
|
||||
icc_c_wr5_b 2.510e-04
|
||||
icc_c_wr6_b 2.510e-04
|
||||
icc_c_wr7_b 2.525e-04
|
||||
icc_p_wr0_b 6.635e-03
|
||||
icc_p_wr1_b 6.723e-03
|
||||
icc_p_wr2_b 6.723e-03
|
||||
icc_p_wr3_b 6.763e-03
|
||||
icc_p_wr4_b 6.993e-03
|
||||
icc_p_wr5_b 7.152e-03
|
||||
icc_p_wr6_b 7.312e-03
|
||||
icc_p_wr7_b 7.398e-03
|
||||
icc_c_desela 0.000e+00
|
||||
icc_p_desela 1.083e-04
|
||||
icc_c_deselb 0.000e+00
|
||||
icc_p_deselb 1.207e-03
|
||||
icc_c_peak 10.775173
|
||||
icc_p_peak 165.11481
|
||||
icc_c_inrush 4.978407
|
||||
icc_p_inrush 157.2522
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
275
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_rtl.v
Normal file
275
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_rtl.v
Normal file
@@ -0,0 +1,275 @@
|
||||
/* verilog_rtl_memcomp Version: 4.0.5-beta11 */
|
||||
/* common_memcomp Version: 4.0.5.2-amci */
|
||||
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
|
||||
//
|
||||
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
//
|
||||
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
//
|
||||
// Use of this Software is subject to the terms and conditions of the
|
||||
// applicable license agreement with ARM Physical IP, Inc.
|
||||
// In addition, this Software is protected by patents, copyright law
|
||||
// and international treaties.
|
||||
//
|
||||
// The copyright notice(s) in this Software does not indicate actual or
|
||||
// intended publication of this Software.
|
||||
//
|
||||
// Repair Verilog RTL for High Density Two Port Register File SVT MVT Compiler
|
||||
//
|
||||
// Instance Name: rf2_256x128_wm1_rtl_top
|
||||
// Words: 256
|
||||
// User Bits: 128
|
||||
// Mux: 2
|
||||
// Drive: 6
|
||||
// Write Mask: On
|
||||
// Extra Margin Adjustment: On
|
||||
// Redundancy: off
|
||||
// Redundant Rows: 0
|
||||
// Redundant Columns: 2
|
||||
// Test Muxes On
|
||||
// Ser: none
|
||||
// Retention: on
|
||||
// Power Gating: off
|
||||
//
|
||||
// Creation Date: Sun Oct 20 14:38:18 2019
|
||||
// Version: r4p0
|
||||
//
|
||||
// Verified
|
||||
//
|
||||
// Known Bugs: None.
|
||||
//
|
||||
// Known Work Arounds: N/A
|
||||
//
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module rf2_256x128_wm1_rtl_top (
|
||||
CENYA,
|
||||
AYA,
|
||||
CENYB,
|
||||
WENYB,
|
||||
AYB,
|
||||
QA,
|
||||
SOA,
|
||||
SOB,
|
||||
CLKA,
|
||||
CENA,
|
||||
AA,
|
||||
CLKB,
|
||||
CENB,
|
||||
WENB,
|
||||
AB,
|
||||
DB,
|
||||
EMAA,
|
||||
EMASA,
|
||||
EMAB,
|
||||
TENA,
|
||||
TCENA,
|
||||
TAA,
|
||||
TENB,
|
||||
TCENB,
|
||||
TWENB,
|
||||
TAB,
|
||||
TDB,
|
||||
RET1N,
|
||||
SIA,
|
||||
SEA,
|
||||
DFTRAMBYP,
|
||||
SIB,
|
||||
SEB,
|
||||
COLLDISN
|
||||
);
|
||||
|
||||
output CENYA;
|
||||
output [7:0] AYA;
|
||||
output CENYB;
|
||||
output [127:0] WENYB;
|
||||
output [7:0] AYB;
|
||||
output [127:0] QA;
|
||||
output [1:0] SOA;
|
||||
output [1:0] SOB;
|
||||
input CLKA;
|
||||
input CENA;
|
||||
input [7:0] AA;
|
||||
input CLKB;
|
||||
input CENB;
|
||||
input [127:0] WENB;
|
||||
input [7:0] AB;
|
||||
input [127:0] DB;
|
||||
input [2:0] EMAA;
|
||||
input EMASA;
|
||||
input [2:0] EMAB;
|
||||
input TENA;
|
||||
input TCENA;
|
||||
input [7:0] TAA;
|
||||
input TENB;
|
||||
input TCENB;
|
||||
input [127:0] TWENB;
|
||||
input [7:0] TAB;
|
||||
input [127:0] TDB;
|
||||
input RET1N;
|
||||
input [1:0] SIA;
|
||||
input SEA;
|
||||
input DFTRAMBYP;
|
||||
input [1:0] SIB;
|
||||
input SEB;
|
||||
input COLLDISN;
|
||||
wire [127:0] QOA;
|
||||
wire [127:0] DIB;
|
||||
|
||||
assign QA = QOA;
|
||||
assign DIB = DB;
|
||||
rf2_256x128_wm1_fr_top u0 (
|
||||
.CENYA(CENYA),
|
||||
.AYA(AYA),
|
||||
.CENYB(CENYB),
|
||||
.WENYB(WENYB),
|
||||
.AYB(AYB),
|
||||
.QOA(QOA),
|
||||
.SOA(SOA),
|
||||
.SOB(SOB),
|
||||
.CLKA(CLKA),
|
||||
.CENA(CENA),
|
||||
.AA(AA),
|
||||
.CLKB(CLKB),
|
||||
.CENB(CENB),
|
||||
.WENB(WENB),
|
||||
.AB(AB),
|
||||
.DIB(DIB),
|
||||
.EMAA(EMAA),
|
||||
.EMASA(EMASA),
|
||||
.EMAB(EMAB),
|
||||
.TENA(TENA),
|
||||
.TCENA(TCENA),
|
||||
.TAA(TAA),
|
||||
.TENB(TENB),
|
||||
.TCENB(TCENB),
|
||||
.TWENB(TWENB),
|
||||
.TAB(TAB),
|
||||
.TDB(TDB),
|
||||
.RET1N(RET1N),
|
||||
.SIA(SIA),
|
||||
.SEA(SEA),
|
||||
.DFTRAMBYP(DFTRAMBYP),
|
||||
.SIB(SIB),
|
||||
.SEB(SEB),
|
||||
.COLLDISN(COLLDISN)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
module rf2_256x128_wm1_fr_top (
|
||||
CENYA,
|
||||
AYA,
|
||||
CENYB,
|
||||
WENYB,
|
||||
AYB,
|
||||
QOA,
|
||||
SOA,
|
||||
SOB,
|
||||
CLKA,
|
||||
CENA,
|
||||
AA,
|
||||
CLKB,
|
||||
CENB,
|
||||
WENB,
|
||||
AB,
|
||||
DIB,
|
||||
EMAA,
|
||||
EMASA,
|
||||
EMAB,
|
||||
TENA,
|
||||
TCENA,
|
||||
TAA,
|
||||
TENB,
|
||||
TCENB,
|
||||
TWENB,
|
||||
TAB,
|
||||
TDB,
|
||||
RET1N,
|
||||
SIA,
|
||||
SEA,
|
||||
DFTRAMBYP,
|
||||
SIB,
|
||||
SEB,
|
||||
COLLDISN
|
||||
);
|
||||
|
||||
output CENYA;
|
||||
output [7:0] AYA;
|
||||
output CENYB;
|
||||
output [127:0] WENYB;
|
||||
output [7:0] AYB;
|
||||
output [127:0] QOA;
|
||||
output [1:0] SOA;
|
||||
output [1:0] SOB;
|
||||
input CLKA;
|
||||
input CENA;
|
||||
input [7:0] AA;
|
||||
input CLKB;
|
||||
input CENB;
|
||||
input [127:0] WENB;
|
||||
input [7:0] AB;
|
||||
input [127:0] DIB;
|
||||
input [2:0] EMAA;
|
||||
input EMASA;
|
||||
input [2:0] EMAB;
|
||||
input TENA;
|
||||
input TCENA;
|
||||
input [7:0] TAA;
|
||||
input TENB;
|
||||
input TCENB;
|
||||
input [127:0] TWENB;
|
||||
input [7:0] TAB;
|
||||
input [127:0] TDB;
|
||||
input RET1N;
|
||||
input [1:0] SIA;
|
||||
input SEA;
|
||||
input DFTRAMBYP;
|
||||
input [1:0] SIB;
|
||||
input SEB;
|
||||
input COLLDISN;
|
||||
|
||||
wire [127:0] DB;
|
||||
wire [127:0] QA;
|
||||
|
||||
assign DB=DIB;
|
||||
assign QOA=QA;
|
||||
rf2_256x128_wm1 u0 (
|
||||
.CENYA(CENYA),
|
||||
.AYA(AYA),
|
||||
.CENYB(CENYB),
|
||||
.WENYB(WENYB),
|
||||
.AYB(AYB),
|
||||
.QA(QA),
|
||||
.SOA(SOA),
|
||||
.SOB(SOB),
|
||||
.CLKA(CLKA),
|
||||
.CENA(CENA),
|
||||
.AA(AA),
|
||||
.CLKB(CLKB),
|
||||
.CENB(CENB),
|
||||
.WENB(WENB),
|
||||
.AB(AB),
|
||||
.DB(DB),
|
||||
.EMAA(EMAA),
|
||||
.EMASA(EMASA),
|
||||
.EMAB(EMAB),
|
||||
.TENA(TENA),
|
||||
.TCENA(TCENA),
|
||||
.TAA(TAA),
|
||||
.TENB(TENB),
|
||||
.TCENB(TCENB),
|
||||
.TWENB(TWENB),
|
||||
.TAB(TAB),
|
||||
.TDB(TDB),
|
||||
.RET1N(RET1N),
|
||||
.SIA(SIA),
|
||||
.SEA(SEA),
|
||||
.DFTRAMBYP(DFTRAMBYP),
|
||||
.SIB(SIB),
|
||||
.SEB(SEB),
|
||||
.COLLDISN(COLLDISN)
|
||||
);
|
||||
|
||||
endmodule // rf2_256x128_wm1_fr_top
|
||||
|
||||
@@ -0,0 +1,162 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:34:42 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_256x128_wm1
|
||||
# Number of Words: 256
|
||||
# Number of Bits: 128
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: on
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: avm
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# avm_memcomp Version: 2.1.1-EAC
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
rf2_256x128_wm1 {
|
||||
MEMORY_TYPE RegFile
|
||||
EQUIV_GATE_COUNT 36045
|
||||
VDD_PIN VDDCE VDDPE
|
||||
GND_PIN VSSE
|
||||
#This file is for PROCESS SS, CORNER SS_0P81V_0P81V_M40C
|
||||
#However, RedHawk needs the process to be specified as 'PROCESS XX'
|
||||
PROCESS XX
|
||||
Cload 3.5e-05nF
|
||||
VDD 0.81 0.81
|
||||
|
||||
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
|
||||
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
|
||||
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
|
||||
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
|
||||
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
|
||||
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
|
||||
|
||||
Cpd avm_into_lowpwr {
|
||||
VDDCE VSSE 1.36450e-04nF
|
||||
VDDPE VSSE 5.69028e-04nF
|
||||
}
|
||||
PEAK_I avm_into_lowpwr {
|
||||
VDDCE VSSE 1.38817mA
|
||||
VDDPE VSSE 3.40465mA
|
||||
}
|
||||
Cpd avm_outof_lowpwr {
|
||||
VDDCE VSSE 1.50095e-04nF
|
||||
VDDPE VSSE 1.99757e-02nF
|
||||
}
|
||||
PEAK_I avm_outof_lowpwr {
|
||||
VDDCE VSSE 1.52699mA
|
||||
VDDPE VSSE 54.53884mA
|
||||
}
|
||||
Cpd avm_read_write {
|
||||
VDDCE VSSE 3.02086e-04nF
|
||||
VDDPE VSSE 1.12684e-02nF
|
||||
}
|
||||
PEAK_I avm_read_write {
|
||||
VDDCE VSSE 3.03008mA
|
||||
VDDPE VSSE 57.13365mA
|
||||
}
|
||||
Cpd avm_read_desel {
|
||||
VDDCE VSSE 1.11001e-04nF
|
||||
VDDPE VSSE 4.76672e-03nF
|
||||
}
|
||||
PEAK_I avm_read_desel {
|
||||
VDDCE VSSE 0.98347mA
|
||||
VDDPE VSSE 24.69243mA
|
||||
}
|
||||
Cpd avm_desel_write {
|
||||
VDDCE VSSE 1.91085e-04nF
|
||||
VDDPE VSSE 6.50167e-03nF
|
||||
}
|
||||
PEAK_I avm_desel_write {
|
||||
VDDCE VSSE 2.00722mA
|
||||
VDDPE VSSE 32.81133mA
|
||||
}
|
||||
Cpd avm_scan_capture {
|
||||
VDDCE VSSE 8.14454e-06nF
|
||||
VDDPE VSSE 9.88468e-03nF
|
||||
}
|
||||
PEAK_I avm_scan_capture {
|
||||
VDDCE VSSE 0.14129mA
|
||||
VDDPE VSSE 13.03296mA
|
||||
}
|
||||
Cpd avm_scan_shift {
|
||||
VDDCE VSSE 8.14454e-06nF
|
||||
VDDPE VSSE 9.88468e-03nF
|
||||
}
|
||||
PEAK_I avm_scan_shift {
|
||||
VDDCE VSSE 0.14129mA
|
||||
VDDPE VSSE 13.03296mA
|
||||
}
|
||||
Cpd standby_trig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.69190e-05nF
|
||||
}
|
||||
Cpd standby_ntrig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.87989e-05nF
|
||||
}
|
||||
LEAKAGE_I {
|
||||
VDDCE VSSE 1.48000e-03mA
|
||||
VDDPE VSSE 1.00800e-03mA
|
||||
}
|
||||
tsu 0.30673ns
|
||||
ck2q_delay 1.23487ns
|
||||
tr_q 0.034858ns
|
||||
tf_q 0.039745ns
|
||||
CHARACTERIZATION_MODE accurate
|
||||
}
|
||||
@@ -0,0 +1,334 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:35:06 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_256x128_wm1
|
||||
# Number of Words: 256
|
||||
# Number of Bits: 128
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: on
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: datatable
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# datatable_memcomp Version: 1.3.0-amci
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
# Units used in Datatable :
|
||||
# geomx: micron
|
||||
# geomy: micron
|
||||
# Voltage: volts
|
||||
# Temprature: Degree Celsius
|
||||
# Current: mA
|
||||
# Time: ns
|
||||
#
|
||||
name ss_0p81v_0p81v_m40c
|
||||
S N
|
||||
geomx 51.4050
|
||||
geomy 414.8600
|
||||
volt 0.8100
|
||||
temp -40.0000
|
||||
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
|
||||
tcenacenya 0.2145
|
||||
ttcenacenya 0.2108
|
||||
ttenacenyapu 0.3026
|
||||
ttenacenyanu 0.3541
|
||||
tdftrambypcenya 0.3853
|
||||
taaaya 0.2110
|
||||
ttaaaya 0.2184
|
||||
ttenaayapu 0.3904
|
||||
ttenaayanu 0.3751
|
||||
tdftrambypaya 0.3736
|
||||
tcenbcenyb 0.2113
|
||||
ttcenbcenyb 0.2108
|
||||
ttenbcenybpu 0.3045
|
||||
ttenbcenybnu 0.5445
|
||||
tdftrambypcenyb 0.3738
|
||||
twenbwenyb 0.2952
|
||||
ttwenbwenyb 0.2956
|
||||
ttenbwenybpu 0.6920
|
||||
ttenbwenybnu 0.7096
|
||||
tdftrambypwenyb 0.4014
|
||||
tabayb 0.2105
|
||||
ttabayb 0.2161
|
||||
ttenbaybpu 0.5881
|
||||
ttenbaybnu 0.5463
|
||||
tdftrambypayb 0.3669
|
||||
taccqa_rd0 1.1578
|
||||
taccqa_rd1 1.2052
|
||||
taccqa_rd2 1.2130
|
||||
taccqa_rd3 1.2349
|
||||
taccqa_rd4 1.3452
|
||||
taccqa_rd5 1.4641
|
||||
taccqa_rd6 1.5960
|
||||
taccqa_rd7 1.7145
|
||||
taccqa_scan0 1.1578
|
||||
taccqa_scan1 1.2052
|
||||
taccqa_scan2 1.2130
|
||||
taccqa_scan3 1.2349
|
||||
taccqa_scan4 1.3452
|
||||
taccqa_scan5 1.4641
|
||||
taccqa_scan6 1.5960
|
||||
taccqa_scan7 1.7145
|
||||
tclkasoa_rd0 1.2615
|
||||
tclkasoa_rd1 1.3089
|
||||
tclkasoa_rd2 1.3167
|
||||
tclkasoa_rd3 1.3386
|
||||
tclkasoa_rd4 1.4489
|
||||
tclkasoa_rd5 1.5678
|
||||
tclkasoa_rd6 1.6997
|
||||
tclkasoa_rd7 1.8182
|
||||
tclkasoa_scan0 1.2615
|
||||
tclkasoa_scan1 1.3089
|
||||
tclkasoa_scan2 1.3167
|
||||
tclkasoa_scan3 1.3386
|
||||
tclkasoa_scan4 1.4489
|
||||
tclkasoa_scan5 1.5678
|
||||
tclkasoa_scan6 1.6997
|
||||
tclkasoa_scan7 1.8182
|
||||
tclkbsob 0.5287
|
||||
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
|
||||
kload_cenya 3.3060
|
||||
kload_aya 2.7500
|
||||
kload_cenyb 3.3440
|
||||
kload_wenyb 3.0700
|
||||
kload_ayb 2.7720
|
||||
kload_qa 1.0935
|
||||
kload_soa 2.7600
|
||||
kload_sob 3.1660
|
||||
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
|
||||
tcyca_ema0 1.6962
|
||||
tcyca_ema1 1.7444
|
||||
tcyca_ema2 1.7524
|
||||
tcyca_ema3 1.7745
|
||||
tcyca_ema4 1.8864
|
||||
tcyca_ema5 2.0071
|
||||
tcyca_ema6 2.1411
|
||||
tcyca_ema7 2.2613
|
||||
tcycb_ema0 1.9005
|
||||
tcycb_ema1 2.0932
|
||||
tcycb_ema2 2.1705
|
||||
tcycb_ema3 2.3041
|
||||
tcycb_ema4 2.4369
|
||||
tcycb_ema5 2.5494
|
||||
tcycb_ema6 2.7016
|
||||
tcycb_ema7 2.8221
|
||||
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
|
||||
tcracwb_rd0 0.9660
|
||||
tcracwb_rd1 1.0134
|
||||
tcracwb_rd2 1.0212
|
||||
tcracwb_rd3 1.0431
|
||||
tcracwb_rd4 1.1534
|
||||
tcracwb_rd5 1.2723
|
||||
tcracwb_rd6 1.4042
|
||||
tcracwb_rd7 1.5227
|
||||
tcwbcra_wr0 1.3612
|
||||
tcwbcra_wr1 1.5512
|
||||
tcwbcra_wr2 1.6273
|
||||
tcwbcra_wr3 1.7590
|
||||
tcwbcra_wr4 1.8898
|
||||
tcwbcra_wr5 2.0006
|
||||
tcwbcra_wr6 2.1506
|
||||
tcwbcra_wr7 2.2692
|
||||
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
|
||||
tckah 0.1789
|
||||
tckal 0.1936
|
||||
tckbh 0.1811
|
||||
tckbl 0.1760
|
||||
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
|
||||
tcenas 0.2616
|
||||
taas 0.3067
|
||||
tcenbs 0.2580
|
||||
twenbs 0.0857
|
||||
tabs 0.3108
|
||||
tdbs 0.1681
|
||||
temaas 1.8578
|
||||
temasas 1.8578
|
||||
temabs 2.3875
|
||||
ttenas 0.4973
|
||||
ttcenas 0.2628
|
||||
ttaas 0.3154
|
||||
ttenbs 0.8279
|
||||
ttcenbs 0.2586
|
||||
ttwenbs 0.0862
|
||||
ttabs 0.3179
|
||||
ttdbs 0.1738
|
||||
tsias 0.5470
|
||||
tseas 0.5470
|
||||
tdftrambypas 0.7164
|
||||
tdftrambypbs 0.7164
|
||||
tsibs 0.1681
|
||||
tsebs 0.8279
|
||||
tcolldisnas 1.8578
|
||||
tcolldisnbs 2.3875
|
||||
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
|
||||
tcenah 0.0852
|
||||
tcenaf_ret1nfh 2.3683
|
||||
tcenaf_ret1nrh 0.9924
|
||||
taah 0.1420
|
||||
tcenbh 0.0853
|
||||
tcenbf_ret1nfh 2.3683
|
||||
tcenbf_ret1nrh 0.9924
|
||||
twenbh 0.3114
|
||||
tabh 0.1299
|
||||
tdbh 0.3013
|
||||
temaah 2.5228
|
||||
temasah 2.5228
|
||||
temabh 2.8863
|
||||
ttenah 0.1562
|
||||
ttcenah 0.0868
|
||||
ttcenaf_ret1nfh 2.3683
|
||||
ttcenaf_ret1nrh 0.9924
|
||||
ttaah 0.1420
|
||||
ttenbh 0.3425
|
||||
ttcenbh 0.0866
|
||||
ttcenbf_ret1nfh 2.3683
|
||||
ttcenbf_ret1nrh 0.9924
|
||||
ttwenbh 0.3114
|
||||
ttabh 0.1299
|
||||
ttdbh 0.3013
|
||||
tret1nf_dftrambypfh 0.0657
|
||||
tret1nr_dftrambypfh 2.3683
|
||||
tret1nf_cenbrh 0.0646
|
||||
tret1nf_cenarh 0.0657
|
||||
tret1nf_tcenarh 0.0657
|
||||
tret1nf_tcenbrh 0.0646
|
||||
tret1nr_tcenbrh 2.3683
|
||||
tret1nr_tcenarh 1.8386
|
||||
tret1nr_cenbrh 2.3683
|
||||
tret1nr_cenarh 1.8386
|
||||
tsiah 0.1246
|
||||
tseah 2.5228
|
||||
tdftrambypah 2.5228
|
||||
tdftrambypbh 2.3683
|
||||
tdftrambypr_ret1nfh 2.3683
|
||||
tdftrambypr_ret1nrh 0.9924
|
||||
tsibh 0.3013
|
||||
tsebh 0.3425
|
||||
tcolldisnah 2.5228
|
||||
tcolldisnbh 2.8863
|
||||
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
|
||||
icap_clka 0.0087
|
||||
icap_cena 0.0014
|
||||
icap_aa 0.0017
|
||||
icap_clkb 0.0088
|
||||
icap_cenb 0.0011
|
||||
icap_wenb 0.0016
|
||||
icap_ab 0.0015
|
||||
icap_db 0.0018
|
||||
icap_emaa 0.0056
|
||||
icap_emasa 0.0021
|
||||
icap_emab 0.0054
|
||||
icap_tena 0.0008
|
||||
icap_tcena 0.0012
|
||||
icap_taa 0.0016
|
||||
icap_tenb 0.0009
|
||||
icap_tcenb 0.0012
|
||||
icap_twenb 0.0014
|
||||
icap_tab 0.0014
|
||||
icap_tdb 0.0015
|
||||
icap_sia 0.0011
|
||||
icap_sea 0.0016
|
||||
icap_dftrambyp 0.0016
|
||||
icap_sib 0.0054
|
||||
icap_seb 0.0017
|
||||
icap_colldisn 0.0021
|
||||
icap_ret1n 0.0032
|
||||
# High Density Two Port Register File SVT MVT Compiler : current specific information.
|
||||
icc_standby_c_chipdisable 1.480e-03
|
||||
icc_standby_p_chipdisable 1.008e-03
|
||||
icc_standby_c_ret1 1.476e-03
|
||||
icc_standby_p_ret1 7.112e-06
|
||||
icc_standby_c_selective_precharge 1.473e-03
|
||||
icc_standby_p_selective_precharge 3.757e-04
|
||||
icc_c_rd0_a 8.975e-05
|
||||
icc_c_rd1_a 8.975e-05
|
||||
icc_c_rd2_a 8.991e-05
|
||||
icc_c_rd3_a 8.991e-05
|
||||
icc_c_rd4_a 9.031e-05
|
||||
icc_c_rd5_a 9.135e-05
|
||||
icc_c_rd6_a 9.197e-05
|
||||
icc_c_rd7_a 9.199e-05
|
||||
icc_p_rd0_a 3.725e-03
|
||||
icc_p_rd1_a 3.805e-03
|
||||
icc_p_rd2_a 3.839e-03
|
||||
icc_p_rd3_a 3.861e-03
|
||||
icc_p_rd4_a 4.110e-03
|
||||
icc_p_rd5_a 4.285e-03
|
||||
icc_p_rd6_a 4.387e-03
|
||||
icc_p_rd7_a 4.441e-03
|
||||
icc_c_wr0_b 1.546e-04
|
||||
icc_c_wr1_b 1.546e-04
|
||||
icc_c_wr2_b 1.548e-04
|
||||
icc_c_wr3_b 1.548e-04
|
||||
icc_c_wr4_b 1.552e-04
|
||||
icc_c_wr5_b 1.562e-04
|
||||
icc_c_wr6_b 1.568e-04
|
||||
icc_c_wr7_b 1.569e-04
|
||||
icc_p_wr0_b 5.130e-03
|
||||
icc_p_wr1_b 5.210e-03
|
||||
icc_p_wr2_b 5.245e-03
|
||||
icc_p_wr3_b 5.266e-03
|
||||
icc_p_wr4_b 5.515e-03
|
||||
icc_p_wr5_b 5.690e-03
|
||||
icc_p_wr6_b 5.792e-03
|
||||
icc_p_wr7_b 5.846e-03
|
||||
icc_c_desela 0.000e+00
|
||||
icc_p_desela 7.685e-05
|
||||
icc_c_deselb 0.000e+00
|
||||
icc_p_deselb 9.096e-04
|
||||
icc_c_peak 3.03008
|
||||
icc_p_peak 57.133648
|
||||
icc_c_inrush 1.397455
|
||||
icc_p_inrush 54.412998
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,162 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:34:49 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_256x128_wm1
|
||||
# Number of Words: 256
|
||||
# Number of Bits: 128
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: on
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: avm
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# avm_memcomp Version: 2.1.1-EAC
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
rf2_256x128_wm1 {
|
||||
MEMORY_TYPE RegFile
|
||||
EQUIV_GATE_COUNT 36045
|
||||
VDD_PIN VDDCE VDDPE
|
||||
GND_PIN VSSE
|
||||
#This file is for PROCESS TT, CORNER TT_0P90V_0P90V_25C
|
||||
#However, RedHawk needs the process to be specified as 'PROCESS XX'
|
||||
PROCESS XX
|
||||
Cload 3.5e-05nF
|
||||
VDD 0.9 0.9
|
||||
|
||||
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
|
||||
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
|
||||
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
|
||||
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
|
||||
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
|
||||
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
|
||||
|
||||
Cpd avm_into_lowpwr {
|
||||
VDDCE VSSE 1.46123e-04nF
|
||||
VDDPE VSSE 5.81140e-04nF
|
||||
}
|
||||
PEAK_I avm_into_lowpwr {
|
||||
VDDCE VSSE 2.51801mA
|
||||
VDDPE VSSE 5.85375mA
|
||||
}
|
||||
Cpd avm_outof_lowpwr {
|
||||
VDDCE VSSE 1.60735e-04nF
|
||||
VDDPE VSSE 2.06310e-02nF
|
||||
}
|
||||
PEAK_I avm_outof_lowpwr {
|
||||
VDDCE VSSE 2.76981mA
|
||||
VDDPE VSSE 97.44930mA
|
||||
}
|
||||
Cpd avm_read_write {
|
||||
VDDCE VSSE 3.28585e-04nF
|
||||
VDDPE VSSE 1.15071e-02nF
|
||||
}
|
||||
PEAK_I avm_read_write {
|
||||
VDDCE VSSE 6.02046mA
|
||||
VDDPE VSSE 102.32177mA
|
||||
}
|
||||
Cpd avm_read_desel {
|
||||
VDDCE VSSE 1.13920e-04nF
|
||||
VDDPE VSSE 4.91994e-03nF
|
||||
}
|
||||
PEAK_I avm_read_desel {
|
||||
VDDCE VSSE 1.74222mA
|
||||
VDDPE VSSE 43.45212mA
|
||||
}
|
||||
Cpd avm_desel_write {
|
||||
VDDCE VSSE 2.14665e-04nF
|
||||
VDDPE VSSE 6.58721e-03nF
|
||||
}
|
||||
PEAK_I avm_desel_write {
|
||||
VDDCE VSSE 4.09592mA
|
||||
VDDPE VSSE 61.21476mA
|
||||
}
|
||||
Cpd avm_scan_capture {
|
||||
VDDCE VSSE 8.56193e-06nF
|
||||
VDDPE VSSE 1.02363e-02nF
|
||||
}
|
||||
PEAK_I avm_scan_capture {
|
||||
VDDCE VSSE 0.27530mA
|
||||
VDDPE VSSE 24.42748mA
|
||||
}
|
||||
Cpd avm_scan_shift {
|
||||
VDDCE VSSE 8.56193e-06nF
|
||||
VDDPE VSSE 1.02363e-02nF
|
||||
}
|
||||
PEAK_I avm_scan_shift {
|
||||
VDDCE VSSE 0.27530mA
|
||||
VDDPE VSSE 24.42748mA
|
||||
}
|
||||
Cpd standby_trig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.77000e-05nF
|
||||
}
|
||||
Cpd standby_ntrig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.96666e-05nF
|
||||
}
|
||||
LEAKAGE_I {
|
||||
VDDCE VSSE 1.27820e-02mA
|
||||
VDDPE VSSE 1.52060e-02mA
|
||||
}
|
||||
tsu 0.146718ns
|
||||
ck2q_delay 0.73198ns
|
||||
tr_q 0.018874ns
|
||||
tf_q 0.022096ns
|
||||
CHARACTERIZATION_MODE accurate
|
||||
}
|
||||
@@ -0,0 +1,334 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:35:10 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_256x128_wm1
|
||||
# Number of Words: 256
|
||||
# Number of Bits: 128
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: on
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: datatable
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# datatable_memcomp Version: 1.3.0-amci
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
# Units used in Datatable :
|
||||
# geomx: micron
|
||||
# geomy: micron
|
||||
# Voltage: volts
|
||||
# Temprature: Degree Celsius
|
||||
# Current: mA
|
||||
# Time: ns
|
||||
#
|
||||
name tt_0p90v_0p90v_25c
|
||||
S N
|
||||
geomx 51.4050
|
||||
geomy 414.8600
|
||||
volt 0.9000
|
||||
temp 25.0000
|
||||
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
|
||||
tcenacenya 0.1187
|
||||
ttcenacenya 0.1176
|
||||
ttenacenyapu 0.1613
|
||||
ttenacenyanu 0.1885
|
||||
tdftrambypcenya 0.1900
|
||||
taaaya 0.1038
|
||||
ttaaaya 0.1082
|
||||
ttenaayapu 0.1877
|
||||
ttenaayanu 0.1835
|
||||
tdftrambypaya 0.1776
|
||||
tcenbcenyb 0.1195
|
||||
ttcenbcenyb 0.1185
|
||||
ttenbcenybpu 0.1658
|
||||
ttenbcenybnu 0.2823
|
||||
tdftrambypcenyb 0.1824
|
||||
twenbwenyb 0.1351
|
||||
ttwenbwenyb 0.1341
|
||||
ttenbwenybpu 0.3463
|
||||
ttenbwenybnu 0.3615
|
||||
tdftrambypwenyb 0.2183
|
||||
tabayb 0.1040
|
||||
ttabayb 0.1062
|
||||
ttenbaybpu 0.2796
|
||||
ttenbaybnu 0.2792
|
||||
tdftrambypayb 0.1779
|
||||
taccqa_rd0 0.6912
|
||||
taccqa_rd1 0.7160
|
||||
taccqa_rd2 0.7230
|
||||
taccqa_rd3 0.7320
|
||||
taccqa_rd4 0.7886
|
||||
taccqa_rd5 0.8424
|
||||
taccqa_rd6 0.8983
|
||||
taccqa_rd7 0.9521
|
||||
taccqa_scan0 0.6912
|
||||
taccqa_scan1 0.7160
|
||||
taccqa_scan2 0.7230
|
||||
taccqa_scan3 0.7320
|
||||
taccqa_scan4 0.7886
|
||||
taccqa_scan5 0.8424
|
||||
taccqa_scan6 0.8983
|
||||
taccqa_scan7 0.9521
|
||||
tclkasoa_rd0 0.7252
|
||||
tclkasoa_rd1 0.7501
|
||||
tclkasoa_rd2 0.7570
|
||||
tclkasoa_rd3 0.7660
|
||||
tclkasoa_rd4 0.8227
|
||||
tclkasoa_rd5 0.8764
|
||||
tclkasoa_rd6 0.9324
|
||||
tclkasoa_rd7 0.9862
|
||||
tclkasoa_scan0 0.7252
|
||||
tclkasoa_scan1 0.7501
|
||||
tclkasoa_scan2 0.7570
|
||||
tclkasoa_scan3 0.7660
|
||||
tclkasoa_scan4 0.8227
|
||||
tclkasoa_scan5 0.8764
|
||||
tclkasoa_scan6 0.9324
|
||||
tclkasoa_scan7 0.9862
|
||||
tclkbsob 0.2966
|
||||
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
|
||||
kload_cenya 2.0800
|
||||
kload_aya 1.6620
|
||||
kload_cenyb 1.9640
|
||||
kload_wenyb 1.7940
|
||||
kload_ayb 1.6740
|
||||
kload_qa 0.6365
|
||||
kload_soa 1.7020
|
||||
kload_sob 1.8420
|
||||
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
|
||||
tcyca_ema0 0.9855
|
||||
tcyca_ema1 1.0107
|
||||
tcyca_ema2 1.0178
|
||||
tcyca_ema3 1.0269
|
||||
tcyca_ema4 1.0845
|
||||
tcyca_ema5 1.1390
|
||||
tcyca_ema6 1.1958
|
||||
tcyca_ema7 1.2504
|
||||
tcycb_ema0 1.0536
|
||||
tcycb_ema1 1.1407
|
||||
tcycb_ema2 1.1704
|
||||
tcycb_ema3 1.2298
|
||||
tcycb_ema4 1.2998
|
||||
tcycb_ema5 1.3506
|
||||
tcycb_ema6 1.4216
|
||||
tcycb_ema7 1.4725
|
||||
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
|
||||
tcracwb_rd0 0.6691
|
||||
tcracwb_rd1 0.6939
|
||||
tcracwb_rd2 0.7009
|
||||
tcracwb_rd3 0.7099
|
||||
tcracwb_rd4 0.7665
|
||||
tcracwb_rd5 0.8203
|
||||
tcracwb_rd6 0.8762
|
||||
tcracwb_rd7 0.9300
|
||||
tcwbcra_wr0 0.8352
|
||||
tcwbcra_wr1 0.9210
|
||||
tcwbcra_wr2 0.9503
|
||||
tcwbcra_wr3 1.0088
|
||||
tcwbcra_wr4 1.0777
|
||||
tcwbcra_wr5 1.1277
|
||||
tcwbcra_wr6 1.1978
|
||||
tcwbcra_wr7 1.2478
|
||||
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
|
||||
tckah 0.1135
|
||||
tckal 0.1131
|
||||
tckbh 0.1160
|
||||
tckbl 0.1128
|
||||
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
|
||||
tcenas 0.1417
|
||||
taas 0.1467
|
||||
tcenbs 0.1422
|
||||
twenbs 0.0225
|
||||
tabs 0.1545
|
||||
tdbs 0.0487
|
||||
temaas 1.0667
|
||||
temasas 1.0667
|
||||
temabs 1.2696
|
||||
ttenas 0.2541
|
||||
ttcenas 0.1417
|
||||
ttaas 0.1512
|
||||
ttenbs 0.4755
|
||||
ttcenbs 0.1434
|
||||
ttwenbs 0.0225
|
||||
ttabs 0.1580
|
||||
ttdbs 0.0509
|
||||
tsias 0.2795
|
||||
tseas 0.2795
|
||||
tdftrambypas 0.3488
|
||||
tdftrambypbs 0.3488
|
||||
tsibs 0.0487
|
||||
tsebs 0.4755
|
||||
tcolldisnas 1.0667
|
||||
tcolldisnbs 1.2696
|
||||
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
|
||||
tcenah 0.0495
|
||||
tcenaf_ret1nfh 1.2730
|
||||
tcenaf_ret1nrh 0.5521
|
||||
taah 0.0840
|
||||
tcenbh 0.0496
|
||||
tcenbf_ret1nfh 1.2730
|
||||
tcenbf_ret1nrh 0.5521
|
||||
twenbh 0.2057
|
||||
tabh 0.0788
|
||||
tdbh 0.1941
|
||||
temaah 1.3783
|
||||
temasah 1.3783
|
||||
temabh 1.5157
|
||||
ttenah 0.0924
|
||||
ttcenah 0.0524
|
||||
ttcenaf_ret1nfh 1.2730
|
||||
ttcenaf_ret1nrh 0.5521
|
||||
ttaah 0.0840
|
||||
ttenbh 0.2271
|
||||
ttcenbh 0.0510
|
||||
ttcenbf_ret1nfh 1.2730
|
||||
ttcenbf_ret1nrh 0.5521
|
||||
ttwenbh 0.2065
|
||||
ttabh 0.0788
|
||||
ttdbh 0.1941
|
||||
tret1nf_dftrambypfh 0.0358
|
||||
tret1nr_dftrambypfh 1.2730
|
||||
tret1nf_cenbrh 0.0358
|
||||
tret1nf_cenarh 0.0354
|
||||
tret1nf_tcenarh 0.0354
|
||||
tret1nf_tcenbrh 0.0358
|
||||
tret1nr_tcenbrh 1.2730
|
||||
tret1nr_tcenarh 1.0701
|
||||
tret1nr_cenbrh 1.2730
|
||||
tret1nr_cenarh 1.0701
|
||||
tsiah 0.0817
|
||||
tseah 1.3783
|
||||
tdftrambypah 1.3783
|
||||
tdftrambypbh 1.2730
|
||||
tdftrambypr_ret1nfh 1.2730
|
||||
tdftrambypr_ret1nrh 0.5521
|
||||
tsibh 0.1941
|
||||
tsebh 0.2271
|
||||
tcolldisnah 1.3783
|
||||
tcolldisnbh 1.5157
|
||||
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
|
||||
icap_clka 0.0091
|
||||
icap_cena 0.0013
|
||||
icap_aa 0.0016
|
||||
icap_clkb 0.0097
|
||||
icap_cenb 0.0013
|
||||
icap_wenb 0.0014
|
||||
icap_ab 0.0016
|
||||
icap_db 0.0019
|
||||
icap_emaa 0.0058
|
||||
icap_emasa 0.0025
|
||||
icap_emab 0.0056
|
||||
icap_tena 0.0009
|
||||
icap_tcena 0.0014
|
||||
icap_taa 0.0015
|
||||
icap_tenb 0.0010
|
||||
icap_tcenb 0.0014
|
||||
icap_twenb 0.0012
|
||||
icap_tab 0.0016
|
||||
icap_tdb 0.0016
|
||||
icap_sia 0.0012
|
||||
icap_sea 0.0016
|
||||
icap_dftrambyp 0.0021
|
||||
icap_sib 0.0058
|
||||
icap_seb 0.0019
|
||||
icap_colldisn 0.0021
|
||||
icap_ret1n 0.0034
|
||||
# High Density Two Port Register File SVT MVT Compiler : current specific information.
|
||||
icc_standby_c_chipdisable 0.012782
|
||||
icc_standby_p_chipdisable 0.015206
|
||||
icc_standby_c_ret1 0.013463
|
||||
icc_standby_p_ret1 1.006e-03
|
||||
icc_standby_c_selective_precharge 0.012632
|
||||
icc_standby_p_selective_precharge 0.01099
|
||||
icc_c_rd0_a 1.021e-04
|
||||
icc_c_rd1_a 1.025e-04
|
||||
icc_c_rd2_a 1.025e-04
|
||||
icc_c_rd3_a 1.025e-04
|
||||
icc_c_rd4_a 1.052e-04
|
||||
icc_c_rd5_a 1.057e-04
|
||||
icc_c_rd6_a 1.057e-04
|
||||
icc_c_rd7_a 1.073e-04
|
||||
icc_p_rd0_a 4.288e-03
|
||||
icc_p_rd1_a 4.372e-03
|
||||
icc_p_rd2_a 4.389e-03
|
||||
icc_p_rd3_a 4.428e-03
|
||||
icc_p_rd4_a 4.684e-03
|
||||
icc_p_rd5_a 4.855e-03
|
||||
icc_p_rd6_a 5.030e-03
|
||||
icc_p_rd7_a 5.100e-03
|
||||
icc_c_wr0_b 1.927e-04
|
||||
icc_c_wr1_b 1.932e-04
|
||||
icc_c_wr2_b 1.932e-04
|
||||
icc_c_wr3_b 1.932e-04
|
||||
icc_c_wr4_b 1.958e-04
|
||||
icc_c_wr5_b 1.964e-04
|
||||
icc_c_wr6_b 1.964e-04
|
||||
icc_c_wr7_b 1.979e-04
|
||||
icc_p_wr0_b 5.789e-03
|
||||
icc_p_wr1_b 5.872e-03
|
||||
icc_p_wr2_b 5.889e-03
|
||||
icc_p_wr3_b 5.928e-03
|
||||
icc_p_wr4_b 6.185e-03
|
||||
icc_p_wr5_b 6.356e-03
|
||||
icc_p_wr6_b 6.530e-03
|
||||
icc_p_wr7_b 6.601e-03
|
||||
icc_c_desela 0.000e+00
|
||||
icc_p_desela 8.948e-05
|
||||
icc_c_deselb 0.000e+00
|
||||
icc_p_deselb 1.043e-03
|
||||
icc_c_peak 6.020455
|
||||
icc_p_peak 102.321769
|
||||
icc_c_inrush 3.248879
|
||||
icc_p_inrush 97.449304
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
257
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.bitmap
Normal file
257
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.bitmap
Normal file
@@ -0,0 +1,257 @@
|
||||
#address bit[0] bit[0]_ bit[1] bit[1]_ bit[2] bit[2]_ bit[3] bit[3]_ bit[4] bit[4]_ bit[5] bit[5]_ bit[6] bit[6]_ bit[7] bit[7]_ bit[8] bit[8]_ bit[9] bit[9]_ bit[10] bit[10]_ bit[11] bit[11]_ bit[12] bit[12]_ bit[13] bit[13]_ bit[14] bit[14]_ bit[15] bit[15]_ bit[16] bit[16]_ bit[17] bit[17]_ bit[18] bit[18]_
|
||||
00000 15.175,2.960 15.275,3.030 15.175,5.840 15.275,5.910 15.175,8.720 15.275,8.790 15.175,11.600 15.275,11.670 15.175,14.480 15.275,14.550 15.175,17.360 15.275,17.430 15.175,20.240 15.275,20.310 15.175,23.120 15.275,23.190 15.175,26.000 15.275,26.070 15.175,72.060 15.275,71.990 15.175,74.940 15.275,74.870 15.175,77.820 15.275,77.750 15.175,80.700 15.275,80.630 15.175,83.580 15.275,83.510 15.175,86.460 15.275,86.390 15.175,89.340 15.275,89.270 15.175,92.220 15.275,92.150 15.175,95.100 15.275,95.030 15.175,97.980 15.275,97.910
|
||||
00001 15.175,1.590 15.275,1.520 15.175,4.470 15.275,4.400 15.175,7.350 15.275,7.280 15.175,10.230 15.275,10.160 15.175,13.110 15.275,13.040 15.175,15.990 15.275,15.920 15.175,18.870 15.275,18.800 15.175,21.750 15.275,21.680 15.175,24.630 15.275,24.560 15.175,73.430 15.275,73.500 15.175,76.310 15.275,76.380 15.175,79.190 15.275,79.260 15.175,82.070 15.275,82.140 15.175,84.950 15.275,85.020 15.175,87.830 15.275,87.900 15.175,90.710 15.275,90.780 15.175,93.590 15.275,93.660 15.175,96.470 15.275,96.540 15.175,99.350 15.275,99.420
|
||||
00002 15.545,2.960 15.445,3.030 15.545,5.840 15.445,5.910 15.545,8.720 15.445,8.790 15.545,11.600 15.445,11.670 15.545,14.480 15.445,14.550 15.545,17.360 15.445,17.430 15.545,20.240 15.445,20.310 15.545,23.120 15.445,23.190 15.545,26.000 15.445,26.070 15.545,72.060 15.445,71.990 15.545,74.940 15.445,74.870 15.545,77.820 15.445,77.750 15.545,80.700 15.445,80.630 15.545,83.580 15.445,83.510 15.545,86.460 15.445,86.390 15.545,89.340 15.445,89.270 15.545,92.220 15.445,92.150 15.545,95.100 15.445,95.030 15.545,97.980 15.445,97.910
|
||||
00003 15.545,1.590 15.445,1.520 15.545,4.470 15.445,4.400 15.545,7.350 15.445,7.280 15.545,10.230 15.445,10.160 15.545,13.110 15.445,13.040 15.545,15.990 15.445,15.920 15.545,18.870 15.445,18.800 15.545,21.750 15.445,21.680 15.545,24.630 15.445,24.560 15.545,73.430 15.445,73.500 15.545,76.310 15.445,76.380 15.545,79.190 15.445,79.260 15.545,82.070 15.445,82.140 15.545,84.950 15.445,85.020 15.545,87.830 15.445,87.900 15.545,90.710 15.445,90.780 15.545,93.590 15.445,93.660 15.545,96.470 15.445,96.540 15.545,99.350 15.445,99.420
|
||||
00004 15.715,2.960 15.815,3.030 15.715,5.840 15.815,5.910 15.715,8.720 15.815,8.790 15.715,11.600 15.815,11.670 15.715,14.480 15.815,14.550 15.715,17.360 15.815,17.430 15.715,20.240 15.815,20.310 15.715,23.120 15.815,23.190 15.715,26.000 15.815,26.070 15.715,72.060 15.815,71.990 15.715,74.940 15.815,74.870 15.715,77.820 15.815,77.750 15.715,80.700 15.815,80.630 15.715,83.580 15.815,83.510 15.715,86.460 15.815,86.390 15.715,89.340 15.815,89.270 15.715,92.220 15.815,92.150 15.715,95.100 15.815,95.030 15.715,97.980 15.815,97.910
|
||||
00005 15.715,1.590 15.815,1.520 15.715,4.470 15.815,4.400 15.715,7.350 15.815,7.280 15.715,10.230 15.815,10.160 15.715,13.110 15.815,13.040 15.715,15.990 15.815,15.920 15.715,18.870 15.815,18.800 15.715,21.750 15.815,21.680 15.715,24.630 15.815,24.560 15.715,73.430 15.815,73.500 15.715,76.310 15.815,76.380 15.715,79.190 15.815,79.260 15.715,82.070 15.815,82.140 15.715,84.950 15.815,85.020 15.715,87.830 15.815,87.900 15.715,90.710 15.815,90.780 15.715,93.590 15.815,93.660 15.715,96.470 15.815,96.540 15.715,99.350 15.815,99.420
|
||||
00006 16.085,2.960 15.985,3.030 16.085,5.840 15.985,5.910 16.085,8.720 15.985,8.790 16.085,11.600 15.985,11.670 16.085,14.480 15.985,14.550 16.085,17.360 15.985,17.430 16.085,20.240 15.985,20.310 16.085,23.120 15.985,23.190 16.085,26.000 15.985,26.070 16.085,72.060 15.985,71.990 16.085,74.940 15.985,74.870 16.085,77.820 15.985,77.750 16.085,80.700 15.985,80.630 16.085,83.580 15.985,83.510 16.085,86.460 15.985,86.390 16.085,89.340 15.985,89.270 16.085,92.220 15.985,92.150 16.085,95.100 15.985,95.030 16.085,97.980 15.985,97.910
|
||||
00007 16.085,1.590 15.985,1.520 16.085,4.470 15.985,4.400 16.085,7.350 15.985,7.280 16.085,10.230 15.985,10.160 16.085,13.110 15.985,13.040 16.085,15.990 15.985,15.920 16.085,18.870 15.985,18.800 16.085,21.750 15.985,21.680 16.085,24.630 15.985,24.560 16.085,73.430 15.985,73.500 16.085,76.310 15.985,76.380 16.085,79.190 15.985,79.260 16.085,82.070 15.985,82.140 16.085,84.950 15.985,85.020 16.085,87.830 15.985,87.900 16.085,90.710 15.985,90.780 16.085,93.590 15.985,93.660 16.085,96.470 15.985,96.540 16.085,99.350 15.985,99.420
|
||||
00008 16.255,2.960 16.355,3.030 16.255,5.840 16.355,5.910 16.255,8.720 16.355,8.790 16.255,11.600 16.355,11.670 16.255,14.480 16.355,14.550 16.255,17.360 16.355,17.430 16.255,20.240 16.355,20.310 16.255,23.120 16.355,23.190 16.255,26.000 16.355,26.070 16.255,72.060 16.355,71.990 16.255,74.940 16.355,74.870 16.255,77.820 16.355,77.750 16.255,80.700 16.355,80.630 16.255,83.580 16.355,83.510 16.255,86.460 16.355,86.390 16.255,89.340 16.355,89.270 16.255,92.220 16.355,92.150 16.255,95.100 16.355,95.030 16.255,97.980 16.355,97.910
|
||||
00009 16.255,1.590 16.355,1.520 16.255,4.470 16.355,4.400 16.255,7.350 16.355,7.280 16.255,10.230 16.355,10.160 16.255,13.110 16.355,13.040 16.255,15.990 16.355,15.920 16.255,18.870 16.355,18.800 16.255,21.750 16.355,21.680 16.255,24.630 16.355,24.560 16.255,73.430 16.355,73.500 16.255,76.310 16.355,76.380 16.255,79.190 16.355,79.260 16.255,82.070 16.355,82.140 16.255,84.950 16.355,85.020 16.255,87.830 16.355,87.900 16.255,90.710 16.355,90.780 16.255,93.590 16.355,93.660 16.255,96.470 16.355,96.540 16.255,99.350 16.355,99.420
|
||||
0000A 16.625,2.960 16.525,3.030 16.625,5.840 16.525,5.910 16.625,8.720 16.525,8.790 16.625,11.600 16.525,11.670 16.625,14.480 16.525,14.550 16.625,17.360 16.525,17.430 16.625,20.240 16.525,20.310 16.625,23.120 16.525,23.190 16.625,26.000 16.525,26.070 16.625,72.060 16.525,71.990 16.625,74.940 16.525,74.870 16.625,77.820 16.525,77.750 16.625,80.700 16.525,80.630 16.625,83.580 16.525,83.510 16.625,86.460 16.525,86.390 16.625,89.340 16.525,89.270 16.625,92.220 16.525,92.150 16.625,95.100 16.525,95.030 16.625,97.980 16.525,97.910
|
||||
0000B 16.625,1.590 16.525,1.520 16.625,4.470 16.525,4.400 16.625,7.350 16.525,7.280 16.625,10.230 16.525,10.160 16.625,13.110 16.525,13.040 16.625,15.990 16.525,15.920 16.625,18.870 16.525,18.800 16.625,21.750 16.525,21.680 16.625,24.630 16.525,24.560 16.625,73.430 16.525,73.500 16.625,76.310 16.525,76.380 16.625,79.190 16.525,79.260 16.625,82.070 16.525,82.140 16.625,84.950 16.525,85.020 16.625,87.830 16.525,87.900 16.625,90.710 16.525,90.780 16.625,93.590 16.525,93.660 16.625,96.470 16.525,96.540 16.625,99.350 16.525,99.420
|
||||
0000C 16.795,2.960 16.895,3.030 16.795,5.840 16.895,5.910 16.795,8.720 16.895,8.790 16.795,11.600 16.895,11.670 16.795,14.480 16.895,14.550 16.795,17.360 16.895,17.430 16.795,20.240 16.895,20.310 16.795,23.120 16.895,23.190 16.795,26.000 16.895,26.070 16.795,72.060 16.895,71.990 16.795,74.940 16.895,74.870 16.795,77.820 16.895,77.750 16.795,80.700 16.895,80.630 16.795,83.580 16.895,83.510 16.795,86.460 16.895,86.390 16.795,89.340 16.895,89.270 16.795,92.220 16.895,92.150 16.795,95.100 16.895,95.030 16.795,97.980 16.895,97.910
|
||||
0000D 16.795,1.590 16.895,1.520 16.795,4.470 16.895,4.400 16.795,7.350 16.895,7.280 16.795,10.230 16.895,10.160 16.795,13.110 16.895,13.040 16.795,15.990 16.895,15.920 16.795,18.870 16.895,18.800 16.795,21.750 16.895,21.680 16.795,24.630 16.895,24.560 16.795,73.430 16.895,73.500 16.795,76.310 16.895,76.380 16.795,79.190 16.895,79.260 16.795,82.070 16.895,82.140 16.795,84.950 16.895,85.020 16.795,87.830 16.895,87.900 16.795,90.710 16.895,90.780 16.795,93.590 16.895,93.660 16.795,96.470 16.895,96.540 16.795,99.350 16.895,99.420
|
||||
0000E 17.165,2.960 17.065,3.030 17.165,5.840 17.065,5.910 17.165,8.720 17.065,8.790 17.165,11.600 17.065,11.670 17.165,14.480 17.065,14.550 17.165,17.360 17.065,17.430 17.165,20.240 17.065,20.310 17.165,23.120 17.065,23.190 17.165,26.000 17.065,26.070 17.165,72.060 17.065,71.990 17.165,74.940 17.065,74.870 17.165,77.820 17.065,77.750 17.165,80.700 17.065,80.630 17.165,83.580 17.065,83.510 17.165,86.460 17.065,86.390 17.165,89.340 17.065,89.270 17.165,92.220 17.065,92.150 17.165,95.100 17.065,95.030 17.165,97.980 17.065,97.910
|
||||
0000F 17.165,1.590 17.065,1.520 17.165,4.470 17.065,4.400 17.165,7.350 17.065,7.280 17.165,10.230 17.065,10.160 17.165,13.110 17.065,13.040 17.165,15.990 17.065,15.920 17.165,18.870 17.065,18.800 17.165,21.750 17.065,21.680 17.165,24.630 17.065,24.560 17.165,73.430 17.065,73.500 17.165,76.310 17.065,76.380 17.165,79.190 17.065,79.260 17.165,82.070 17.065,82.140 17.165,84.950 17.065,85.020 17.165,87.830 17.065,87.900 17.165,90.710 17.065,90.780 17.165,93.590 17.065,93.660 17.165,96.470 17.065,96.540 17.165,99.350 17.065,99.420
|
||||
00010 17.335,2.960 17.435,3.030 17.335,5.840 17.435,5.910 17.335,8.720 17.435,8.790 17.335,11.600 17.435,11.670 17.335,14.480 17.435,14.550 17.335,17.360 17.435,17.430 17.335,20.240 17.435,20.310 17.335,23.120 17.435,23.190 17.335,26.000 17.435,26.070 17.335,72.060 17.435,71.990 17.335,74.940 17.435,74.870 17.335,77.820 17.435,77.750 17.335,80.700 17.435,80.630 17.335,83.580 17.435,83.510 17.335,86.460 17.435,86.390 17.335,89.340 17.435,89.270 17.335,92.220 17.435,92.150 17.335,95.100 17.435,95.030 17.335,97.980 17.435,97.910
|
||||
00011 17.335,1.590 17.435,1.520 17.335,4.470 17.435,4.400 17.335,7.350 17.435,7.280 17.335,10.230 17.435,10.160 17.335,13.110 17.435,13.040 17.335,15.990 17.435,15.920 17.335,18.870 17.435,18.800 17.335,21.750 17.435,21.680 17.335,24.630 17.435,24.560 17.335,73.430 17.435,73.500 17.335,76.310 17.435,76.380 17.335,79.190 17.435,79.260 17.335,82.070 17.435,82.140 17.335,84.950 17.435,85.020 17.335,87.830 17.435,87.900 17.335,90.710 17.435,90.780 17.335,93.590 17.435,93.660 17.335,96.470 17.435,96.540 17.335,99.350 17.435,99.420
|
||||
00012 17.705,2.960 17.605,3.030 17.705,5.840 17.605,5.910 17.705,8.720 17.605,8.790 17.705,11.600 17.605,11.670 17.705,14.480 17.605,14.550 17.705,17.360 17.605,17.430 17.705,20.240 17.605,20.310 17.705,23.120 17.605,23.190 17.705,26.000 17.605,26.070 17.705,72.060 17.605,71.990 17.705,74.940 17.605,74.870 17.705,77.820 17.605,77.750 17.705,80.700 17.605,80.630 17.705,83.580 17.605,83.510 17.705,86.460 17.605,86.390 17.705,89.340 17.605,89.270 17.705,92.220 17.605,92.150 17.705,95.100 17.605,95.030 17.705,97.980 17.605,97.910
|
||||
00013 17.705,1.590 17.605,1.520 17.705,4.470 17.605,4.400 17.705,7.350 17.605,7.280 17.705,10.230 17.605,10.160 17.705,13.110 17.605,13.040 17.705,15.990 17.605,15.920 17.705,18.870 17.605,18.800 17.705,21.750 17.605,21.680 17.705,24.630 17.605,24.560 17.705,73.430 17.605,73.500 17.705,76.310 17.605,76.380 17.705,79.190 17.605,79.260 17.705,82.070 17.605,82.140 17.705,84.950 17.605,85.020 17.705,87.830 17.605,87.900 17.705,90.710 17.605,90.780 17.705,93.590 17.605,93.660 17.705,96.470 17.605,96.540 17.705,99.350 17.605,99.420
|
||||
00014 17.875,2.960 17.975,3.030 17.875,5.840 17.975,5.910 17.875,8.720 17.975,8.790 17.875,11.600 17.975,11.670 17.875,14.480 17.975,14.550 17.875,17.360 17.975,17.430 17.875,20.240 17.975,20.310 17.875,23.120 17.975,23.190 17.875,26.000 17.975,26.070 17.875,72.060 17.975,71.990 17.875,74.940 17.975,74.870 17.875,77.820 17.975,77.750 17.875,80.700 17.975,80.630 17.875,83.580 17.975,83.510 17.875,86.460 17.975,86.390 17.875,89.340 17.975,89.270 17.875,92.220 17.975,92.150 17.875,95.100 17.975,95.030 17.875,97.980 17.975,97.910
|
||||
00015 17.875,1.590 17.975,1.520 17.875,4.470 17.975,4.400 17.875,7.350 17.975,7.280 17.875,10.230 17.975,10.160 17.875,13.110 17.975,13.040 17.875,15.990 17.975,15.920 17.875,18.870 17.975,18.800 17.875,21.750 17.975,21.680 17.875,24.630 17.975,24.560 17.875,73.430 17.975,73.500 17.875,76.310 17.975,76.380 17.875,79.190 17.975,79.260 17.875,82.070 17.975,82.140 17.875,84.950 17.975,85.020 17.875,87.830 17.975,87.900 17.875,90.710 17.975,90.780 17.875,93.590 17.975,93.660 17.875,96.470 17.975,96.540 17.875,99.350 17.975,99.420
|
||||
00016 18.245,2.960 18.145,3.030 18.245,5.840 18.145,5.910 18.245,8.720 18.145,8.790 18.245,11.600 18.145,11.670 18.245,14.480 18.145,14.550 18.245,17.360 18.145,17.430 18.245,20.240 18.145,20.310 18.245,23.120 18.145,23.190 18.245,26.000 18.145,26.070 18.245,72.060 18.145,71.990 18.245,74.940 18.145,74.870 18.245,77.820 18.145,77.750 18.245,80.700 18.145,80.630 18.245,83.580 18.145,83.510 18.245,86.460 18.145,86.390 18.245,89.340 18.145,89.270 18.245,92.220 18.145,92.150 18.245,95.100 18.145,95.030 18.245,97.980 18.145,97.910
|
||||
00017 18.245,1.590 18.145,1.520 18.245,4.470 18.145,4.400 18.245,7.350 18.145,7.280 18.245,10.230 18.145,10.160 18.245,13.110 18.145,13.040 18.245,15.990 18.145,15.920 18.245,18.870 18.145,18.800 18.245,21.750 18.145,21.680 18.245,24.630 18.145,24.560 18.245,73.430 18.145,73.500 18.245,76.310 18.145,76.380 18.245,79.190 18.145,79.260 18.245,82.070 18.145,82.140 18.245,84.950 18.145,85.020 18.245,87.830 18.145,87.900 18.245,90.710 18.145,90.780 18.245,93.590 18.145,93.660 18.245,96.470 18.145,96.540 18.245,99.350 18.145,99.420
|
||||
00018 18.415,2.960 18.515,3.030 18.415,5.840 18.515,5.910 18.415,8.720 18.515,8.790 18.415,11.600 18.515,11.670 18.415,14.480 18.515,14.550 18.415,17.360 18.515,17.430 18.415,20.240 18.515,20.310 18.415,23.120 18.515,23.190 18.415,26.000 18.515,26.070 18.415,72.060 18.515,71.990 18.415,74.940 18.515,74.870 18.415,77.820 18.515,77.750 18.415,80.700 18.515,80.630 18.415,83.580 18.515,83.510 18.415,86.460 18.515,86.390 18.415,89.340 18.515,89.270 18.415,92.220 18.515,92.150 18.415,95.100 18.515,95.030 18.415,97.980 18.515,97.910
|
||||
00019 18.415,1.590 18.515,1.520 18.415,4.470 18.515,4.400 18.415,7.350 18.515,7.280 18.415,10.230 18.515,10.160 18.415,13.110 18.515,13.040 18.415,15.990 18.515,15.920 18.415,18.870 18.515,18.800 18.415,21.750 18.515,21.680 18.415,24.630 18.515,24.560 18.415,73.430 18.515,73.500 18.415,76.310 18.515,76.380 18.415,79.190 18.515,79.260 18.415,82.070 18.515,82.140 18.415,84.950 18.515,85.020 18.415,87.830 18.515,87.900 18.415,90.710 18.515,90.780 18.415,93.590 18.515,93.660 18.415,96.470 18.515,96.540 18.415,99.350 18.515,99.420
|
||||
0001A 18.785,2.960 18.685,3.030 18.785,5.840 18.685,5.910 18.785,8.720 18.685,8.790 18.785,11.600 18.685,11.670 18.785,14.480 18.685,14.550 18.785,17.360 18.685,17.430 18.785,20.240 18.685,20.310 18.785,23.120 18.685,23.190 18.785,26.000 18.685,26.070 18.785,72.060 18.685,71.990 18.785,74.940 18.685,74.870 18.785,77.820 18.685,77.750 18.785,80.700 18.685,80.630 18.785,83.580 18.685,83.510 18.785,86.460 18.685,86.390 18.785,89.340 18.685,89.270 18.785,92.220 18.685,92.150 18.785,95.100 18.685,95.030 18.785,97.980 18.685,97.910
|
||||
0001B 18.785,1.590 18.685,1.520 18.785,4.470 18.685,4.400 18.785,7.350 18.685,7.280 18.785,10.230 18.685,10.160 18.785,13.110 18.685,13.040 18.785,15.990 18.685,15.920 18.785,18.870 18.685,18.800 18.785,21.750 18.685,21.680 18.785,24.630 18.685,24.560 18.785,73.430 18.685,73.500 18.785,76.310 18.685,76.380 18.785,79.190 18.685,79.260 18.785,82.070 18.685,82.140 18.785,84.950 18.685,85.020 18.785,87.830 18.685,87.900 18.785,90.710 18.685,90.780 18.785,93.590 18.685,93.660 18.785,96.470 18.685,96.540 18.785,99.350 18.685,99.420
|
||||
0001C 18.955,2.960 19.055,3.030 18.955,5.840 19.055,5.910 18.955,8.720 19.055,8.790 18.955,11.600 19.055,11.670 18.955,14.480 19.055,14.550 18.955,17.360 19.055,17.430 18.955,20.240 19.055,20.310 18.955,23.120 19.055,23.190 18.955,26.000 19.055,26.070 18.955,72.060 19.055,71.990 18.955,74.940 19.055,74.870 18.955,77.820 19.055,77.750 18.955,80.700 19.055,80.630 18.955,83.580 19.055,83.510 18.955,86.460 19.055,86.390 18.955,89.340 19.055,89.270 18.955,92.220 19.055,92.150 18.955,95.100 19.055,95.030 18.955,97.980 19.055,97.910
|
||||
0001D 18.955,1.590 19.055,1.520 18.955,4.470 19.055,4.400 18.955,7.350 19.055,7.280 18.955,10.230 19.055,10.160 18.955,13.110 19.055,13.040 18.955,15.990 19.055,15.920 18.955,18.870 19.055,18.800 18.955,21.750 19.055,21.680 18.955,24.630 19.055,24.560 18.955,73.430 19.055,73.500 18.955,76.310 19.055,76.380 18.955,79.190 19.055,79.260 18.955,82.070 19.055,82.140 18.955,84.950 19.055,85.020 18.955,87.830 19.055,87.900 18.955,90.710 19.055,90.780 18.955,93.590 19.055,93.660 18.955,96.470 19.055,96.540 18.955,99.350 19.055,99.420
|
||||
0001E 19.325,2.960 19.225,3.030 19.325,5.840 19.225,5.910 19.325,8.720 19.225,8.790 19.325,11.600 19.225,11.670 19.325,14.480 19.225,14.550 19.325,17.360 19.225,17.430 19.325,20.240 19.225,20.310 19.325,23.120 19.225,23.190 19.325,26.000 19.225,26.070 19.325,72.060 19.225,71.990 19.325,74.940 19.225,74.870 19.325,77.820 19.225,77.750 19.325,80.700 19.225,80.630 19.325,83.580 19.225,83.510 19.325,86.460 19.225,86.390 19.325,89.340 19.225,89.270 19.325,92.220 19.225,92.150 19.325,95.100 19.225,95.030 19.325,97.980 19.225,97.910
|
||||
0001F 19.325,1.590 19.225,1.520 19.325,4.470 19.225,4.400 19.325,7.350 19.225,7.280 19.325,10.230 19.225,10.160 19.325,13.110 19.225,13.040 19.325,15.990 19.225,15.920 19.325,18.870 19.225,18.800 19.325,21.750 19.225,21.680 19.325,24.630 19.225,24.560 19.325,73.430 19.225,73.500 19.325,76.310 19.225,76.380 19.325,79.190 19.225,79.260 19.325,82.070 19.225,82.140 19.325,84.950 19.225,85.020 19.325,87.830 19.225,87.900 19.325,90.710 19.225,90.780 19.325,93.590 19.225,93.660 19.325,96.470 19.225,96.540 19.325,99.350 19.225,99.420
|
||||
00020 19.495,2.960 19.595,3.030 19.495,5.840 19.595,5.910 19.495,8.720 19.595,8.790 19.495,11.600 19.595,11.670 19.495,14.480 19.595,14.550 19.495,17.360 19.595,17.430 19.495,20.240 19.595,20.310 19.495,23.120 19.595,23.190 19.495,26.000 19.595,26.070 19.495,72.060 19.595,71.990 19.495,74.940 19.595,74.870 19.495,77.820 19.595,77.750 19.495,80.700 19.595,80.630 19.495,83.580 19.595,83.510 19.495,86.460 19.595,86.390 19.495,89.340 19.595,89.270 19.495,92.220 19.595,92.150 19.495,95.100 19.595,95.030 19.495,97.980 19.595,97.910
|
||||
00021 19.495,1.590 19.595,1.520 19.495,4.470 19.595,4.400 19.495,7.350 19.595,7.280 19.495,10.230 19.595,10.160 19.495,13.110 19.595,13.040 19.495,15.990 19.595,15.920 19.495,18.870 19.595,18.800 19.495,21.750 19.595,21.680 19.495,24.630 19.595,24.560 19.495,73.430 19.595,73.500 19.495,76.310 19.595,76.380 19.495,79.190 19.595,79.260 19.495,82.070 19.595,82.140 19.495,84.950 19.595,85.020 19.495,87.830 19.595,87.900 19.495,90.710 19.595,90.780 19.495,93.590 19.595,93.660 19.495,96.470 19.595,96.540 19.495,99.350 19.595,99.420
|
||||
00022 19.865,2.960 19.765,3.030 19.865,5.840 19.765,5.910 19.865,8.720 19.765,8.790 19.865,11.600 19.765,11.670 19.865,14.480 19.765,14.550 19.865,17.360 19.765,17.430 19.865,20.240 19.765,20.310 19.865,23.120 19.765,23.190 19.865,26.000 19.765,26.070 19.865,72.060 19.765,71.990 19.865,74.940 19.765,74.870 19.865,77.820 19.765,77.750 19.865,80.700 19.765,80.630 19.865,83.580 19.765,83.510 19.865,86.460 19.765,86.390 19.865,89.340 19.765,89.270 19.865,92.220 19.765,92.150 19.865,95.100 19.765,95.030 19.865,97.980 19.765,97.910
|
||||
00023 19.865,1.590 19.765,1.520 19.865,4.470 19.765,4.400 19.865,7.350 19.765,7.280 19.865,10.230 19.765,10.160 19.865,13.110 19.765,13.040 19.865,15.990 19.765,15.920 19.865,18.870 19.765,18.800 19.865,21.750 19.765,21.680 19.865,24.630 19.765,24.560 19.865,73.430 19.765,73.500 19.865,76.310 19.765,76.380 19.865,79.190 19.765,79.260 19.865,82.070 19.765,82.140 19.865,84.950 19.765,85.020 19.865,87.830 19.765,87.900 19.865,90.710 19.765,90.780 19.865,93.590 19.765,93.660 19.865,96.470 19.765,96.540 19.865,99.350 19.765,99.420
|
||||
00024 20.035,2.960 20.135,3.030 20.035,5.840 20.135,5.910 20.035,8.720 20.135,8.790 20.035,11.600 20.135,11.670 20.035,14.480 20.135,14.550 20.035,17.360 20.135,17.430 20.035,20.240 20.135,20.310 20.035,23.120 20.135,23.190 20.035,26.000 20.135,26.070 20.035,72.060 20.135,71.990 20.035,74.940 20.135,74.870 20.035,77.820 20.135,77.750 20.035,80.700 20.135,80.630 20.035,83.580 20.135,83.510 20.035,86.460 20.135,86.390 20.035,89.340 20.135,89.270 20.035,92.220 20.135,92.150 20.035,95.100 20.135,95.030 20.035,97.980 20.135,97.910
|
||||
00025 20.035,1.590 20.135,1.520 20.035,4.470 20.135,4.400 20.035,7.350 20.135,7.280 20.035,10.230 20.135,10.160 20.035,13.110 20.135,13.040 20.035,15.990 20.135,15.920 20.035,18.870 20.135,18.800 20.035,21.750 20.135,21.680 20.035,24.630 20.135,24.560 20.035,73.430 20.135,73.500 20.035,76.310 20.135,76.380 20.035,79.190 20.135,79.260 20.035,82.070 20.135,82.140 20.035,84.950 20.135,85.020 20.035,87.830 20.135,87.900 20.035,90.710 20.135,90.780 20.035,93.590 20.135,93.660 20.035,96.470 20.135,96.540 20.035,99.350 20.135,99.420
|
||||
00026 20.405,2.960 20.305,3.030 20.405,5.840 20.305,5.910 20.405,8.720 20.305,8.790 20.405,11.600 20.305,11.670 20.405,14.480 20.305,14.550 20.405,17.360 20.305,17.430 20.405,20.240 20.305,20.310 20.405,23.120 20.305,23.190 20.405,26.000 20.305,26.070 20.405,72.060 20.305,71.990 20.405,74.940 20.305,74.870 20.405,77.820 20.305,77.750 20.405,80.700 20.305,80.630 20.405,83.580 20.305,83.510 20.405,86.460 20.305,86.390 20.405,89.340 20.305,89.270 20.405,92.220 20.305,92.150 20.405,95.100 20.305,95.030 20.405,97.980 20.305,97.910
|
||||
00027 20.405,1.590 20.305,1.520 20.405,4.470 20.305,4.400 20.405,7.350 20.305,7.280 20.405,10.230 20.305,10.160 20.405,13.110 20.305,13.040 20.405,15.990 20.305,15.920 20.405,18.870 20.305,18.800 20.405,21.750 20.305,21.680 20.405,24.630 20.305,24.560 20.405,73.430 20.305,73.500 20.405,76.310 20.305,76.380 20.405,79.190 20.305,79.260 20.405,82.070 20.305,82.140 20.405,84.950 20.305,85.020 20.405,87.830 20.305,87.900 20.405,90.710 20.305,90.780 20.405,93.590 20.305,93.660 20.405,96.470 20.305,96.540 20.405,99.350 20.305,99.420
|
||||
00028 20.575,2.960 20.675,3.030 20.575,5.840 20.675,5.910 20.575,8.720 20.675,8.790 20.575,11.600 20.675,11.670 20.575,14.480 20.675,14.550 20.575,17.360 20.675,17.430 20.575,20.240 20.675,20.310 20.575,23.120 20.675,23.190 20.575,26.000 20.675,26.070 20.575,72.060 20.675,71.990 20.575,74.940 20.675,74.870 20.575,77.820 20.675,77.750 20.575,80.700 20.675,80.630 20.575,83.580 20.675,83.510 20.575,86.460 20.675,86.390 20.575,89.340 20.675,89.270 20.575,92.220 20.675,92.150 20.575,95.100 20.675,95.030 20.575,97.980 20.675,97.910
|
||||
00029 20.575,1.590 20.675,1.520 20.575,4.470 20.675,4.400 20.575,7.350 20.675,7.280 20.575,10.230 20.675,10.160 20.575,13.110 20.675,13.040 20.575,15.990 20.675,15.920 20.575,18.870 20.675,18.800 20.575,21.750 20.675,21.680 20.575,24.630 20.675,24.560 20.575,73.430 20.675,73.500 20.575,76.310 20.675,76.380 20.575,79.190 20.675,79.260 20.575,82.070 20.675,82.140 20.575,84.950 20.675,85.020 20.575,87.830 20.675,87.900 20.575,90.710 20.675,90.780 20.575,93.590 20.675,93.660 20.575,96.470 20.675,96.540 20.575,99.350 20.675,99.420
|
||||
0002A 20.945,2.960 20.845,3.030 20.945,5.840 20.845,5.910 20.945,8.720 20.845,8.790 20.945,11.600 20.845,11.670 20.945,14.480 20.845,14.550 20.945,17.360 20.845,17.430 20.945,20.240 20.845,20.310 20.945,23.120 20.845,23.190 20.945,26.000 20.845,26.070 20.945,72.060 20.845,71.990 20.945,74.940 20.845,74.870 20.945,77.820 20.845,77.750 20.945,80.700 20.845,80.630 20.945,83.580 20.845,83.510 20.945,86.460 20.845,86.390 20.945,89.340 20.845,89.270 20.945,92.220 20.845,92.150 20.945,95.100 20.845,95.030 20.945,97.980 20.845,97.910
|
||||
0002B 20.945,1.590 20.845,1.520 20.945,4.470 20.845,4.400 20.945,7.350 20.845,7.280 20.945,10.230 20.845,10.160 20.945,13.110 20.845,13.040 20.945,15.990 20.845,15.920 20.945,18.870 20.845,18.800 20.945,21.750 20.845,21.680 20.945,24.630 20.845,24.560 20.945,73.430 20.845,73.500 20.945,76.310 20.845,76.380 20.945,79.190 20.845,79.260 20.945,82.070 20.845,82.140 20.945,84.950 20.845,85.020 20.945,87.830 20.845,87.900 20.945,90.710 20.845,90.780 20.945,93.590 20.845,93.660 20.945,96.470 20.845,96.540 20.945,99.350 20.845,99.420
|
||||
0002C 21.115,2.960 21.215,3.030 21.115,5.840 21.215,5.910 21.115,8.720 21.215,8.790 21.115,11.600 21.215,11.670 21.115,14.480 21.215,14.550 21.115,17.360 21.215,17.430 21.115,20.240 21.215,20.310 21.115,23.120 21.215,23.190 21.115,26.000 21.215,26.070 21.115,72.060 21.215,71.990 21.115,74.940 21.215,74.870 21.115,77.820 21.215,77.750 21.115,80.700 21.215,80.630 21.115,83.580 21.215,83.510 21.115,86.460 21.215,86.390 21.115,89.340 21.215,89.270 21.115,92.220 21.215,92.150 21.115,95.100 21.215,95.030 21.115,97.980 21.215,97.910
|
||||
0002D 21.115,1.590 21.215,1.520 21.115,4.470 21.215,4.400 21.115,7.350 21.215,7.280 21.115,10.230 21.215,10.160 21.115,13.110 21.215,13.040 21.115,15.990 21.215,15.920 21.115,18.870 21.215,18.800 21.115,21.750 21.215,21.680 21.115,24.630 21.215,24.560 21.115,73.430 21.215,73.500 21.115,76.310 21.215,76.380 21.115,79.190 21.215,79.260 21.115,82.070 21.215,82.140 21.115,84.950 21.215,85.020 21.115,87.830 21.215,87.900 21.115,90.710 21.215,90.780 21.115,93.590 21.215,93.660 21.115,96.470 21.215,96.540 21.115,99.350 21.215,99.420
|
||||
0002E 21.485,2.960 21.385,3.030 21.485,5.840 21.385,5.910 21.485,8.720 21.385,8.790 21.485,11.600 21.385,11.670 21.485,14.480 21.385,14.550 21.485,17.360 21.385,17.430 21.485,20.240 21.385,20.310 21.485,23.120 21.385,23.190 21.485,26.000 21.385,26.070 21.485,72.060 21.385,71.990 21.485,74.940 21.385,74.870 21.485,77.820 21.385,77.750 21.485,80.700 21.385,80.630 21.485,83.580 21.385,83.510 21.485,86.460 21.385,86.390 21.485,89.340 21.385,89.270 21.485,92.220 21.385,92.150 21.485,95.100 21.385,95.030 21.485,97.980 21.385,97.910
|
||||
0002F 21.485,1.590 21.385,1.520 21.485,4.470 21.385,4.400 21.485,7.350 21.385,7.280 21.485,10.230 21.385,10.160 21.485,13.110 21.385,13.040 21.485,15.990 21.385,15.920 21.485,18.870 21.385,18.800 21.485,21.750 21.385,21.680 21.485,24.630 21.385,24.560 21.485,73.430 21.385,73.500 21.485,76.310 21.385,76.380 21.485,79.190 21.385,79.260 21.485,82.070 21.385,82.140 21.485,84.950 21.385,85.020 21.485,87.830 21.385,87.900 21.485,90.710 21.385,90.780 21.485,93.590 21.385,93.660 21.485,96.470 21.385,96.540 21.485,99.350 21.385,99.420
|
||||
00030 21.655,2.960 21.755,3.030 21.655,5.840 21.755,5.910 21.655,8.720 21.755,8.790 21.655,11.600 21.755,11.670 21.655,14.480 21.755,14.550 21.655,17.360 21.755,17.430 21.655,20.240 21.755,20.310 21.655,23.120 21.755,23.190 21.655,26.000 21.755,26.070 21.655,72.060 21.755,71.990 21.655,74.940 21.755,74.870 21.655,77.820 21.755,77.750 21.655,80.700 21.755,80.630 21.655,83.580 21.755,83.510 21.655,86.460 21.755,86.390 21.655,89.340 21.755,89.270 21.655,92.220 21.755,92.150 21.655,95.100 21.755,95.030 21.655,97.980 21.755,97.910
|
||||
00031 21.655,1.590 21.755,1.520 21.655,4.470 21.755,4.400 21.655,7.350 21.755,7.280 21.655,10.230 21.755,10.160 21.655,13.110 21.755,13.040 21.655,15.990 21.755,15.920 21.655,18.870 21.755,18.800 21.655,21.750 21.755,21.680 21.655,24.630 21.755,24.560 21.655,73.430 21.755,73.500 21.655,76.310 21.755,76.380 21.655,79.190 21.755,79.260 21.655,82.070 21.755,82.140 21.655,84.950 21.755,85.020 21.655,87.830 21.755,87.900 21.655,90.710 21.755,90.780 21.655,93.590 21.755,93.660 21.655,96.470 21.755,96.540 21.655,99.350 21.755,99.420
|
||||
00032 22.025,2.960 21.925,3.030 22.025,5.840 21.925,5.910 22.025,8.720 21.925,8.790 22.025,11.600 21.925,11.670 22.025,14.480 21.925,14.550 22.025,17.360 21.925,17.430 22.025,20.240 21.925,20.310 22.025,23.120 21.925,23.190 22.025,26.000 21.925,26.070 22.025,72.060 21.925,71.990 22.025,74.940 21.925,74.870 22.025,77.820 21.925,77.750 22.025,80.700 21.925,80.630 22.025,83.580 21.925,83.510 22.025,86.460 21.925,86.390 22.025,89.340 21.925,89.270 22.025,92.220 21.925,92.150 22.025,95.100 21.925,95.030 22.025,97.980 21.925,97.910
|
||||
00033 22.025,1.590 21.925,1.520 22.025,4.470 21.925,4.400 22.025,7.350 21.925,7.280 22.025,10.230 21.925,10.160 22.025,13.110 21.925,13.040 22.025,15.990 21.925,15.920 22.025,18.870 21.925,18.800 22.025,21.750 21.925,21.680 22.025,24.630 21.925,24.560 22.025,73.430 21.925,73.500 22.025,76.310 21.925,76.380 22.025,79.190 21.925,79.260 22.025,82.070 21.925,82.140 22.025,84.950 21.925,85.020 22.025,87.830 21.925,87.900 22.025,90.710 21.925,90.780 22.025,93.590 21.925,93.660 22.025,96.470 21.925,96.540 22.025,99.350 21.925,99.420
|
||||
00034 22.195,2.960 22.295,3.030 22.195,5.840 22.295,5.910 22.195,8.720 22.295,8.790 22.195,11.600 22.295,11.670 22.195,14.480 22.295,14.550 22.195,17.360 22.295,17.430 22.195,20.240 22.295,20.310 22.195,23.120 22.295,23.190 22.195,26.000 22.295,26.070 22.195,72.060 22.295,71.990 22.195,74.940 22.295,74.870 22.195,77.820 22.295,77.750 22.195,80.700 22.295,80.630 22.195,83.580 22.295,83.510 22.195,86.460 22.295,86.390 22.195,89.340 22.295,89.270 22.195,92.220 22.295,92.150 22.195,95.100 22.295,95.030 22.195,97.980 22.295,97.910
|
||||
00035 22.195,1.590 22.295,1.520 22.195,4.470 22.295,4.400 22.195,7.350 22.295,7.280 22.195,10.230 22.295,10.160 22.195,13.110 22.295,13.040 22.195,15.990 22.295,15.920 22.195,18.870 22.295,18.800 22.195,21.750 22.295,21.680 22.195,24.630 22.295,24.560 22.195,73.430 22.295,73.500 22.195,76.310 22.295,76.380 22.195,79.190 22.295,79.260 22.195,82.070 22.295,82.140 22.195,84.950 22.295,85.020 22.195,87.830 22.295,87.900 22.195,90.710 22.295,90.780 22.195,93.590 22.295,93.660 22.195,96.470 22.295,96.540 22.195,99.350 22.295,99.420
|
||||
00036 22.565,2.960 22.465,3.030 22.565,5.840 22.465,5.910 22.565,8.720 22.465,8.790 22.565,11.600 22.465,11.670 22.565,14.480 22.465,14.550 22.565,17.360 22.465,17.430 22.565,20.240 22.465,20.310 22.565,23.120 22.465,23.190 22.565,26.000 22.465,26.070 22.565,72.060 22.465,71.990 22.565,74.940 22.465,74.870 22.565,77.820 22.465,77.750 22.565,80.700 22.465,80.630 22.565,83.580 22.465,83.510 22.565,86.460 22.465,86.390 22.565,89.340 22.465,89.270 22.565,92.220 22.465,92.150 22.565,95.100 22.465,95.030 22.565,97.980 22.465,97.910
|
||||
00037 22.565,1.590 22.465,1.520 22.565,4.470 22.465,4.400 22.565,7.350 22.465,7.280 22.565,10.230 22.465,10.160 22.565,13.110 22.465,13.040 22.565,15.990 22.465,15.920 22.565,18.870 22.465,18.800 22.565,21.750 22.465,21.680 22.565,24.630 22.465,24.560 22.565,73.430 22.465,73.500 22.565,76.310 22.465,76.380 22.565,79.190 22.465,79.260 22.565,82.070 22.465,82.140 22.565,84.950 22.465,85.020 22.565,87.830 22.465,87.900 22.565,90.710 22.465,90.780 22.565,93.590 22.465,93.660 22.565,96.470 22.465,96.540 22.565,99.350 22.465,99.420
|
||||
00038 22.735,2.960 22.835,3.030 22.735,5.840 22.835,5.910 22.735,8.720 22.835,8.790 22.735,11.600 22.835,11.670 22.735,14.480 22.835,14.550 22.735,17.360 22.835,17.430 22.735,20.240 22.835,20.310 22.735,23.120 22.835,23.190 22.735,26.000 22.835,26.070 22.735,72.060 22.835,71.990 22.735,74.940 22.835,74.870 22.735,77.820 22.835,77.750 22.735,80.700 22.835,80.630 22.735,83.580 22.835,83.510 22.735,86.460 22.835,86.390 22.735,89.340 22.835,89.270 22.735,92.220 22.835,92.150 22.735,95.100 22.835,95.030 22.735,97.980 22.835,97.910
|
||||
00039 22.735,1.590 22.835,1.520 22.735,4.470 22.835,4.400 22.735,7.350 22.835,7.280 22.735,10.230 22.835,10.160 22.735,13.110 22.835,13.040 22.735,15.990 22.835,15.920 22.735,18.870 22.835,18.800 22.735,21.750 22.835,21.680 22.735,24.630 22.835,24.560 22.735,73.430 22.835,73.500 22.735,76.310 22.835,76.380 22.735,79.190 22.835,79.260 22.735,82.070 22.835,82.140 22.735,84.950 22.835,85.020 22.735,87.830 22.835,87.900 22.735,90.710 22.835,90.780 22.735,93.590 22.835,93.660 22.735,96.470 22.835,96.540 22.735,99.350 22.835,99.420
|
||||
0003A 23.105,2.960 23.005,3.030 23.105,5.840 23.005,5.910 23.105,8.720 23.005,8.790 23.105,11.600 23.005,11.670 23.105,14.480 23.005,14.550 23.105,17.360 23.005,17.430 23.105,20.240 23.005,20.310 23.105,23.120 23.005,23.190 23.105,26.000 23.005,26.070 23.105,72.060 23.005,71.990 23.105,74.940 23.005,74.870 23.105,77.820 23.005,77.750 23.105,80.700 23.005,80.630 23.105,83.580 23.005,83.510 23.105,86.460 23.005,86.390 23.105,89.340 23.005,89.270 23.105,92.220 23.005,92.150 23.105,95.100 23.005,95.030 23.105,97.980 23.005,97.910
|
||||
0003B 23.105,1.590 23.005,1.520 23.105,4.470 23.005,4.400 23.105,7.350 23.005,7.280 23.105,10.230 23.005,10.160 23.105,13.110 23.005,13.040 23.105,15.990 23.005,15.920 23.105,18.870 23.005,18.800 23.105,21.750 23.005,21.680 23.105,24.630 23.005,24.560 23.105,73.430 23.005,73.500 23.105,76.310 23.005,76.380 23.105,79.190 23.005,79.260 23.105,82.070 23.005,82.140 23.105,84.950 23.005,85.020 23.105,87.830 23.005,87.900 23.105,90.710 23.005,90.780 23.105,93.590 23.005,93.660 23.105,96.470 23.005,96.540 23.105,99.350 23.005,99.420
|
||||
0003C 23.275,2.960 23.375,3.030 23.275,5.840 23.375,5.910 23.275,8.720 23.375,8.790 23.275,11.600 23.375,11.670 23.275,14.480 23.375,14.550 23.275,17.360 23.375,17.430 23.275,20.240 23.375,20.310 23.275,23.120 23.375,23.190 23.275,26.000 23.375,26.070 23.275,72.060 23.375,71.990 23.275,74.940 23.375,74.870 23.275,77.820 23.375,77.750 23.275,80.700 23.375,80.630 23.275,83.580 23.375,83.510 23.275,86.460 23.375,86.390 23.275,89.340 23.375,89.270 23.275,92.220 23.375,92.150 23.275,95.100 23.375,95.030 23.275,97.980 23.375,97.910
|
||||
0003D 23.275,1.590 23.375,1.520 23.275,4.470 23.375,4.400 23.275,7.350 23.375,7.280 23.275,10.230 23.375,10.160 23.275,13.110 23.375,13.040 23.275,15.990 23.375,15.920 23.275,18.870 23.375,18.800 23.275,21.750 23.375,21.680 23.275,24.630 23.375,24.560 23.275,73.430 23.375,73.500 23.275,76.310 23.375,76.380 23.275,79.190 23.375,79.260 23.275,82.070 23.375,82.140 23.275,84.950 23.375,85.020 23.275,87.830 23.375,87.900 23.275,90.710 23.375,90.780 23.275,93.590 23.375,93.660 23.275,96.470 23.375,96.540 23.275,99.350 23.375,99.420
|
||||
0003E 23.645,2.960 23.545,3.030 23.645,5.840 23.545,5.910 23.645,8.720 23.545,8.790 23.645,11.600 23.545,11.670 23.645,14.480 23.545,14.550 23.645,17.360 23.545,17.430 23.645,20.240 23.545,20.310 23.645,23.120 23.545,23.190 23.645,26.000 23.545,26.070 23.645,72.060 23.545,71.990 23.645,74.940 23.545,74.870 23.645,77.820 23.545,77.750 23.645,80.700 23.545,80.630 23.645,83.580 23.545,83.510 23.645,86.460 23.545,86.390 23.645,89.340 23.545,89.270 23.645,92.220 23.545,92.150 23.645,95.100 23.545,95.030 23.645,97.980 23.545,97.910
|
||||
0003F 23.645,1.590 23.545,1.520 23.645,4.470 23.545,4.400 23.645,7.350 23.545,7.280 23.645,10.230 23.545,10.160 23.645,13.110 23.545,13.040 23.645,15.990 23.545,15.920 23.645,18.870 23.545,18.800 23.645,21.750 23.545,21.680 23.645,24.630 23.545,24.560 23.645,73.430 23.545,73.500 23.645,76.310 23.545,76.380 23.645,79.190 23.545,79.260 23.645,82.070 23.545,82.140 23.645,84.950 23.545,85.020 23.645,87.830 23.545,87.900 23.645,90.710 23.545,90.780 23.645,93.590 23.545,93.660 23.645,96.470 23.545,96.540 23.645,99.350 23.545,99.420
|
||||
00040 23.815,2.960 23.915,3.030 23.815,5.840 23.915,5.910 23.815,8.720 23.915,8.790 23.815,11.600 23.915,11.670 23.815,14.480 23.915,14.550 23.815,17.360 23.915,17.430 23.815,20.240 23.915,20.310 23.815,23.120 23.915,23.190 23.815,26.000 23.915,26.070 23.815,72.060 23.915,71.990 23.815,74.940 23.915,74.870 23.815,77.820 23.915,77.750 23.815,80.700 23.915,80.630 23.815,83.580 23.915,83.510 23.815,86.460 23.915,86.390 23.815,89.340 23.915,89.270 23.815,92.220 23.915,92.150 23.815,95.100 23.915,95.030 23.815,97.980 23.915,97.910
|
||||
00041 23.815,1.590 23.915,1.520 23.815,4.470 23.915,4.400 23.815,7.350 23.915,7.280 23.815,10.230 23.915,10.160 23.815,13.110 23.915,13.040 23.815,15.990 23.915,15.920 23.815,18.870 23.915,18.800 23.815,21.750 23.915,21.680 23.815,24.630 23.915,24.560 23.815,73.430 23.915,73.500 23.815,76.310 23.915,76.380 23.815,79.190 23.915,79.260 23.815,82.070 23.915,82.140 23.815,84.950 23.915,85.020 23.815,87.830 23.915,87.900 23.815,90.710 23.915,90.780 23.815,93.590 23.915,93.660 23.815,96.470 23.915,96.540 23.815,99.350 23.915,99.420
|
||||
00042 24.185,2.960 24.085,3.030 24.185,5.840 24.085,5.910 24.185,8.720 24.085,8.790 24.185,11.600 24.085,11.670 24.185,14.480 24.085,14.550 24.185,17.360 24.085,17.430 24.185,20.240 24.085,20.310 24.185,23.120 24.085,23.190 24.185,26.000 24.085,26.070 24.185,72.060 24.085,71.990 24.185,74.940 24.085,74.870 24.185,77.820 24.085,77.750 24.185,80.700 24.085,80.630 24.185,83.580 24.085,83.510 24.185,86.460 24.085,86.390 24.185,89.340 24.085,89.270 24.185,92.220 24.085,92.150 24.185,95.100 24.085,95.030 24.185,97.980 24.085,97.910
|
||||
00043 24.185,1.590 24.085,1.520 24.185,4.470 24.085,4.400 24.185,7.350 24.085,7.280 24.185,10.230 24.085,10.160 24.185,13.110 24.085,13.040 24.185,15.990 24.085,15.920 24.185,18.870 24.085,18.800 24.185,21.750 24.085,21.680 24.185,24.630 24.085,24.560 24.185,73.430 24.085,73.500 24.185,76.310 24.085,76.380 24.185,79.190 24.085,79.260 24.185,82.070 24.085,82.140 24.185,84.950 24.085,85.020 24.185,87.830 24.085,87.900 24.185,90.710 24.085,90.780 24.185,93.590 24.085,93.660 24.185,96.470 24.085,96.540 24.185,99.350 24.085,99.420
|
||||
00044 24.355,2.960 24.455,3.030 24.355,5.840 24.455,5.910 24.355,8.720 24.455,8.790 24.355,11.600 24.455,11.670 24.355,14.480 24.455,14.550 24.355,17.360 24.455,17.430 24.355,20.240 24.455,20.310 24.355,23.120 24.455,23.190 24.355,26.000 24.455,26.070 24.355,72.060 24.455,71.990 24.355,74.940 24.455,74.870 24.355,77.820 24.455,77.750 24.355,80.700 24.455,80.630 24.355,83.580 24.455,83.510 24.355,86.460 24.455,86.390 24.355,89.340 24.455,89.270 24.355,92.220 24.455,92.150 24.355,95.100 24.455,95.030 24.355,97.980 24.455,97.910
|
||||
00045 24.355,1.590 24.455,1.520 24.355,4.470 24.455,4.400 24.355,7.350 24.455,7.280 24.355,10.230 24.455,10.160 24.355,13.110 24.455,13.040 24.355,15.990 24.455,15.920 24.355,18.870 24.455,18.800 24.355,21.750 24.455,21.680 24.355,24.630 24.455,24.560 24.355,73.430 24.455,73.500 24.355,76.310 24.455,76.380 24.355,79.190 24.455,79.260 24.355,82.070 24.455,82.140 24.355,84.950 24.455,85.020 24.355,87.830 24.455,87.900 24.355,90.710 24.455,90.780 24.355,93.590 24.455,93.660 24.355,96.470 24.455,96.540 24.355,99.350 24.455,99.420
|
||||
00046 24.725,2.960 24.625,3.030 24.725,5.840 24.625,5.910 24.725,8.720 24.625,8.790 24.725,11.600 24.625,11.670 24.725,14.480 24.625,14.550 24.725,17.360 24.625,17.430 24.725,20.240 24.625,20.310 24.725,23.120 24.625,23.190 24.725,26.000 24.625,26.070 24.725,72.060 24.625,71.990 24.725,74.940 24.625,74.870 24.725,77.820 24.625,77.750 24.725,80.700 24.625,80.630 24.725,83.580 24.625,83.510 24.725,86.460 24.625,86.390 24.725,89.340 24.625,89.270 24.725,92.220 24.625,92.150 24.725,95.100 24.625,95.030 24.725,97.980 24.625,97.910
|
||||
00047 24.725,1.590 24.625,1.520 24.725,4.470 24.625,4.400 24.725,7.350 24.625,7.280 24.725,10.230 24.625,10.160 24.725,13.110 24.625,13.040 24.725,15.990 24.625,15.920 24.725,18.870 24.625,18.800 24.725,21.750 24.625,21.680 24.725,24.630 24.625,24.560 24.725,73.430 24.625,73.500 24.725,76.310 24.625,76.380 24.725,79.190 24.625,79.260 24.725,82.070 24.625,82.140 24.725,84.950 24.625,85.020 24.725,87.830 24.625,87.900 24.725,90.710 24.625,90.780 24.725,93.590 24.625,93.660 24.725,96.470 24.625,96.540 24.725,99.350 24.625,99.420
|
||||
00048 24.895,2.960 24.995,3.030 24.895,5.840 24.995,5.910 24.895,8.720 24.995,8.790 24.895,11.600 24.995,11.670 24.895,14.480 24.995,14.550 24.895,17.360 24.995,17.430 24.895,20.240 24.995,20.310 24.895,23.120 24.995,23.190 24.895,26.000 24.995,26.070 24.895,72.060 24.995,71.990 24.895,74.940 24.995,74.870 24.895,77.820 24.995,77.750 24.895,80.700 24.995,80.630 24.895,83.580 24.995,83.510 24.895,86.460 24.995,86.390 24.895,89.340 24.995,89.270 24.895,92.220 24.995,92.150 24.895,95.100 24.995,95.030 24.895,97.980 24.995,97.910
|
||||
00049 24.895,1.590 24.995,1.520 24.895,4.470 24.995,4.400 24.895,7.350 24.995,7.280 24.895,10.230 24.995,10.160 24.895,13.110 24.995,13.040 24.895,15.990 24.995,15.920 24.895,18.870 24.995,18.800 24.895,21.750 24.995,21.680 24.895,24.630 24.995,24.560 24.895,73.430 24.995,73.500 24.895,76.310 24.995,76.380 24.895,79.190 24.995,79.260 24.895,82.070 24.995,82.140 24.895,84.950 24.995,85.020 24.895,87.830 24.995,87.900 24.895,90.710 24.995,90.780 24.895,93.590 24.995,93.660 24.895,96.470 24.995,96.540 24.895,99.350 24.995,99.420
|
||||
0004A 25.265,2.960 25.165,3.030 25.265,5.840 25.165,5.910 25.265,8.720 25.165,8.790 25.265,11.600 25.165,11.670 25.265,14.480 25.165,14.550 25.265,17.360 25.165,17.430 25.265,20.240 25.165,20.310 25.265,23.120 25.165,23.190 25.265,26.000 25.165,26.070 25.265,72.060 25.165,71.990 25.265,74.940 25.165,74.870 25.265,77.820 25.165,77.750 25.265,80.700 25.165,80.630 25.265,83.580 25.165,83.510 25.265,86.460 25.165,86.390 25.265,89.340 25.165,89.270 25.265,92.220 25.165,92.150 25.265,95.100 25.165,95.030 25.265,97.980 25.165,97.910
|
||||
0004B 25.265,1.590 25.165,1.520 25.265,4.470 25.165,4.400 25.265,7.350 25.165,7.280 25.265,10.230 25.165,10.160 25.265,13.110 25.165,13.040 25.265,15.990 25.165,15.920 25.265,18.870 25.165,18.800 25.265,21.750 25.165,21.680 25.265,24.630 25.165,24.560 25.265,73.430 25.165,73.500 25.265,76.310 25.165,76.380 25.265,79.190 25.165,79.260 25.265,82.070 25.165,82.140 25.265,84.950 25.165,85.020 25.265,87.830 25.165,87.900 25.265,90.710 25.165,90.780 25.265,93.590 25.165,93.660 25.265,96.470 25.165,96.540 25.265,99.350 25.165,99.420
|
||||
0004C 25.435,2.960 25.535,3.030 25.435,5.840 25.535,5.910 25.435,8.720 25.535,8.790 25.435,11.600 25.535,11.670 25.435,14.480 25.535,14.550 25.435,17.360 25.535,17.430 25.435,20.240 25.535,20.310 25.435,23.120 25.535,23.190 25.435,26.000 25.535,26.070 25.435,72.060 25.535,71.990 25.435,74.940 25.535,74.870 25.435,77.820 25.535,77.750 25.435,80.700 25.535,80.630 25.435,83.580 25.535,83.510 25.435,86.460 25.535,86.390 25.435,89.340 25.535,89.270 25.435,92.220 25.535,92.150 25.435,95.100 25.535,95.030 25.435,97.980 25.535,97.910
|
||||
0004D 25.435,1.590 25.535,1.520 25.435,4.470 25.535,4.400 25.435,7.350 25.535,7.280 25.435,10.230 25.535,10.160 25.435,13.110 25.535,13.040 25.435,15.990 25.535,15.920 25.435,18.870 25.535,18.800 25.435,21.750 25.535,21.680 25.435,24.630 25.535,24.560 25.435,73.430 25.535,73.500 25.435,76.310 25.535,76.380 25.435,79.190 25.535,79.260 25.435,82.070 25.535,82.140 25.435,84.950 25.535,85.020 25.435,87.830 25.535,87.900 25.435,90.710 25.535,90.780 25.435,93.590 25.535,93.660 25.435,96.470 25.535,96.540 25.435,99.350 25.535,99.420
|
||||
0004E 25.805,2.960 25.705,3.030 25.805,5.840 25.705,5.910 25.805,8.720 25.705,8.790 25.805,11.600 25.705,11.670 25.805,14.480 25.705,14.550 25.805,17.360 25.705,17.430 25.805,20.240 25.705,20.310 25.805,23.120 25.705,23.190 25.805,26.000 25.705,26.070 25.805,72.060 25.705,71.990 25.805,74.940 25.705,74.870 25.805,77.820 25.705,77.750 25.805,80.700 25.705,80.630 25.805,83.580 25.705,83.510 25.805,86.460 25.705,86.390 25.805,89.340 25.705,89.270 25.805,92.220 25.705,92.150 25.805,95.100 25.705,95.030 25.805,97.980 25.705,97.910
|
||||
0004F 25.805,1.590 25.705,1.520 25.805,4.470 25.705,4.400 25.805,7.350 25.705,7.280 25.805,10.230 25.705,10.160 25.805,13.110 25.705,13.040 25.805,15.990 25.705,15.920 25.805,18.870 25.705,18.800 25.805,21.750 25.705,21.680 25.805,24.630 25.705,24.560 25.805,73.430 25.705,73.500 25.805,76.310 25.705,76.380 25.805,79.190 25.705,79.260 25.805,82.070 25.705,82.140 25.805,84.950 25.705,85.020 25.805,87.830 25.705,87.900 25.805,90.710 25.705,90.780 25.805,93.590 25.705,93.660 25.805,96.470 25.705,96.540 25.805,99.350 25.705,99.420
|
||||
00050 25.975,2.960 26.075,3.030 25.975,5.840 26.075,5.910 25.975,8.720 26.075,8.790 25.975,11.600 26.075,11.670 25.975,14.480 26.075,14.550 25.975,17.360 26.075,17.430 25.975,20.240 26.075,20.310 25.975,23.120 26.075,23.190 25.975,26.000 26.075,26.070 25.975,72.060 26.075,71.990 25.975,74.940 26.075,74.870 25.975,77.820 26.075,77.750 25.975,80.700 26.075,80.630 25.975,83.580 26.075,83.510 25.975,86.460 26.075,86.390 25.975,89.340 26.075,89.270 25.975,92.220 26.075,92.150 25.975,95.100 26.075,95.030 25.975,97.980 26.075,97.910
|
||||
00051 25.975,1.590 26.075,1.520 25.975,4.470 26.075,4.400 25.975,7.350 26.075,7.280 25.975,10.230 26.075,10.160 25.975,13.110 26.075,13.040 25.975,15.990 26.075,15.920 25.975,18.870 26.075,18.800 25.975,21.750 26.075,21.680 25.975,24.630 26.075,24.560 25.975,73.430 26.075,73.500 25.975,76.310 26.075,76.380 25.975,79.190 26.075,79.260 25.975,82.070 26.075,82.140 25.975,84.950 26.075,85.020 25.975,87.830 26.075,87.900 25.975,90.710 26.075,90.780 25.975,93.590 26.075,93.660 25.975,96.470 26.075,96.540 25.975,99.350 26.075,99.420
|
||||
00052 26.345,2.960 26.245,3.030 26.345,5.840 26.245,5.910 26.345,8.720 26.245,8.790 26.345,11.600 26.245,11.670 26.345,14.480 26.245,14.550 26.345,17.360 26.245,17.430 26.345,20.240 26.245,20.310 26.345,23.120 26.245,23.190 26.345,26.000 26.245,26.070 26.345,72.060 26.245,71.990 26.345,74.940 26.245,74.870 26.345,77.820 26.245,77.750 26.345,80.700 26.245,80.630 26.345,83.580 26.245,83.510 26.345,86.460 26.245,86.390 26.345,89.340 26.245,89.270 26.345,92.220 26.245,92.150 26.345,95.100 26.245,95.030 26.345,97.980 26.245,97.910
|
||||
00053 26.345,1.590 26.245,1.520 26.345,4.470 26.245,4.400 26.345,7.350 26.245,7.280 26.345,10.230 26.245,10.160 26.345,13.110 26.245,13.040 26.345,15.990 26.245,15.920 26.345,18.870 26.245,18.800 26.345,21.750 26.245,21.680 26.345,24.630 26.245,24.560 26.345,73.430 26.245,73.500 26.345,76.310 26.245,76.380 26.345,79.190 26.245,79.260 26.345,82.070 26.245,82.140 26.345,84.950 26.245,85.020 26.345,87.830 26.245,87.900 26.345,90.710 26.245,90.780 26.345,93.590 26.245,93.660 26.345,96.470 26.245,96.540 26.345,99.350 26.245,99.420
|
||||
00054 26.515,2.960 26.615,3.030 26.515,5.840 26.615,5.910 26.515,8.720 26.615,8.790 26.515,11.600 26.615,11.670 26.515,14.480 26.615,14.550 26.515,17.360 26.615,17.430 26.515,20.240 26.615,20.310 26.515,23.120 26.615,23.190 26.515,26.000 26.615,26.070 26.515,72.060 26.615,71.990 26.515,74.940 26.615,74.870 26.515,77.820 26.615,77.750 26.515,80.700 26.615,80.630 26.515,83.580 26.615,83.510 26.515,86.460 26.615,86.390 26.515,89.340 26.615,89.270 26.515,92.220 26.615,92.150 26.515,95.100 26.615,95.030 26.515,97.980 26.615,97.910
|
||||
00055 26.515,1.590 26.615,1.520 26.515,4.470 26.615,4.400 26.515,7.350 26.615,7.280 26.515,10.230 26.615,10.160 26.515,13.110 26.615,13.040 26.515,15.990 26.615,15.920 26.515,18.870 26.615,18.800 26.515,21.750 26.615,21.680 26.515,24.630 26.615,24.560 26.515,73.430 26.615,73.500 26.515,76.310 26.615,76.380 26.515,79.190 26.615,79.260 26.515,82.070 26.615,82.140 26.515,84.950 26.615,85.020 26.515,87.830 26.615,87.900 26.515,90.710 26.615,90.780 26.515,93.590 26.615,93.660 26.515,96.470 26.615,96.540 26.515,99.350 26.615,99.420
|
||||
00056 26.885,2.960 26.785,3.030 26.885,5.840 26.785,5.910 26.885,8.720 26.785,8.790 26.885,11.600 26.785,11.670 26.885,14.480 26.785,14.550 26.885,17.360 26.785,17.430 26.885,20.240 26.785,20.310 26.885,23.120 26.785,23.190 26.885,26.000 26.785,26.070 26.885,72.060 26.785,71.990 26.885,74.940 26.785,74.870 26.885,77.820 26.785,77.750 26.885,80.700 26.785,80.630 26.885,83.580 26.785,83.510 26.885,86.460 26.785,86.390 26.885,89.340 26.785,89.270 26.885,92.220 26.785,92.150 26.885,95.100 26.785,95.030 26.885,97.980 26.785,97.910
|
||||
00057 26.885,1.590 26.785,1.520 26.885,4.470 26.785,4.400 26.885,7.350 26.785,7.280 26.885,10.230 26.785,10.160 26.885,13.110 26.785,13.040 26.885,15.990 26.785,15.920 26.885,18.870 26.785,18.800 26.885,21.750 26.785,21.680 26.885,24.630 26.785,24.560 26.885,73.430 26.785,73.500 26.885,76.310 26.785,76.380 26.885,79.190 26.785,79.260 26.885,82.070 26.785,82.140 26.885,84.950 26.785,85.020 26.885,87.830 26.785,87.900 26.885,90.710 26.785,90.780 26.885,93.590 26.785,93.660 26.885,96.470 26.785,96.540 26.885,99.350 26.785,99.420
|
||||
00058 27.055,2.960 27.155,3.030 27.055,5.840 27.155,5.910 27.055,8.720 27.155,8.790 27.055,11.600 27.155,11.670 27.055,14.480 27.155,14.550 27.055,17.360 27.155,17.430 27.055,20.240 27.155,20.310 27.055,23.120 27.155,23.190 27.055,26.000 27.155,26.070 27.055,72.060 27.155,71.990 27.055,74.940 27.155,74.870 27.055,77.820 27.155,77.750 27.055,80.700 27.155,80.630 27.055,83.580 27.155,83.510 27.055,86.460 27.155,86.390 27.055,89.340 27.155,89.270 27.055,92.220 27.155,92.150 27.055,95.100 27.155,95.030 27.055,97.980 27.155,97.910
|
||||
00059 27.055,1.590 27.155,1.520 27.055,4.470 27.155,4.400 27.055,7.350 27.155,7.280 27.055,10.230 27.155,10.160 27.055,13.110 27.155,13.040 27.055,15.990 27.155,15.920 27.055,18.870 27.155,18.800 27.055,21.750 27.155,21.680 27.055,24.630 27.155,24.560 27.055,73.430 27.155,73.500 27.055,76.310 27.155,76.380 27.055,79.190 27.155,79.260 27.055,82.070 27.155,82.140 27.055,84.950 27.155,85.020 27.055,87.830 27.155,87.900 27.055,90.710 27.155,90.780 27.055,93.590 27.155,93.660 27.055,96.470 27.155,96.540 27.055,99.350 27.155,99.420
|
||||
0005A 27.425,2.960 27.325,3.030 27.425,5.840 27.325,5.910 27.425,8.720 27.325,8.790 27.425,11.600 27.325,11.670 27.425,14.480 27.325,14.550 27.425,17.360 27.325,17.430 27.425,20.240 27.325,20.310 27.425,23.120 27.325,23.190 27.425,26.000 27.325,26.070 27.425,72.060 27.325,71.990 27.425,74.940 27.325,74.870 27.425,77.820 27.325,77.750 27.425,80.700 27.325,80.630 27.425,83.580 27.325,83.510 27.425,86.460 27.325,86.390 27.425,89.340 27.325,89.270 27.425,92.220 27.325,92.150 27.425,95.100 27.325,95.030 27.425,97.980 27.325,97.910
|
||||
0005B 27.425,1.590 27.325,1.520 27.425,4.470 27.325,4.400 27.425,7.350 27.325,7.280 27.425,10.230 27.325,10.160 27.425,13.110 27.325,13.040 27.425,15.990 27.325,15.920 27.425,18.870 27.325,18.800 27.425,21.750 27.325,21.680 27.425,24.630 27.325,24.560 27.425,73.430 27.325,73.500 27.425,76.310 27.325,76.380 27.425,79.190 27.325,79.260 27.425,82.070 27.325,82.140 27.425,84.950 27.325,85.020 27.425,87.830 27.325,87.900 27.425,90.710 27.325,90.780 27.425,93.590 27.325,93.660 27.425,96.470 27.325,96.540 27.425,99.350 27.325,99.420
|
||||
0005C 27.595,2.960 27.695,3.030 27.595,5.840 27.695,5.910 27.595,8.720 27.695,8.790 27.595,11.600 27.695,11.670 27.595,14.480 27.695,14.550 27.595,17.360 27.695,17.430 27.595,20.240 27.695,20.310 27.595,23.120 27.695,23.190 27.595,26.000 27.695,26.070 27.595,72.060 27.695,71.990 27.595,74.940 27.695,74.870 27.595,77.820 27.695,77.750 27.595,80.700 27.695,80.630 27.595,83.580 27.695,83.510 27.595,86.460 27.695,86.390 27.595,89.340 27.695,89.270 27.595,92.220 27.695,92.150 27.595,95.100 27.695,95.030 27.595,97.980 27.695,97.910
|
||||
0005D 27.595,1.590 27.695,1.520 27.595,4.470 27.695,4.400 27.595,7.350 27.695,7.280 27.595,10.230 27.695,10.160 27.595,13.110 27.695,13.040 27.595,15.990 27.695,15.920 27.595,18.870 27.695,18.800 27.595,21.750 27.695,21.680 27.595,24.630 27.695,24.560 27.595,73.430 27.695,73.500 27.595,76.310 27.695,76.380 27.595,79.190 27.695,79.260 27.595,82.070 27.695,82.140 27.595,84.950 27.695,85.020 27.595,87.830 27.695,87.900 27.595,90.710 27.695,90.780 27.595,93.590 27.695,93.660 27.595,96.470 27.695,96.540 27.595,99.350 27.695,99.420
|
||||
0005E 27.965,2.960 27.865,3.030 27.965,5.840 27.865,5.910 27.965,8.720 27.865,8.790 27.965,11.600 27.865,11.670 27.965,14.480 27.865,14.550 27.965,17.360 27.865,17.430 27.965,20.240 27.865,20.310 27.965,23.120 27.865,23.190 27.965,26.000 27.865,26.070 27.965,72.060 27.865,71.990 27.965,74.940 27.865,74.870 27.965,77.820 27.865,77.750 27.965,80.700 27.865,80.630 27.965,83.580 27.865,83.510 27.965,86.460 27.865,86.390 27.965,89.340 27.865,89.270 27.965,92.220 27.865,92.150 27.965,95.100 27.865,95.030 27.965,97.980 27.865,97.910
|
||||
0005F 27.965,1.590 27.865,1.520 27.965,4.470 27.865,4.400 27.965,7.350 27.865,7.280 27.965,10.230 27.865,10.160 27.965,13.110 27.865,13.040 27.965,15.990 27.865,15.920 27.965,18.870 27.865,18.800 27.965,21.750 27.865,21.680 27.965,24.630 27.865,24.560 27.965,73.430 27.865,73.500 27.965,76.310 27.865,76.380 27.965,79.190 27.865,79.260 27.965,82.070 27.865,82.140 27.965,84.950 27.865,85.020 27.965,87.830 27.865,87.900 27.965,90.710 27.865,90.780 27.965,93.590 27.865,93.660 27.965,96.470 27.865,96.540 27.965,99.350 27.865,99.420
|
||||
00060 28.135,2.960 28.235,3.030 28.135,5.840 28.235,5.910 28.135,8.720 28.235,8.790 28.135,11.600 28.235,11.670 28.135,14.480 28.235,14.550 28.135,17.360 28.235,17.430 28.135,20.240 28.235,20.310 28.135,23.120 28.235,23.190 28.135,26.000 28.235,26.070 28.135,72.060 28.235,71.990 28.135,74.940 28.235,74.870 28.135,77.820 28.235,77.750 28.135,80.700 28.235,80.630 28.135,83.580 28.235,83.510 28.135,86.460 28.235,86.390 28.135,89.340 28.235,89.270 28.135,92.220 28.235,92.150 28.135,95.100 28.235,95.030 28.135,97.980 28.235,97.910
|
||||
00061 28.135,1.590 28.235,1.520 28.135,4.470 28.235,4.400 28.135,7.350 28.235,7.280 28.135,10.230 28.235,10.160 28.135,13.110 28.235,13.040 28.135,15.990 28.235,15.920 28.135,18.870 28.235,18.800 28.135,21.750 28.235,21.680 28.135,24.630 28.235,24.560 28.135,73.430 28.235,73.500 28.135,76.310 28.235,76.380 28.135,79.190 28.235,79.260 28.135,82.070 28.235,82.140 28.135,84.950 28.235,85.020 28.135,87.830 28.235,87.900 28.135,90.710 28.235,90.780 28.135,93.590 28.235,93.660 28.135,96.470 28.235,96.540 28.135,99.350 28.235,99.420
|
||||
00062 28.505,2.960 28.405,3.030 28.505,5.840 28.405,5.910 28.505,8.720 28.405,8.790 28.505,11.600 28.405,11.670 28.505,14.480 28.405,14.550 28.505,17.360 28.405,17.430 28.505,20.240 28.405,20.310 28.505,23.120 28.405,23.190 28.505,26.000 28.405,26.070 28.505,72.060 28.405,71.990 28.505,74.940 28.405,74.870 28.505,77.820 28.405,77.750 28.505,80.700 28.405,80.630 28.505,83.580 28.405,83.510 28.505,86.460 28.405,86.390 28.505,89.340 28.405,89.270 28.505,92.220 28.405,92.150 28.505,95.100 28.405,95.030 28.505,97.980 28.405,97.910
|
||||
00063 28.505,1.590 28.405,1.520 28.505,4.470 28.405,4.400 28.505,7.350 28.405,7.280 28.505,10.230 28.405,10.160 28.505,13.110 28.405,13.040 28.505,15.990 28.405,15.920 28.505,18.870 28.405,18.800 28.505,21.750 28.405,21.680 28.505,24.630 28.405,24.560 28.505,73.430 28.405,73.500 28.505,76.310 28.405,76.380 28.505,79.190 28.405,79.260 28.505,82.070 28.405,82.140 28.505,84.950 28.405,85.020 28.505,87.830 28.405,87.900 28.505,90.710 28.405,90.780 28.505,93.590 28.405,93.660 28.505,96.470 28.405,96.540 28.505,99.350 28.405,99.420
|
||||
00064 28.675,2.960 28.775,3.030 28.675,5.840 28.775,5.910 28.675,8.720 28.775,8.790 28.675,11.600 28.775,11.670 28.675,14.480 28.775,14.550 28.675,17.360 28.775,17.430 28.675,20.240 28.775,20.310 28.675,23.120 28.775,23.190 28.675,26.000 28.775,26.070 28.675,72.060 28.775,71.990 28.675,74.940 28.775,74.870 28.675,77.820 28.775,77.750 28.675,80.700 28.775,80.630 28.675,83.580 28.775,83.510 28.675,86.460 28.775,86.390 28.675,89.340 28.775,89.270 28.675,92.220 28.775,92.150 28.675,95.100 28.775,95.030 28.675,97.980 28.775,97.910
|
||||
00065 28.675,1.590 28.775,1.520 28.675,4.470 28.775,4.400 28.675,7.350 28.775,7.280 28.675,10.230 28.775,10.160 28.675,13.110 28.775,13.040 28.675,15.990 28.775,15.920 28.675,18.870 28.775,18.800 28.675,21.750 28.775,21.680 28.675,24.630 28.775,24.560 28.675,73.430 28.775,73.500 28.675,76.310 28.775,76.380 28.675,79.190 28.775,79.260 28.675,82.070 28.775,82.140 28.675,84.950 28.775,85.020 28.675,87.830 28.775,87.900 28.675,90.710 28.775,90.780 28.675,93.590 28.775,93.660 28.675,96.470 28.775,96.540 28.675,99.350 28.775,99.420
|
||||
00066 29.045,2.960 28.945,3.030 29.045,5.840 28.945,5.910 29.045,8.720 28.945,8.790 29.045,11.600 28.945,11.670 29.045,14.480 28.945,14.550 29.045,17.360 28.945,17.430 29.045,20.240 28.945,20.310 29.045,23.120 28.945,23.190 29.045,26.000 28.945,26.070 29.045,72.060 28.945,71.990 29.045,74.940 28.945,74.870 29.045,77.820 28.945,77.750 29.045,80.700 28.945,80.630 29.045,83.580 28.945,83.510 29.045,86.460 28.945,86.390 29.045,89.340 28.945,89.270 29.045,92.220 28.945,92.150 29.045,95.100 28.945,95.030 29.045,97.980 28.945,97.910
|
||||
00067 29.045,1.590 28.945,1.520 29.045,4.470 28.945,4.400 29.045,7.350 28.945,7.280 29.045,10.230 28.945,10.160 29.045,13.110 28.945,13.040 29.045,15.990 28.945,15.920 29.045,18.870 28.945,18.800 29.045,21.750 28.945,21.680 29.045,24.630 28.945,24.560 29.045,73.430 28.945,73.500 29.045,76.310 28.945,76.380 29.045,79.190 28.945,79.260 29.045,82.070 28.945,82.140 29.045,84.950 28.945,85.020 29.045,87.830 28.945,87.900 29.045,90.710 28.945,90.780 29.045,93.590 28.945,93.660 29.045,96.470 28.945,96.540 29.045,99.350 28.945,99.420
|
||||
00068 29.215,2.960 29.315,3.030 29.215,5.840 29.315,5.910 29.215,8.720 29.315,8.790 29.215,11.600 29.315,11.670 29.215,14.480 29.315,14.550 29.215,17.360 29.315,17.430 29.215,20.240 29.315,20.310 29.215,23.120 29.315,23.190 29.215,26.000 29.315,26.070 29.215,72.060 29.315,71.990 29.215,74.940 29.315,74.870 29.215,77.820 29.315,77.750 29.215,80.700 29.315,80.630 29.215,83.580 29.315,83.510 29.215,86.460 29.315,86.390 29.215,89.340 29.315,89.270 29.215,92.220 29.315,92.150 29.215,95.100 29.315,95.030 29.215,97.980 29.315,97.910
|
||||
00069 29.215,1.590 29.315,1.520 29.215,4.470 29.315,4.400 29.215,7.350 29.315,7.280 29.215,10.230 29.315,10.160 29.215,13.110 29.315,13.040 29.215,15.990 29.315,15.920 29.215,18.870 29.315,18.800 29.215,21.750 29.315,21.680 29.215,24.630 29.315,24.560 29.215,73.430 29.315,73.500 29.215,76.310 29.315,76.380 29.215,79.190 29.315,79.260 29.215,82.070 29.315,82.140 29.215,84.950 29.315,85.020 29.215,87.830 29.315,87.900 29.215,90.710 29.315,90.780 29.215,93.590 29.315,93.660 29.215,96.470 29.315,96.540 29.215,99.350 29.315,99.420
|
||||
0006A 29.585,2.960 29.485,3.030 29.585,5.840 29.485,5.910 29.585,8.720 29.485,8.790 29.585,11.600 29.485,11.670 29.585,14.480 29.485,14.550 29.585,17.360 29.485,17.430 29.585,20.240 29.485,20.310 29.585,23.120 29.485,23.190 29.585,26.000 29.485,26.070 29.585,72.060 29.485,71.990 29.585,74.940 29.485,74.870 29.585,77.820 29.485,77.750 29.585,80.700 29.485,80.630 29.585,83.580 29.485,83.510 29.585,86.460 29.485,86.390 29.585,89.340 29.485,89.270 29.585,92.220 29.485,92.150 29.585,95.100 29.485,95.030 29.585,97.980 29.485,97.910
|
||||
0006B 29.585,1.590 29.485,1.520 29.585,4.470 29.485,4.400 29.585,7.350 29.485,7.280 29.585,10.230 29.485,10.160 29.585,13.110 29.485,13.040 29.585,15.990 29.485,15.920 29.585,18.870 29.485,18.800 29.585,21.750 29.485,21.680 29.585,24.630 29.485,24.560 29.585,73.430 29.485,73.500 29.585,76.310 29.485,76.380 29.585,79.190 29.485,79.260 29.585,82.070 29.485,82.140 29.585,84.950 29.485,85.020 29.585,87.830 29.485,87.900 29.585,90.710 29.485,90.780 29.585,93.590 29.485,93.660 29.585,96.470 29.485,96.540 29.585,99.350 29.485,99.420
|
||||
0006C 29.755,2.960 29.855,3.030 29.755,5.840 29.855,5.910 29.755,8.720 29.855,8.790 29.755,11.600 29.855,11.670 29.755,14.480 29.855,14.550 29.755,17.360 29.855,17.430 29.755,20.240 29.855,20.310 29.755,23.120 29.855,23.190 29.755,26.000 29.855,26.070 29.755,72.060 29.855,71.990 29.755,74.940 29.855,74.870 29.755,77.820 29.855,77.750 29.755,80.700 29.855,80.630 29.755,83.580 29.855,83.510 29.755,86.460 29.855,86.390 29.755,89.340 29.855,89.270 29.755,92.220 29.855,92.150 29.755,95.100 29.855,95.030 29.755,97.980 29.855,97.910
|
||||
0006D 29.755,1.590 29.855,1.520 29.755,4.470 29.855,4.400 29.755,7.350 29.855,7.280 29.755,10.230 29.855,10.160 29.755,13.110 29.855,13.040 29.755,15.990 29.855,15.920 29.755,18.870 29.855,18.800 29.755,21.750 29.855,21.680 29.755,24.630 29.855,24.560 29.755,73.430 29.855,73.500 29.755,76.310 29.855,76.380 29.755,79.190 29.855,79.260 29.755,82.070 29.855,82.140 29.755,84.950 29.855,85.020 29.755,87.830 29.855,87.900 29.755,90.710 29.855,90.780 29.755,93.590 29.855,93.660 29.755,96.470 29.855,96.540 29.755,99.350 29.855,99.420
|
||||
0006E 30.125,2.960 30.025,3.030 30.125,5.840 30.025,5.910 30.125,8.720 30.025,8.790 30.125,11.600 30.025,11.670 30.125,14.480 30.025,14.550 30.125,17.360 30.025,17.430 30.125,20.240 30.025,20.310 30.125,23.120 30.025,23.190 30.125,26.000 30.025,26.070 30.125,72.060 30.025,71.990 30.125,74.940 30.025,74.870 30.125,77.820 30.025,77.750 30.125,80.700 30.025,80.630 30.125,83.580 30.025,83.510 30.125,86.460 30.025,86.390 30.125,89.340 30.025,89.270 30.125,92.220 30.025,92.150 30.125,95.100 30.025,95.030 30.125,97.980 30.025,97.910
|
||||
0006F 30.125,1.590 30.025,1.520 30.125,4.470 30.025,4.400 30.125,7.350 30.025,7.280 30.125,10.230 30.025,10.160 30.125,13.110 30.025,13.040 30.125,15.990 30.025,15.920 30.125,18.870 30.025,18.800 30.125,21.750 30.025,21.680 30.125,24.630 30.025,24.560 30.125,73.430 30.025,73.500 30.125,76.310 30.025,76.380 30.125,79.190 30.025,79.260 30.125,82.070 30.025,82.140 30.125,84.950 30.025,85.020 30.125,87.830 30.025,87.900 30.125,90.710 30.025,90.780 30.125,93.590 30.025,93.660 30.125,96.470 30.025,96.540 30.125,99.350 30.025,99.420
|
||||
00070 30.295,2.960 30.395,3.030 30.295,5.840 30.395,5.910 30.295,8.720 30.395,8.790 30.295,11.600 30.395,11.670 30.295,14.480 30.395,14.550 30.295,17.360 30.395,17.430 30.295,20.240 30.395,20.310 30.295,23.120 30.395,23.190 30.295,26.000 30.395,26.070 30.295,72.060 30.395,71.990 30.295,74.940 30.395,74.870 30.295,77.820 30.395,77.750 30.295,80.700 30.395,80.630 30.295,83.580 30.395,83.510 30.295,86.460 30.395,86.390 30.295,89.340 30.395,89.270 30.295,92.220 30.395,92.150 30.295,95.100 30.395,95.030 30.295,97.980 30.395,97.910
|
||||
00071 30.295,1.590 30.395,1.520 30.295,4.470 30.395,4.400 30.295,7.350 30.395,7.280 30.295,10.230 30.395,10.160 30.295,13.110 30.395,13.040 30.295,15.990 30.395,15.920 30.295,18.870 30.395,18.800 30.295,21.750 30.395,21.680 30.295,24.630 30.395,24.560 30.295,73.430 30.395,73.500 30.295,76.310 30.395,76.380 30.295,79.190 30.395,79.260 30.295,82.070 30.395,82.140 30.295,84.950 30.395,85.020 30.295,87.830 30.395,87.900 30.295,90.710 30.395,90.780 30.295,93.590 30.395,93.660 30.295,96.470 30.395,96.540 30.295,99.350 30.395,99.420
|
||||
00072 30.665,2.960 30.565,3.030 30.665,5.840 30.565,5.910 30.665,8.720 30.565,8.790 30.665,11.600 30.565,11.670 30.665,14.480 30.565,14.550 30.665,17.360 30.565,17.430 30.665,20.240 30.565,20.310 30.665,23.120 30.565,23.190 30.665,26.000 30.565,26.070 30.665,72.060 30.565,71.990 30.665,74.940 30.565,74.870 30.665,77.820 30.565,77.750 30.665,80.700 30.565,80.630 30.665,83.580 30.565,83.510 30.665,86.460 30.565,86.390 30.665,89.340 30.565,89.270 30.665,92.220 30.565,92.150 30.665,95.100 30.565,95.030 30.665,97.980 30.565,97.910
|
||||
00073 30.665,1.590 30.565,1.520 30.665,4.470 30.565,4.400 30.665,7.350 30.565,7.280 30.665,10.230 30.565,10.160 30.665,13.110 30.565,13.040 30.665,15.990 30.565,15.920 30.665,18.870 30.565,18.800 30.665,21.750 30.565,21.680 30.665,24.630 30.565,24.560 30.665,73.430 30.565,73.500 30.665,76.310 30.565,76.380 30.665,79.190 30.565,79.260 30.665,82.070 30.565,82.140 30.665,84.950 30.565,85.020 30.665,87.830 30.565,87.900 30.665,90.710 30.565,90.780 30.665,93.590 30.565,93.660 30.665,96.470 30.565,96.540 30.665,99.350 30.565,99.420
|
||||
00074 30.835,2.960 30.935,3.030 30.835,5.840 30.935,5.910 30.835,8.720 30.935,8.790 30.835,11.600 30.935,11.670 30.835,14.480 30.935,14.550 30.835,17.360 30.935,17.430 30.835,20.240 30.935,20.310 30.835,23.120 30.935,23.190 30.835,26.000 30.935,26.070 30.835,72.060 30.935,71.990 30.835,74.940 30.935,74.870 30.835,77.820 30.935,77.750 30.835,80.700 30.935,80.630 30.835,83.580 30.935,83.510 30.835,86.460 30.935,86.390 30.835,89.340 30.935,89.270 30.835,92.220 30.935,92.150 30.835,95.100 30.935,95.030 30.835,97.980 30.935,97.910
|
||||
00075 30.835,1.590 30.935,1.520 30.835,4.470 30.935,4.400 30.835,7.350 30.935,7.280 30.835,10.230 30.935,10.160 30.835,13.110 30.935,13.040 30.835,15.990 30.935,15.920 30.835,18.870 30.935,18.800 30.835,21.750 30.935,21.680 30.835,24.630 30.935,24.560 30.835,73.430 30.935,73.500 30.835,76.310 30.935,76.380 30.835,79.190 30.935,79.260 30.835,82.070 30.935,82.140 30.835,84.950 30.935,85.020 30.835,87.830 30.935,87.900 30.835,90.710 30.935,90.780 30.835,93.590 30.935,93.660 30.835,96.470 30.935,96.540 30.835,99.350 30.935,99.420
|
||||
00076 31.205,2.960 31.105,3.030 31.205,5.840 31.105,5.910 31.205,8.720 31.105,8.790 31.205,11.600 31.105,11.670 31.205,14.480 31.105,14.550 31.205,17.360 31.105,17.430 31.205,20.240 31.105,20.310 31.205,23.120 31.105,23.190 31.205,26.000 31.105,26.070 31.205,72.060 31.105,71.990 31.205,74.940 31.105,74.870 31.205,77.820 31.105,77.750 31.205,80.700 31.105,80.630 31.205,83.580 31.105,83.510 31.205,86.460 31.105,86.390 31.205,89.340 31.105,89.270 31.205,92.220 31.105,92.150 31.205,95.100 31.105,95.030 31.205,97.980 31.105,97.910
|
||||
00077 31.205,1.590 31.105,1.520 31.205,4.470 31.105,4.400 31.205,7.350 31.105,7.280 31.205,10.230 31.105,10.160 31.205,13.110 31.105,13.040 31.205,15.990 31.105,15.920 31.205,18.870 31.105,18.800 31.205,21.750 31.105,21.680 31.205,24.630 31.105,24.560 31.205,73.430 31.105,73.500 31.205,76.310 31.105,76.380 31.205,79.190 31.105,79.260 31.205,82.070 31.105,82.140 31.205,84.950 31.105,85.020 31.205,87.830 31.105,87.900 31.205,90.710 31.105,90.780 31.205,93.590 31.105,93.660 31.205,96.470 31.105,96.540 31.205,99.350 31.105,99.420
|
||||
00078 31.375,2.960 31.475,3.030 31.375,5.840 31.475,5.910 31.375,8.720 31.475,8.790 31.375,11.600 31.475,11.670 31.375,14.480 31.475,14.550 31.375,17.360 31.475,17.430 31.375,20.240 31.475,20.310 31.375,23.120 31.475,23.190 31.375,26.000 31.475,26.070 31.375,72.060 31.475,71.990 31.375,74.940 31.475,74.870 31.375,77.820 31.475,77.750 31.375,80.700 31.475,80.630 31.375,83.580 31.475,83.510 31.375,86.460 31.475,86.390 31.375,89.340 31.475,89.270 31.375,92.220 31.475,92.150 31.375,95.100 31.475,95.030 31.375,97.980 31.475,97.910
|
||||
00079 31.375,1.590 31.475,1.520 31.375,4.470 31.475,4.400 31.375,7.350 31.475,7.280 31.375,10.230 31.475,10.160 31.375,13.110 31.475,13.040 31.375,15.990 31.475,15.920 31.375,18.870 31.475,18.800 31.375,21.750 31.475,21.680 31.375,24.630 31.475,24.560 31.375,73.430 31.475,73.500 31.375,76.310 31.475,76.380 31.375,79.190 31.475,79.260 31.375,82.070 31.475,82.140 31.375,84.950 31.475,85.020 31.375,87.830 31.475,87.900 31.375,90.710 31.475,90.780 31.375,93.590 31.475,93.660 31.375,96.470 31.475,96.540 31.375,99.350 31.475,99.420
|
||||
0007A 31.745,2.960 31.645,3.030 31.745,5.840 31.645,5.910 31.745,8.720 31.645,8.790 31.745,11.600 31.645,11.670 31.745,14.480 31.645,14.550 31.745,17.360 31.645,17.430 31.745,20.240 31.645,20.310 31.745,23.120 31.645,23.190 31.745,26.000 31.645,26.070 31.745,72.060 31.645,71.990 31.745,74.940 31.645,74.870 31.745,77.820 31.645,77.750 31.745,80.700 31.645,80.630 31.745,83.580 31.645,83.510 31.745,86.460 31.645,86.390 31.745,89.340 31.645,89.270 31.745,92.220 31.645,92.150 31.745,95.100 31.645,95.030 31.745,97.980 31.645,97.910
|
||||
0007B 31.745,1.590 31.645,1.520 31.745,4.470 31.645,4.400 31.745,7.350 31.645,7.280 31.745,10.230 31.645,10.160 31.745,13.110 31.645,13.040 31.745,15.990 31.645,15.920 31.745,18.870 31.645,18.800 31.745,21.750 31.645,21.680 31.745,24.630 31.645,24.560 31.745,73.430 31.645,73.500 31.745,76.310 31.645,76.380 31.745,79.190 31.645,79.260 31.745,82.070 31.645,82.140 31.745,84.950 31.645,85.020 31.745,87.830 31.645,87.900 31.745,90.710 31.645,90.780 31.745,93.590 31.645,93.660 31.745,96.470 31.645,96.540 31.745,99.350 31.645,99.420
|
||||
0007C 31.915,2.960 32.015,3.030 31.915,5.840 32.015,5.910 31.915,8.720 32.015,8.790 31.915,11.600 32.015,11.670 31.915,14.480 32.015,14.550 31.915,17.360 32.015,17.430 31.915,20.240 32.015,20.310 31.915,23.120 32.015,23.190 31.915,26.000 32.015,26.070 31.915,72.060 32.015,71.990 31.915,74.940 32.015,74.870 31.915,77.820 32.015,77.750 31.915,80.700 32.015,80.630 31.915,83.580 32.015,83.510 31.915,86.460 32.015,86.390 31.915,89.340 32.015,89.270 31.915,92.220 32.015,92.150 31.915,95.100 32.015,95.030 31.915,97.980 32.015,97.910
|
||||
0007D 31.915,1.590 32.015,1.520 31.915,4.470 32.015,4.400 31.915,7.350 32.015,7.280 31.915,10.230 32.015,10.160 31.915,13.110 32.015,13.040 31.915,15.990 32.015,15.920 31.915,18.870 32.015,18.800 31.915,21.750 32.015,21.680 31.915,24.630 32.015,24.560 31.915,73.430 32.015,73.500 31.915,76.310 32.015,76.380 31.915,79.190 32.015,79.260 31.915,82.070 32.015,82.140 31.915,84.950 32.015,85.020 31.915,87.830 32.015,87.900 31.915,90.710 32.015,90.780 31.915,93.590 32.015,93.660 31.915,96.470 32.015,96.540 31.915,99.350 32.015,99.420
|
||||
0007E 32.285,2.960 32.185,3.030 32.285,5.840 32.185,5.910 32.285,8.720 32.185,8.790 32.285,11.600 32.185,11.670 32.285,14.480 32.185,14.550 32.285,17.360 32.185,17.430 32.285,20.240 32.185,20.310 32.285,23.120 32.185,23.190 32.285,26.000 32.185,26.070 32.285,72.060 32.185,71.990 32.285,74.940 32.185,74.870 32.285,77.820 32.185,77.750 32.285,80.700 32.185,80.630 32.285,83.580 32.185,83.510 32.285,86.460 32.185,86.390 32.285,89.340 32.185,89.270 32.285,92.220 32.185,92.150 32.285,95.100 32.185,95.030 32.285,97.980 32.185,97.910
|
||||
0007F 32.285,1.590 32.185,1.520 32.285,4.470 32.185,4.400 32.285,7.350 32.185,7.280 32.285,10.230 32.185,10.160 32.285,13.110 32.185,13.040 32.285,15.990 32.185,15.920 32.285,18.870 32.185,18.800 32.285,21.750 32.185,21.680 32.285,24.630 32.185,24.560 32.285,73.430 32.185,73.500 32.285,76.310 32.185,76.380 32.285,79.190 32.185,79.260 32.285,82.070 32.185,82.140 32.285,84.950 32.185,85.020 32.285,87.830 32.185,87.900 32.285,90.710 32.185,90.780 32.285,93.590 32.185,93.660 32.285,96.470 32.185,96.540 32.285,99.350 32.185,99.420
|
||||
00080 32.455,2.960 32.555,3.030 32.455,5.840 32.555,5.910 32.455,8.720 32.555,8.790 32.455,11.600 32.555,11.670 32.455,14.480 32.555,14.550 32.455,17.360 32.555,17.430 32.455,20.240 32.555,20.310 32.455,23.120 32.555,23.190 32.455,26.000 32.555,26.070 32.455,72.060 32.555,71.990 32.455,74.940 32.555,74.870 32.455,77.820 32.555,77.750 32.455,80.700 32.555,80.630 32.455,83.580 32.555,83.510 32.455,86.460 32.555,86.390 32.455,89.340 32.555,89.270 32.455,92.220 32.555,92.150 32.455,95.100 32.555,95.030 32.455,97.980 32.555,97.910
|
||||
00081 32.455,1.590 32.555,1.520 32.455,4.470 32.555,4.400 32.455,7.350 32.555,7.280 32.455,10.230 32.555,10.160 32.455,13.110 32.555,13.040 32.455,15.990 32.555,15.920 32.455,18.870 32.555,18.800 32.455,21.750 32.555,21.680 32.455,24.630 32.555,24.560 32.455,73.430 32.555,73.500 32.455,76.310 32.555,76.380 32.455,79.190 32.555,79.260 32.455,82.070 32.555,82.140 32.455,84.950 32.555,85.020 32.455,87.830 32.555,87.900 32.455,90.710 32.555,90.780 32.455,93.590 32.555,93.660 32.455,96.470 32.555,96.540 32.455,99.350 32.555,99.420
|
||||
00082 32.825,2.960 32.725,3.030 32.825,5.840 32.725,5.910 32.825,8.720 32.725,8.790 32.825,11.600 32.725,11.670 32.825,14.480 32.725,14.550 32.825,17.360 32.725,17.430 32.825,20.240 32.725,20.310 32.825,23.120 32.725,23.190 32.825,26.000 32.725,26.070 32.825,72.060 32.725,71.990 32.825,74.940 32.725,74.870 32.825,77.820 32.725,77.750 32.825,80.700 32.725,80.630 32.825,83.580 32.725,83.510 32.825,86.460 32.725,86.390 32.825,89.340 32.725,89.270 32.825,92.220 32.725,92.150 32.825,95.100 32.725,95.030 32.825,97.980 32.725,97.910
|
||||
00083 32.825,1.590 32.725,1.520 32.825,4.470 32.725,4.400 32.825,7.350 32.725,7.280 32.825,10.230 32.725,10.160 32.825,13.110 32.725,13.040 32.825,15.990 32.725,15.920 32.825,18.870 32.725,18.800 32.825,21.750 32.725,21.680 32.825,24.630 32.725,24.560 32.825,73.430 32.725,73.500 32.825,76.310 32.725,76.380 32.825,79.190 32.725,79.260 32.825,82.070 32.725,82.140 32.825,84.950 32.725,85.020 32.825,87.830 32.725,87.900 32.825,90.710 32.725,90.780 32.825,93.590 32.725,93.660 32.825,96.470 32.725,96.540 32.825,99.350 32.725,99.420
|
||||
00084 32.995,2.960 33.095,3.030 32.995,5.840 33.095,5.910 32.995,8.720 33.095,8.790 32.995,11.600 33.095,11.670 32.995,14.480 33.095,14.550 32.995,17.360 33.095,17.430 32.995,20.240 33.095,20.310 32.995,23.120 33.095,23.190 32.995,26.000 33.095,26.070 32.995,72.060 33.095,71.990 32.995,74.940 33.095,74.870 32.995,77.820 33.095,77.750 32.995,80.700 33.095,80.630 32.995,83.580 33.095,83.510 32.995,86.460 33.095,86.390 32.995,89.340 33.095,89.270 32.995,92.220 33.095,92.150 32.995,95.100 33.095,95.030 32.995,97.980 33.095,97.910
|
||||
00085 32.995,1.590 33.095,1.520 32.995,4.470 33.095,4.400 32.995,7.350 33.095,7.280 32.995,10.230 33.095,10.160 32.995,13.110 33.095,13.040 32.995,15.990 33.095,15.920 32.995,18.870 33.095,18.800 32.995,21.750 33.095,21.680 32.995,24.630 33.095,24.560 32.995,73.430 33.095,73.500 32.995,76.310 33.095,76.380 32.995,79.190 33.095,79.260 32.995,82.070 33.095,82.140 32.995,84.950 33.095,85.020 32.995,87.830 33.095,87.900 32.995,90.710 33.095,90.780 32.995,93.590 33.095,93.660 32.995,96.470 33.095,96.540 32.995,99.350 33.095,99.420
|
||||
00086 33.365,2.960 33.265,3.030 33.365,5.840 33.265,5.910 33.365,8.720 33.265,8.790 33.365,11.600 33.265,11.670 33.365,14.480 33.265,14.550 33.365,17.360 33.265,17.430 33.365,20.240 33.265,20.310 33.365,23.120 33.265,23.190 33.365,26.000 33.265,26.070 33.365,72.060 33.265,71.990 33.365,74.940 33.265,74.870 33.365,77.820 33.265,77.750 33.365,80.700 33.265,80.630 33.365,83.580 33.265,83.510 33.365,86.460 33.265,86.390 33.365,89.340 33.265,89.270 33.365,92.220 33.265,92.150 33.365,95.100 33.265,95.030 33.365,97.980 33.265,97.910
|
||||
00087 33.365,1.590 33.265,1.520 33.365,4.470 33.265,4.400 33.365,7.350 33.265,7.280 33.365,10.230 33.265,10.160 33.365,13.110 33.265,13.040 33.365,15.990 33.265,15.920 33.365,18.870 33.265,18.800 33.365,21.750 33.265,21.680 33.365,24.630 33.265,24.560 33.365,73.430 33.265,73.500 33.365,76.310 33.265,76.380 33.365,79.190 33.265,79.260 33.365,82.070 33.265,82.140 33.365,84.950 33.265,85.020 33.365,87.830 33.265,87.900 33.365,90.710 33.265,90.780 33.365,93.590 33.265,93.660 33.365,96.470 33.265,96.540 33.365,99.350 33.265,99.420
|
||||
00088 33.535,2.960 33.635,3.030 33.535,5.840 33.635,5.910 33.535,8.720 33.635,8.790 33.535,11.600 33.635,11.670 33.535,14.480 33.635,14.550 33.535,17.360 33.635,17.430 33.535,20.240 33.635,20.310 33.535,23.120 33.635,23.190 33.535,26.000 33.635,26.070 33.535,72.060 33.635,71.990 33.535,74.940 33.635,74.870 33.535,77.820 33.635,77.750 33.535,80.700 33.635,80.630 33.535,83.580 33.635,83.510 33.535,86.460 33.635,86.390 33.535,89.340 33.635,89.270 33.535,92.220 33.635,92.150 33.535,95.100 33.635,95.030 33.535,97.980 33.635,97.910
|
||||
00089 33.535,1.590 33.635,1.520 33.535,4.470 33.635,4.400 33.535,7.350 33.635,7.280 33.535,10.230 33.635,10.160 33.535,13.110 33.635,13.040 33.535,15.990 33.635,15.920 33.535,18.870 33.635,18.800 33.535,21.750 33.635,21.680 33.535,24.630 33.635,24.560 33.535,73.430 33.635,73.500 33.535,76.310 33.635,76.380 33.535,79.190 33.635,79.260 33.535,82.070 33.635,82.140 33.535,84.950 33.635,85.020 33.535,87.830 33.635,87.900 33.535,90.710 33.635,90.780 33.535,93.590 33.635,93.660 33.535,96.470 33.635,96.540 33.535,99.350 33.635,99.420
|
||||
0008A 33.905,2.960 33.805,3.030 33.905,5.840 33.805,5.910 33.905,8.720 33.805,8.790 33.905,11.600 33.805,11.670 33.905,14.480 33.805,14.550 33.905,17.360 33.805,17.430 33.905,20.240 33.805,20.310 33.905,23.120 33.805,23.190 33.905,26.000 33.805,26.070 33.905,72.060 33.805,71.990 33.905,74.940 33.805,74.870 33.905,77.820 33.805,77.750 33.905,80.700 33.805,80.630 33.905,83.580 33.805,83.510 33.905,86.460 33.805,86.390 33.905,89.340 33.805,89.270 33.905,92.220 33.805,92.150 33.905,95.100 33.805,95.030 33.905,97.980 33.805,97.910
|
||||
0008B 33.905,1.590 33.805,1.520 33.905,4.470 33.805,4.400 33.905,7.350 33.805,7.280 33.905,10.230 33.805,10.160 33.905,13.110 33.805,13.040 33.905,15.990 33.805,15.920 33.905,18.870 33.805,18.800 33.905,21.750 33.805,21.680 33.905,24.630 33.805,24.560 33.905,73.430 33.805,73.500 33.905,76.310 33.805,76.380 33.905,79.190 33.805,79.260 33.905,82.070 33.805,82.140 33.905,84.950 33.805,85.020 33.905,87.830 33.805,87.900 33.905,90.710 33.805,90.780 33.905,93.590 33.805,93.660 33.905,96.470 33.805,96.540 33.905,99.350 33.805,99.420
|
||||
0008C 34.075,2.960 34.175,3.030 34.075,5.840 34.175,5.910 34.075,8.720 34.175,8.790 34.075,11.600 34.175,11.670 34.075,14.480 34.175,14.550 34.075,17.360 34.175,17.430 34.075,20.240 34.175,20.310 34.075,23.120 34.175,23.190 34.075,26.000 34.175,26.070 34.075,72.060 34.175,71.990 34.075,74.940 34.175,74.870 34.075,77.820 34.175,77.750 34.075,80.700 34.175,80.630 34.075,83.580 34.175,83.510 34.075,86.460 34.175,86.390 34.075,89.340 34.175,89.270 34.075,92.220 34.175,92.150 34.075,95.100 34.175,95.030 34.075,97.980 34.175,97.910
|
||||
0008D 34.075,1.590 34.175,1.520 34.075,4.470 34.175,4.400 34.075,7.350 34.175,7.280 34.075,10.230 34.175,10.160 34.075,13.110 34.175,13.040 34.075,15.990 34.175,15.920 34.075,18.870 34.175,18.800 34.075,21.750 34.175,21.680 34.075,24.630 34.175,24.560 34.075,73.430 34.175,73.500 34.075,76.310 34.175,76.380 34.075,79.190 34.175,79.260 34.075,82.070 34.175,82.140 34.075,84.950 34.175,85.020 34.075,87.830 34.175,87.900 34.075,90.710 34.175,90.780 34.075,93.590 34.175,93.660 34.075,96.470 34.175,96.540 34.075,99.350 34.175,99.420
|
||||
0008E 34.445,2.960 34.345,3.030 34.445,5.840 34.345,5.910 34.445,8.720 34.345,8.790 34.445,11.600 34.345,11.670 34.445,14.480 34.345,14.550 34.445,17.360 34.345,17.430 34.445,20.240 34.345,20.310 34.445,23.120 34.345,23.190 34.445,26.000 34.345,26.070 34.445,72.060 34.345,71.990 34.445,74.940 34.345,74.870 34.445,77.820 34.345,77.750 34.445,80.700 34.345,80.630 34.445,83.580 34.345,83.510 34.445,86.460 34.345,86.390 34.445,89.340 34.345,89.270 34.445,92.220 34.345,92.150 34.445,95.100 34.345,95.030 34.445,97.980 34.345,97.910
|
||||
0008F 34.445,1.590 34.345,1.520 34.445,4.470 34.345,4.400 34.445,7.350 34.345,7.280 34.445,10.230 34.345,10.160 34.445,13.110 34.345,13.040 34.445,15.990 34.345,15.920 34.445,18.870 34.345,18.800 34.445,21.750 34.345,21.680 34.445,24.630 34.345,24.560 34.445,73.430 34.345,73.500 34.445,76.310 34.345,76.380 34.445,79.190 34.345,79.260 34.445,82.070 34.345,82.140 34.445,84.950 34.345,85.020 34.445,87.830 34.345,87.900 34.445,90.710 34.345,90.780 34.445,93.590 34.345,93.660 34.445,96.470 34.345,96.540 34.445,99.350 34.345,99.420
|
||||
00090 34.615,2.960 34.715,3.030 34.615,5.840 34.715,5.910 34.615,8.720 34.715,8.790 34.615,11.600 34.715,11.670 34.615,14.480 34.715,14.550 34.615,17.360 34.715,17.430 34.615,20.240 34.715,20.310 34.615,23.120 34.715,23.190 34.615,26.000 34.715,26.070 34.615,72.060 34.715,71.990 34.615,74.940 34.715,74.870 34.615,77.820 34.715,77.750 34.615,80.700 34.715,80.630 34.615,83.580 34.715,83.510 34.615,86.460 34.715,86.390 34.615,89.340 34.715,89.270 34.615,92.220 34.715,92.150 34.615,95.100 34.715,95.030 34.615,97.980 34.715,97.910
|
||||
00091 34.615,1.590 34.715,1.520 34.615,4.470 34.715,4.400 34.615,7.350 34.715,7.280 34.615,10.230 34.715,10.160 34.615,13.110 34.715,13.040 34.615,15.990 34.715,15.920 34.615,18.870 34.715,18.800 34.615,21.750 34.715,21.680 34.615,24.630 34.715,24.560 34.615,73.430 34.715,73.500 34.615,76.310 34.715,76.380 34.615,79.190 34.715,79.260 34.615,82.070 34.715,82.140 34.615,84.950 34.715,85.020 34.615,87.830 34.715,87.900 34.615,90.710 34.715,90.780 34.615,93.590 34.715,93.660 34.615,96.470 34.715,96.540 34.615,99.350 34.715,99.420
|
||||
00092 34.985,2.960 34.885,3.030 34.985,5.840 34.885,5.910 34.985,8.720 34.885,8.790 34.985,11.600 34.885,11.670 34.985,14.480 34.885,14.550 34.985,17.360 34.885,17.430 34.985,20.240 34.885,20.310 34.985,23.120 34.885,23.190 34.985,26.000 34.885,26.070 34.985,72.060 34.885,71.990 34.985,74.940 34.885,74.870 34.985,77.820 34.885,77.750 34.985,80.700 34.885,80.630 34.985,83.580 34.885,83.510 34.985,86.460 34.885,86.390 34.985,89.340 34.885,89.270 34.985,92.220 34.885,92.150 34.985,95.100 34.885,95.030 34.985,97.980 34.885,97.910
|
||||
00093 34.985,1.590 34.885,1.520 34.985,4.470 34.885,4.400 34.985,7.350 34.885,7.280 34.985,10.230 34.885,10.160 34.985,13.110 34.885,13.040 34.985,15.990 34.885,15.920 34.985,18.870 34.885,18.800 34.985,21.750 34.885,21.680 34.985,24.630 34.885,24.560 34.985,73.430 34.885,73.500 34.985,76.310 34.885,76.380 34.985,79.190 34.885,79.260 34.985,82.070 34.885,82.140 34.985,84.950 34.885,85.020 34.985,87.830 34.885,87.900 34.985,90.710 34.885,90.780 34.985,93.590 34.885,93.660 34.985,96.470 34.885,96.540 34.985,99.350 34.885,99.420
|
||||
00094 35.155,2.960 35.255,3.030 35.155,5.840 35.255,5.910 35.155,8.720 35.255,8.790 35.155,11.600 35.255,11.670 35.155,14.480 35.255,14.550 35.155,17.360 35.255,17.430 35.155,20.240 35.255,20.310 35.155,23.120 35.255,23.190 35.155,26.000 35.255,26.070 35.155,72.060 35.255,71.990 35.155,74.940 35.255,74.870 35.155,77.820 35.255,77.750 35.155,80.700 35.255,80.630 35.155,83.580 35.255,83.510 35.155,86.460 35.255,86.390 35.155,89.340 35.255,89.270 35.155,92.220 35.255,92.150 35.155,95.100 35.255,95.030 35.155,97.980 35.255,97.910
|
||||
00095 35.155,1.590 35.255,1.520 35.155,4.470 35.255,4.400 35.155,7.350 35.255,7.280 35.155,10.230 35.255,10.160 35.155,13.110 35.255,13.040 35.155,15.990 35.255,15.920 35.155,18.870 35.255,18.800 35.155,21.750 35.255,21.680 35.155,24.630 35.255,24.560 35.155,73.430 35.255,73.500 35.155,76.310 35.255,76.380 35.155,79.190 35.255,79.260 35.155,82.070 35.255,82.140 35.155,84.950 35.255,85.020 35.155,87.830 35.255,87.900 35.155,90.710 35.255,90.780 35.155,93.590 35.255,93.660 35.155,96.470 35.255,96.540 35.155,99.350 35.255,99.420
|
||||
00096 35.525,2.960 35.425,3.030 35.525,5.840 35.425,5.910 35.525,8.720 35.425,8.790 35.525,11.600 35.425,11.670 35.525,14.480 35.425,14.550 35.525,17.360 35.425,17.430 35.525,20.240 35.425,20.310 35.525,23.120 35.425,23.190 35.525,26.000 35.425,26.070 35.525,72.060 35.425,71.990 35.525,74.940 35.425,74.870 35.525,77.820 35.425,77.750 35.525,80.700 35.425,80.630 35.525,83.580 35.425,83.510 35.525,86.460 35.425,86.390 35.525,89.340 35.425,89.270 35.525,92.220 35.425,92.150 35.525,95.100 35.425,95.030 35.525,97.980 35.425,97.910
|
||||
00097 35.525,1.590 35.425,1.520 35.525,4.470 35.425,4.400 35.525,7.350 35.425,7.280 35.525,10.230 35.425,10.160 35.525,13.110 35.425,13.040 35.525,15.990 35.425,15.920 35.525,18.870 35.425,18.800 35.525,21.750 35.425,21.680 35.525,24.630 35.425,24.560 35.525,73.430 35.425,73.500 35.525,76.310 35.425,76.380 35.525,79.190 35.425,79.260 35.525,82.070 35.425,82.140 35.525,84.950 35.425,85.020 35.525,87.830 35.425,87.900 35.525,90.710 35.425,90.780 35.525,93.590 35.425,93.660 35.525,96.470 35.425,96.540 35.525,99.350 35.425,99.420
|
||||
00098 35.695,2.960 35.795,3.030 35.695,5.840 35.795,5.910 35.695,8.720 35.795,8.790 35.695,11.600 35.795,11.670 35.695,14.480 35.795,14.550 35.695,17.360 35.795,17.430 35.695,20.240 35.795,20.310 35.695,23.120 35.795,23.190 35.695,26.000 35.795,26.070 35.695,72.060 35.795,71.990 35.695,74.940 35.795,74.870 35.695,77.820 35.795,77.750 35.695,80.700 35.795,80.630 35.695,83.580 35.795,83.510 35.695,86.460 35.795,86.390 35.695,89.340 35.795,89.270 35.695,92.220 35.795,92.150 35.695,95.100 35.795,95.030 35.695,97.980 35.795,97.910
|
||||
00099 35.695,1.590 35.795,1.520 35.695,4.470 35.795,4.400 35.695,7.350 35.795,7.280 35.695,10.230 35.795,10.160 35.695,13.110 35.795,13.040 35.695,15.990 35.795,15.920 35.695,18.870 35.795,18.800 35.695,21.750 35.795,21.680 35.695,24.630 35.795,24.560 35.695,73.430 35.795,73.500 35.695,76.310 35.795,76.380 35.695,79.190 35.795,79.260 35.695,82.070 35.795,82.140 35.695,84.950 35.795,85.020 35.695,87.830 35.795,87.900 35.695,90.710 35.795,90.780 35.695,93.590 35.795,93.660 35.695,96.470 35.795,96.540 35.695,99.350 35.795,99.420
|
||||
0009A 36.065,2.960 35.965,3.030 36.065,5.840 35.965,5.910 36.065,8.720 35.965,8.790 36.065,11.600 35.965,11.670 36.065,14.480 35.965,14.550 36.065,17.360 35.965,17.430 36.065,20.240 35.965,20.310 36.065,23.120 35.965,23.190 36.065,26.000 35.965,26.070 36.065,72.060 35.965,71.990 36.065,74.940 35.965,74.870 36.065,77.820 35.965,77.750 36.065,80.700 35.965,80.630 36.065,83.580 35.965,83.510 36.065,86.460 35.965,86.390 36.065,89.340 35.965,89.270 36.065,92.220 35.965,92.150 36.065,95.100 35.965,95.030 36.065,97.980 35.965,97.910
|
||||
0009B 36.065,1.590 35.965,1.520 36.065,4.470 35.965,4.400 36.065,7.350 35.965,7.280 36.065,10.230 35.965,10.160 36.065,13.110 35.965,13.040 36.065,15.990 35.965,15.920 36.065,18.870 35.965,18.800 36.065,21.750 35.965,21.680 36.065,24.630 35.965,24.560 36.065,73.430 35.965,73.500 36.065,76.310 35.965,76.380 36.065,79.190 35.965,79.260 36.065,82.070 35.965,82.140 36.065,84.950 35.965,85.020 36.065,87.830 35.965,87.900 36.065,90.710 35.965,90.780 36.065,93.590 35.965,93.660 36.065,96.470 35.965,96.540 36.065,99.350 35.965,99.420
|
||||
0009C 36.235,2.960 36.335,3.030 36.235,5.840 36.335,5.910 36.235,8.720 36.335,8.790 36.235,11.600 36.335,11.670 36.235,14.480 36.335,14.550 36.235,17.360 36.335,17.430 36.235,20.240 36.335,20.310 36.235,23.120 36.335,23.190 36.235,26.000 36.335,26.070 36.235,72.060 36.335,71.990 36.235,74.940 36.335,74.870 36.235,77.820 36.335,77.750 36.235,80.700 36.335,80.630 36.235,83.580 36.335,83.510 36.235,86.460 36.335,86.390 36.235,89.340 36.335,89.270 36.235,92.220 36.335,92.150 36.235,95.100 36.335,95.030 36.235,97.980 36.335,97.910
|
||||
0009D 36.235,1.590 36.335,1.520 36.235,4.470 36.335,4.400 36.235,7.350 36.335,7.280 36.235,10.230 36.335,10.160 36.235,13.110 36.335,13.040 36.235,15.990 36.335,15.920 36.235,18.870 36.335,18.800 36.235,21.750 36.335,21.680 36.235,24.630 36.335,24.560 36.235,73.430 36.335,73.500 36.235,76.310 36.335,76.380 36.235,79.190 36.335,79.260 36.235,82.070 36.335,82.140 36.235,84.950 36.335,85.020 36.235,87.830 36.335,87.900 36.235,90.710 36.335,90.780 36.235,93.590 36.335,93.660 36.235,96.470 36.335,96.540 36.235,99.350 36.335,99.420
|
||||
0009E 36.605,2.960 36.505,3.030 36.605,5.840 36.505,5.910 36.605,8.720 36.505,8.790 36.605,11.600 36.505,11.670 36.605,14.480 36.505,14.550 36.605,17.360 36.505,17.430 36.605,20.240 36.505,20.310 36.605,23.120 36.505,23.190 36.605,26.000 36.505,26.070 36.605,72.060 36.505,71.990 36.605,74.940 36.505,74.870 36.605,77.820 36.505,77.750 36.605,80.700 36.505,80.630 36.605,83.580 36.505,83.510 36.605,86.460 36.505,86.390 36.605,89.340 36.505,89.270 36.605,92.220 36.505,92.150 36.605,95.100 36.505,95.030 36.605,97.980 36.505,97.910
|
||||
0009F 36.605,1.590 36.505,1.520 36.605,4.470 36.505,4.400 36.605,7.350 36.505,7.280 36.605,10.230 36.505,10.160 36.605,13.110 36.505,13.040 36.605,15.990 36.505,15.920 36.605,18.870 36.505,18.800 36.605,21.750 36.505,21.680 36.605,24.630 36.505,24.560 36.605,73.430 36.505,73.500 36.605,76.310 36.505,76.380 36.605,79.190 36.505,79.260 36.605,82.070 36.505,82.140 36.605,84.950 36.505,85.020 36.605,87.830 36.505,87.900 36.605,90.710 36.505,90.780 36.605,93.590 36.505,93.660 36.605,96.470 36.505,96.540 36.605,99.350 36.505,99.420
|
||||
000A0 36.775,2.960 36.875,3.030 36.775,5.840 36.875,5.910 36.775,8.720 36.875,8.790 36.775,11.600 36.875,11.670 36.775,14.480 36.875,14.550 36.775,17.360 36.875,17.430 36.775,20.240 36.875,20.310 36.775,23.120 36.875,23.190 36.775,26.000 36.875,26.070 36.775,72.060 36.875,71.990 36.775,74.940 36.875,74.870 36.775,77.820 36.875,77.750 36.775,80.700 36.875,80.630 36.775,83.580 36.875,83.510 36.775,86.460 36.875,86.390 36.775,89.340 36.875,89.270 36.775,92.220 36.875,92.150 36.775,95.100 36.875,95.030 36.775,97.980 36.875,97.910
|
||||
000A1 36.775,1.590 36.875,1.520 36.775,4.470 36.875,4.400 36.775,7.350 36.875,7.280 36.775,10.230 36.875,10.160 36.775,13.110 36.875,13.040 36.775,15.990 36.875,15.920 36.775,18.870 36.875,18.800 36.775,21.750 36.875,21.680 36.775,24.630 36.875,24.560 36.775,73.430 36.875,73.500 36.775,76.310 36.875,76.380 36.775,79.190 36.875,79.260 36.775,82.070 36.875,82.140 36.775,84.950 36.875,85.020 36.775,87.830 36.875,87.900 36.775,90.710 36.875,90.780 36.775,93.590 36.875,93.660 36.775,96.470 36.875,96.540 36.775,99.350 36.875,99.420
|
||||
000A2 37.145,2.960 37.045,3.030 37.145,5.840 37.045,5.910 37.145,8.720 37.045,8.790 37.145,11.600 37.045,11.670 37.145,14.480 37.045,14.550 37.145,17.360 37.045,17.430 37.145,20.240 37.045,20.310 37.145,23.120 37.045,23.190 37.145,26.000 37.045,26.070 37.145,72.060 37.045,71.990 37.145,74.940 37.045,74.870 37.145,77.820 37.045,77.750 37.145,80.700 37.045,80.630 37.145,83.580 37.045,83.510 37.145,86.460 37.045,86.390 37.145,89.340 37.045,89.270 37.145,92.220 37.045,92.150 37.145,95.100 37.045,95.030 37.145,97.980 37.045,97.910
|
||||
000A3 37.145,1.590 37.045,1.520 37.145,4.470 37.045,4.400 37.145,7.350 37.045,7.280 37.145,10.230 37.045,10.160 37.145,13.110 37.045,13.040 37.145,15.990 37.045,15.920 37.145,18.870 37.045,18.800 37.145,21.750 37.045,21.680 37.145,24.630 37.045,24.560 37.145,73.430 37.045,73.500 37.145,76.310 37.045,76.380 37.145,79.190 37.045,79.260 37.145,82.070 37.045,82.140 37.145,84.950 37.045,85.020 37.145,87.830 37.045,87.900 37.145,90.710 37.045,90.780 37.145,93.590 37.045,93.660 37.145,96.470 37.045,96.540 37.145,99.350 37.045,99.420
|
||||
000A4 37.315,2.960 37.415,3.030 37.315,5.840 37.415,5.910 37.315,8.720 37.415,8.790 37.315,11.600 37.415,11.670 37.315,14.480 37.415,14.550 37.315,17.360 37.415,17.430 37.315,20.240 37.415,20.310 37.315,23.120 37.415,23.190 37.315,26.000 37.415,26.070 37.315,72.060 37.415,71.990 37.315,74.940 37.415,74.870 37.315,77.820 37.415,77.750 37.315,80.700 37.415,80.630 37.315,83.580 37.415,83.510 37.315,86.460 37.415,86.390 37.315,89.340 37.415,89.270 37.315,92.220 37.415,92.150 37.315,95.100 37.415,95.030 37.315,97.980 37.415,97.910
|
||||
000A5 37.315,1.590 37.415,1.520 37.315,4.470 37.415,4.400 37.315,7.350 37.415,7.280 37.315,10.230 37.415,10.160 37.315,13.110 37.415,13.040 37.315,15.990 37.415,15.920 37.315,18.870 37.415,18.800 37.315,21.750 37.415,21.680 37.315,24.630 37.415,24.560 37.315,73.430 37.415,73.500 37.315,76.310 37.415,76.380 37.315,79.190 37.415,79.260 37.315,82.070 37.415,82.140 37.315,84.950 37.415,85.020 37.315,87.830 37.415,87.900 37.315,90.710 37.415,90.780 37.315,93.590 37.415,93.660 37.315,96.470 37.415,96.540 37.315,99.350 37.415,99.420
|
||||
000A6 37.685,2.960 37.585,3.030 37.685,5.840 37.585,5.910 37.685,8.720 37.585,8.790 37.685,11.600 37.585,11.670 37.685,14.480 37.585,14.550 37.685,17.360 37.585,17.430 37.685,20.240 37.585,20.310 37.685,23.120 37.585,23.190 37.685,26.000 37.585,26.070 37.685,72.060 37.585,71.990 37.685,74.940 37.585,74.870 37.685,77.820 37.585,77.750 37.685,80.700 37.585,80.630 37.685,83.580 37.585,83.510 37.685,86.460 37.585,86.390 37.685,89.340 37.585,89.270 37.685,92.220 37.585,92.150 37.685,95.100 37.585,95.030 37.685,97.980 37.585,97.910
|
||||
000A7 37.685,1.590 37.585,1.520 37.685,4.470 37.585,4.400 37.685,7.350 37.585,7.280 37.685,10.230 37.585,10.160 37.685,13.110 37.585,13.040 37.685,15.990 37.585,15.920 37.685,18.870 37.585,18.800 37.685,21.750 37.585,21.680 37.685,24.630 37.585,24.560 37.685,73.430 37.585,73.500 37.685,76.310 37.585,76.380 37.685,79.190 37.585,79.260 37.685,82.070 37.585,82.140 37.685,84.950 37.585,85.020 37.685,87.830 37.585,87.900 37.685,90.710 37.585,90.780 37.685,93.590 37.585,93.660 37.685,96.470 37.585,96.540 37.685,99.350 37.585,99.420
|
||||
000A8 37.855,2.960 37.955,3.030 37.855,5.840 37.955,5.910 37.855,8.720 37.955,8.790 37.855,11.600 37.955,11.670 37.855,14.480 37.955,14.550 37.855,17.360 37.955,17.430 37.855,20.240 37.955,20.310 37.855,23.120 37.955,23.190 37.855,26.000 37.955,26.070 37.855,72.060 37.955,71.990 37.855,74.940 37.955,74.870 37.855,77.820 37.955,77.750 37.855,80.700 37.955,80.630 37.855,83.580 37.955,83.510 37.855,86.460 37.955,86.390 37.855,89.340 37.955,89.270 37.855,92.220 37.955,92.150 37.855,95.100 37.955,95.030 37.855,97.980 37.955,97.910
|
||||
000A9 37.855,1.590 37.955,1.520 37.855,4.470 37.955,4.400 37.855,7.350 37.955,7.280 37.855,10.230 37.955,10.160 37.855,13.110 37.955,13.040 37.855,15.990 37.955,15.920 37.855,18.870 37.955,18.800 37.855,21.750 37.955,21.680 37.855,24.630 37.955,24.560 37.855,73.430 37.955,73.500 37.855,76.310 37.955,76.380 37.855,79.190 37.955,79.260 37.855,82.070 37.955,82.140 37.855,84.950 37.955,85.020 37.855,87.830 37.955,87.900 37.855,90.710 37.955,90.780 37.855,93.590 37.955,93.660 37.855,96.470 37.955,96.540 37.855,99.350 37.955,99.420
|
||||
000AA 38.225,2.960 38.125,3.030 38.225,5.840 38.125,5.910 38.225,8.720 38.125,8.790 38.225,11.600 38.125,11.670 38.225,14.480 38.125,14.550 38.225,17.360 38.125,17.430 38.225,20.240 38.125,20.310 38.225,23.120 38.125,23.190 38.225,26.000 38.125,26.070 38.225,72.060 38.125,71.990 38.225,74.940 38.125,74.870 38.225,77.820 38.125,77.750 38.225,80.700 38.125,80.630 38.225,83.580 38.125,83.510 38.225,86.460 38.125,86.390 38.225,89.340 38.125,89.270 38.225,92.220 38.125,92.150 38.225,95.100 38.125,95.030 38.225,97.980 38.125,97.910
|
||||
000AB 38.225,1.590 38.125,1.520 38.225,4.470 38.125,4.400 38.225,7.350 38.125,7.280 38.225,10.230 38.125,10.160 38.225,13.110 38.125,13.040 38.225,15.990 38.125,15.920 38.225,18.870 38.125,18.800 38.225,21.750 38.125,21.680 38.225,24.630 38.125,24.560 38.225,73.430 38.125,73.500 38.225,76.310 38.125,76.380 38.225,79.190 38.125,79.260 38.225,82.070 38.125,82.140 38.225,84.950 38.125,85.020 38.225,87.830 38.125,87.900 38.225,90.710 38.125,90.780 38.225,93.590 38.125,93.660 38.225,96.470 38.125,96.540 38.225,99.350 38.125,99.420
|
||||
000AC 38.395,2.960 38.495,3.030 38.395,5.840 38.495,5.910 38.395,8.720 38.495,8.790 38.395,11.600 38.495,11.670 38.395,14.480 38.495,14.550 38.395,17.360 38.495,17.430 38.395,20.240 38.495,20.310 38.395,23.120 38.495,23.190 38.395,26.000 38.495,26.070 38.395,72.060 38.495,71.990 38.395,74.940 38.495,74.870 38.395,77.820 38.495,77.750 38.395,80.700 38.495,80.630 38.395,83.580 38.495,83.510 38.395,86.460 38.495,86.390 38.395,89.340 38.495,89.270 38.395,92.220 38.495,92.150 38.395,95.100 38.495,95.030 38.395,97.980 38.495,97.910
|
||||
000AD 38.395,1.590 38.495,1.520 38.395,4.470 38.495,4.400 38.395,7.350 38.495,7.280 38.395,10.230 38.495,10.160 38.395,13.110 38.495,13.040 38.395,15.990 38.495,15.920 38.395,18.870 38.495,18.800 38.395,21.750 38.495,21.680 38.395,24.630 38.495,24.560 38.395,73.430 38.495,73.500 38.395,76.310 38.495,76.380 38.395,79.190 38.495,79.260 38.395,82.070 38.495,82.140 38.395,84.950 38.495,85.020 38.395,87.830 38.495,87.900 38.395,90.710 38.495,90.780 38.395,93.590 38.495,93.660 38.395,96.470 38.495,96.540 38.395,99.350 38.495,99.420
|
||||
000AE 38.765,2.960 38.665,3.030 38.765,5.840 38.665,5.910 38.765,8.720 38.665,8.790 38.765,11.600 38.665,11.670 38.765,14.480 38.665,14.550 38.765,17.360 38.665,17.430 38.765,20.240 38.665,20.310 38.765,23.120 38.665,23.190 38.765,26.000 38.665,26.070 38.765,72.060 38.665,71.990 38.765,74.940 38.665,74.870 38.765,77.820 38.665,77.750 38.765,80.700 38.665,80.630 38.765,83.580 38.665,83.510 38.765,86.460 38.665,86.390 38.765,89.340 38.665,89.270 38.765,92.220 38.665,92.150 38.765,95.100 38.665,95.030 38.765,97.980 38.665,97.910
|
||||
000AF 38.765,1.590 38.665,1.520 38.765,4.470 38.665,4.400 38.765,7.350 38.665,7.280 38.765,10.230 38.665,10.160 38.765,13.110 38.665,13.040 38.765,15.990 38.665,15.920 38.765,18.870 38.665,18.800 38.765,21.750 38.665,21.680 38.765,24.630 38.665,24.560 38.765,73.430 38.665,73.500 38.765,76.310 38.665,76.380 38.765,79.190 38.665,79.260 38.765,82.070 38.665,82.140 38.765,84.950 38.665,85.020 38.765,87.830 38.665,87.900 38.765,90.710 38.665,90.780 38.765,93.590 38.665,93.660 38.765,96.470 38.665,96.540 38.765,99.350 38.665,99.420
|
||||
000B0 38.935,2.960 39.035,3.030 38.935,5.840 39.035,5.910 38.935,8.720 39.035,8.790 38.935,11.600 39.035,11.670 38.935,14.480 39.035,14.550 38.935,17.360 39.035,17.430 38.935,20.240 39.035,20.310 38.935,23.120 39.035,23.190 38.935,26.000 39.035,26.070 38.935,72.060 39.035,71.990 38.935,74.940 39.035,74.870 38.935,77.820 39.035,77.750 38.935,80.700 39.035,80.630 38.935,83.580 39.035,83.510 38.935,86.460 39.035,86.390 38.935,89.340 39.035,89.270 38.935,92.220 39.035,92.150 38.935,95.100 39.035,95.030 38.935,97.980 39.035,97.910
|
||||
000B1 38.935,1.590 39.035,1.520 38.935,4.470 39.035,4.400 38.935,7.350 39.035,7.280 38.935,10.230 39.035,10.160 38.935,13.110 39.035,13.040 38.935,15.990 39.035,15.920 38.935,18.870 39.035,18.800 38.935,21.750 39.035,21.680 38.935,24.630 39.035,24.560 38.935,73.430 39.035,73.500 38.935,76.310 39.035,76.380 38.935,79.190 39.035,79.260 38.935,82.070 39.035,82.140 38.935,84.950 39.035,85.020 38.935,87.830 39.035,87.900 38.935,90.710 39.035,90.780 38.935,93.590 39.035,93.660 38.935,96.470 39.035,96.540 38.935,99.350 39.035,99.420
|
||||
000B2 39.305,2.960 39.205,3.030 39.305,5.840 39.205,5.910 39.305,8.720 39.205,8.790 39.305,11.600 39.205,11.670 39.305,14.480 39.205,14.550 39.305,17.360 39.205,17.430 39.305,20.240 39.205,20.310 39.305,23.120 39.205,23.190 39.305,26.000 39.205,26.070 39.305,72.060 39.205,71.990 39.305,74.940 39.205,74.870 39.305,77.820 39.205,77.750 39.305,80.700 39.205,80.630 39.305,83.580 39.205,83.510 39.305,86.460 39.205,86.390 39.305,89.340 39.205,89.270 39.305,92.220 39.205,92.150 39.305,95.100 39.205,95.030 39.305,97.980 39.205,97.910
|
||||
000B3 39.305,1.590 39.205,1.520 39.305,4.470 39.205,4.400 39.305,7.350 39.205,7.280 39.305,10.230 39.205,10.160 39.305,13.110 39.205,13.040 39.305,15.990 39.205,15.920 39.305,18.870 39.205,18.800 39.305,21.750 39.205,21.680 39.305,24.630 39.205,24.560 39.305,73.430 39.205,73.500 39.305,76.310 39.205,76.380 39.305,79.190 39.205,79.260 39.305,82.070 39.205,82.140 39.305,84.950 39.205,85.020 39.305,87.830 39.205,87.900 39.305,90.710 39.205,90.780 39.305,93.590 39.205,93.660 39.305,96.470 39.205,96.540 39.305,99.350 39.205,99.420
|
||||
000B4 39.475,2.960 39.575,3.030 39.475,5.840 39.575,5.910 39.475,8.720 39.575,8.790 39.475,11.600 39.575,11.670 39.475,14.480 39.575,14.550 39.475,17.360 39.575,17.430 39.475,20.240 39.575,20.310 39.475,23.120 39.575,23.190 39.475,26.000 39.575,26.070 39.475,72.060 39.575,71.990 39.475,74.940 39.575,74.870 39.475,77.820 39.575,77.750 39.475,80.700 39.575,80.630 39.475,83.580 39.575,83.510 39.475,86.460 39.575,86.390 39.475,89.340 39.575,89.270 39.475,92.220 39.575,92.150 39.475,95.100 39.575,95.030 39.475,97.980 39.575,97.910
|
||||
000B5 39.475,1.590 39.575,1.520 39.475,4.470 39.575,4.400 39.475,7.350 39.575,7.280 39.475,10.230 39.575,10.160 39.475,13.110 39.575,13.040 39.475,15.990 39.575,15.920 39.475,18.870 39.575,18.800 39.475,21.750 39.575,21.680 39.475,24.630 39.575,24.560 39.475,73.430 39.575,73.500 39.475,76.310 39.575,76.380 39.475,79.190 39.575,79.260 39.475,82.070 39.575,82.140 39.475,84.950 39.575,85.020 39.475,87.830 39.575,87.900 39.475,90.710 39.575,90.780 39.475,93.590 39.575,93.660 39.475,96.470 39.575,96.540 39.475,99.350 39.575,99.420
|
||||
000B6 39.845,2.960 39.745,3.030 39.845,5.840 39.745,5.910 39.845,8.720 39.745,8.790 39.845,11.600 39.745,11.670 39.845,14.480 39.745,14.550 39.845,17.360 39.745,17.430 39.845,20.240 39.745,20.310 39.845,23.120 39.745,23.190 39.845,26.000 39.745,26.070 39.845,72.060 39.745,71.990 39.845,74.940 39.745,74.870 39.845,77.820 39.745,77.750 39.845,80.700 39.745,80.630 39.845,83.580 39.745,83.510 39.845,86.460 39.745,86.390 39.845,89.340 39.745,89.270 39.845,92.220 39.745,92.150 39.845,95.100 39.745,95.030 39.845,97.980 39.745,97.910
|
||||
000B7 39.845,1.590 39.745,1.520 39.845,4.470 39.745,4.400 39.845,7.350 39.745,7.280 39.845,10.230 39.745,10.160 39.845,13.110 39.745,13.040 39.845,15.990 39.745,15.920 39.845,18.870 39.745,18.800 39.845,21.750 39.745,21.680 39.845,24.630 39.745,24.560 39.845,73.430 39.745,73.500 39.845,76.310 39.745,76.380 39.845,79.190 39.745,79.260 39.845,82.070 39.745,82.140 39.845,84.950 39.745,85.020 39.845,87.830 39.745,87.900 39.845,90.710 39.745,90.780 39.845,93.590 39.745,93.660 39.845,96.470 39.745,96.540 39.845,99.350 39.745,99.420
|
||||
000B8 40.015,2.960 40.115,3.030 40.015,5.840 40.115,5.910 40.015,8.720 40.115,8.790 40.015,11.600 40.115,11.670 40.015,14.480 40.115,14.550 40.015,17.360 40.115,17.430 40.015,20.240 40.115,20.310 40.015,23.120 40.115,23.190 40.015,26.000 40.115,26.070 40.015,72.060 40.115,71.990 40.015,74.940 40.115,74.870 40.015,77.820 40.115,77.750 40.015,80.700 40.115,80.630 40.015,83.580 40.115,83.510 40.015,86.460 40.115,86.390 40.015,89.340 40.115,89.270 40.015,92.220 40.115,92.150 40.015,95.100 40.115,95.030 40.015,97.980 40.115,97.910
|
||||
000B9 40.015,1.590 40.115,1.520 40.015,4.470 40.115,4.400 40.015,7.350 40.115,7.280 40.015,10.230 40.115,10.160 40.015,13.110 40.115,13.040 40.015,15.990 40.115,15.920 40.015,18.870 40.115,18.800 40.015,21.750 40.115,21.680 40.015,24.630 40.115,24.560 40.015,73.430 40.115,73.500 40.015,76.310 40.115,76.380 40.015,79.190 40.115,79.260 40.015,82.070 40.115,82.140 40.015,84.950 40.115,85.020 40.015,87.830 40.115,87.900 40.015,90.710 40.115,90.780 40.015,93.590 40.115,93.660 40.015,96.470 40.115,96.540 40.015,99.350 40.115,99.420
|
||||
000BA 40.385,2.960 40.285,3.030 40.385,5.840 40.285,5.910 40.385,8.720 40.285,8.790 40.385,11.600 40.285,11.670 40.385,14.480 40.285,14.550 40.385,17.360 40.285,17.430 40.385,20.240 40.285,20.310 40.385,23.120 40.285,23.190 40.385,26.000 40.285,26.070 40.385,72.060 40.285,71.990 40.385,74.940 40.285,74.870 40.385,77.820 40.285,77.750 40.385,80.700 40.285,80.630 40.385,83.580 40.285,83.510 40.385,86.460 40.285,86.390 40.385,89.340 40.285,89.270 40.385,92.220 40.285,92.150 40.385,95.100 40.285,95.030 40.385,97.980 40.285,97.910
|
||||
000BB 40.385,1.590 40.285,1.520 40.385,4.470 40.285,4.400 40.385,7.350 40.285,7.280 40.385,10.230 40.285,10.160 40.385,13.110 40.285,13.040 40.385,15.990 40.285,15.920 40.385,18.870 40.285,18.800 40.385,21.750 40.285,21.680 40.385,24.630 40.285,24.560 40.385,73.430 40.285,73.500 40.385,76.310 40.285,76.380 40.385,79.190 40.285,79.260 40.385,82.070 40.285,82.140 40.385,84.950 40.285,85.020 40.385,87.830 40.285,87.900 40.385,90.710 40.285,90.780 40.385,93.590 40.285,93.660 40.385,96.470 40.285,96.540 40.385,99.350 40.285,99.420
|
||||
000BC 40.555,2.960 40.655,3.030 40.555,5.840 40.655,5.910 40.555,8.720 40.655,8.790 40.555,11.600 40.655,11.670 40.555,14.480 40.655,14.550 40.555,17.360 40.655,17.430 40.555,20.240 40.655,20.310 40.555,23.120 40.655,23.190 40.555,26.000 40.655,26.070 40.555,72.060 40.655,71.990 40.555,74.940 40.655,74.870 40.555,77.820 40.655,77.750 40.555,80.700 40.655,80.630 40.555,83.580 40.655,83.510 40.555,86.460 40.655,86.390 40.555,89.340 40.655,89.270 40.555,92.220 40.655,92.150 40.555,95.100 40.655,95.030 40.555,97.980 40.655,97.910
|
||||
000BD 40.555,1.590 40.655,1.520 40.555,4.470 40.655,4.400 40.555,7.350 40.655,7.280 40.555,10.230 40.655,10.160 40.555,13.110 40.655,13.040 40.555,15.990 40.655,15.920 40.555,18.870 40.655,18.800 40.555,21.750 40.655,21.680 40.555,24.630 40.655,24.560 40.555,73.430 40.655,73.500 40.555,76.310 40.655,76.380 40.555,79.190 40.655,79.260 40.555,82.070 40.655,82.140 40.555,84.950 40.655,85.020 40.555,87.830 40.655,87.900 40.555,90.710 40.655,90.780 40.555,93.590 40.655,93.660 40.555,96.470 40.655,96.540 40.555,99.350 40.655,99.420
|
||||
000BE 40.925,2.960 40.825,3.030 40.925,5.840 40.825,5.910 40.925,8.720 40.825,8.790 40.925,11.600 40.825,11.670 40.925,14.480 40.825,14.550 40.925,17.360 40.825,17.430 40.925,20.240 40.825,20.310 40.925,23.120 40.825,23.190 40.925,26.000 40.825,26.070 40.925,72.060 40.825,71.990 40.925,74.940 40.825,74.870 40.925,77.820 40.825,77.750 40.925,80.700 40.825,80.630 40.925,83.580 40.825,83.510 40.925,86.460 40.825,86.390 40.925,89.340 40.825,89.270 40.925,92.220 40.825,92.150 40.925,95.100 40.825,95.030 40.925,97.980 40.825,97.910
|
||||
000BF 40.925,1.590 40.825,1.520 40.925,4.470 40.825,4.400 40.925,7.350 40.825,7.280 40.925,10.230 40.825,10.160 40.925,13.110 40.825,13.040 40.925,15.990 40.825,15.920 40.925,18.870 40.825,18.800 40.925,21.750 40.825,21.680 40.925,24.630 40.825,24.560 40.925,73.430 40.825,73.500 40.925,76.310 40.825,76.380 40.925,79.190 40.825,79.260 40.925,82.070 40.825,82.140 40.925,84.950 40.825,85.020 40.925,87.830 40.825,87.900 40.925,90.710 40.825,90.780 40.925,93.590 40.825,93.660 40.925,96.470 40.825,96.540 40.925,99.350 40.825,99.420
|
||||
000C0 41.095,2.960 41.195,3.030 41.095,5.840 41.195,5.910 41.095,8.720 41.195,8.790 41.095,11.600 41.195,11.670 41.095,14.480 41.195,14.550 41.095,17.360 41.195,17.430 41.095,20.240 41.195,20.310 41.095,23.120 41.195,23.190 41.095,26.000 41.195,26.070 41.095,72.060 41.195,71.990 41.095,74.940 41.195,74.870 41.095,77.820 41.195,77.750 41.095,80.700 41.195,80.630 41.095,83.580 41.195,83.510 41.095,86.460 41.195,86.390 41.095,89.340 41.195,89.270 41.095,92.220 41.195,92.150 41.095,95.100 41.195,95.030 41.095,97.980 41.195,97.910
|
||||
000C1 41.095,1.590 41.195,1.520 41.095,4.470 41.195,4.400 41.095,7.350 41.195,7.280 41.095,10.230 41.195,10.160 41.095,13.110 41.195,13.040 41.095,15.990 41.195,15.920 41.095,18.870 41.195,18.800 41.095,21.750 41.195,21.680 41.095,24.630 41.195,24.560 41.095,73.430 41.195,73.500 41.095,76.310 41.195,76.380 41.095,79.190 41.195,79.260 41.095,82.070 41.195,82.140 41.095,84.950 41.195,85.020 41.095,87.830 41.195,87.900 41.095,90.710 41.195,90.780 41.095,93.590 41.195,93.660 41.095,96.470 41.195,96.540 41.095,99.350 41.195,99.420
|
||||
000C2 41.465,2.960 41.365,3.030 41.465,5.840 41.365,5.910 41.465,8.720 41.365,8.790 41.465,11.600 41.365,11.670 41.465,14.480 41.365,14.550 41.465,17.360 41.365,17.430 41.465,20.240 41.365,20.310 41.465,23.120 41.365,23.190 41.465,26.000 41.365,26.070 41.465,72.060 41.365,71.990 41.465,74.940 41.365,74.870 41.465,77.820 41.365,77.750 41.465,80.700 41.365,80.630 41.465,83.580 41.365,83.510 41.465,86.460 41.365,86.390 41.465,89.340 41.365,89.270 41.465,92.220 41.365,92.150 41.465,95.100 41.365,95.030 41.465,97.980 41.365,97.910
|
||||
000C3 41.465,1.590 41.365,1.520 41.465,4.470 41.365,4.400 41.465,7.350 41.365,7.280 41.465,10.230 41.365,10.160 41.465,13.110 41.365,13.040 41.465,15.990 41.365,15.920 41.465,18.870 41.365,18.800 41.465,21.750 41.365,21.680 41.465,24.630 41.365,24.560 41.465,73.430 41.365,73.500 41.465,76.310 41.365,76.380 41.465,79.190 41.365,79.260 41.465,82.070 41.365,82.140 41.465,84.950 41.365,85.020 41.465,87.830 41.365,87.900 41.465,90.710 41.365,90.780 41.465,93.590 41.365,93.660 41.465,96.470 41.365,96.540 41.465,99.350 41.365,99.420
|
||||
000C4 41.635,2.960 41.735,3.030 41.635,5.840 41.735,5.910 41.635,8.720 41.735,8.790 41.635,11.600 41.735,11.670 41.635,14.480 41.735,14.550 41.635,17.360 41.735,17.430 41.635,20.240 41.735,20.310 41.635,23.120 41.735,23.190 41.635,26.000 41.735,26.070 41.635,72.060 41.735,71.990 41.635,74.940 41.735,74.870 41.635,77.820 41.735,77.750 41.635,80.700 41.735,80.630 41.635,83.580 41.735,83.510 41.635,86.460 41.735,86.390 41.635,89.340 41.735,89.270 41.635,92.220 41.735,92.150 41.635,95.100 41.735,95.030 41.635,97.980 41.735,97.910
|
||||
000C5 41.635,1.590 41.735,1.520 41.635,4.470 41.735,4.400 41.635,7.350 41.735,7.280 41.635,10.230 41.735,10.160 41.635,13.110 41.735,13.040 41.635,15.990 41.735,15.920 41.635,18.870 41.735,18.800 41.635,21.750 41.735,21.680 41.635,24.630 41.735,24.560 41.635,73.430 41.735,73.500 41.635,76.310 41.735,76.380 41.635,79.190 41.735,79.260 41.635,82.070 41.735,82.140 41.635,84.950 41.735,85.020 41.635,87.830 41.735,87.900 41.635,90.710 41.735,90.780 41.635,93.590 41.735,93.660 41.635,96.470 41.735,96.540 41.635,99.350 41.735,99.420
|
||||
000C6 42.005,2.960 41.905,3.030 42.005,5.840 41.905,5.910 42.005,8.720 41.905,8.790 42.005,11.600 41.905,11.670 42.005,14.480 41.905,14.550 42.005,17.360 41.905,17.430 42.005,20.240 41.905,20.310 42.005,23.120 41.905,23.190 42.005,26.000 41.905,26.070 42.005,72.060 41.905,71.990 42.005,74.940 41.905,74.870 42.005,77.820 41.905,77.750 42.005,80.700 41.905,80.630 42.005,83.580 41.905,83.510 42.005,86.460 41.905,86.390 42.005,89.340 41.905,89.270 42.005,92.220 41.905,92.150 42.005,95.100 41.905,95.030 42.005,97.980 41.905,97.910
|
||||
000C7 42.005,1.590 41.905,1.520 42.005,4.470 41.905,4.400 42.005,7.350 41.905,7.280 42.005,10.230 41.905,10.160 42.005,13.110 41.905,13.040 42.005,15.990 41.905,15.920 42.005,18.870 41.905,18.800 42.005,21.750 41.905,21.680 42.005,24.630 41.905,24.560 42.005,73.430 41.905,73.500 42.005,76.310 41.905,76.380 42.005,79.190 41.905,79.260 42.005,82.070 41.905,82.140 42.005,84.950 41.905,85.020 42.005,87.830 41.905,87.900 42.005,90.710 41.905,90.780 42.005,93.590 41.905,93.660 42.005,96.470 41.905,96.540 42.005,99.350 41.905,99.420
|
||||
000C8 42.175,2.960 42.275,3.030 42.175,5.840 42.275,5.910 42.175,8.720 42.275,8.790 42.175,11.600 42.275,11.670 42.175,14.480 42.275,14.550 42.175,17.360 42.275,17.430 42.175,20.240 42.275,20.310 42.175,23.120 42.275,23.190 42.175,26.000 42.275,26.070 42.175,72.060 42.275,71.990 42.175,74.940 42.275,74.870 42.175,77.820 42.275,77.750 42.175,80.700 42.275,80.630 42.175,83.580 42.275,83.510 42.175,86.460 42.275,86.390 42.175,89.340 42.275,89.270 42.175,92.220 42.275,92.150 42.175,95.100 42.275,95.030 42.175,97.980 42.275,97.910
|
||||
000C9 42.175,1.590 42.275,1.520 42.175,4.470 42.275,4.400 42.175,7.350 42.275,7.280 42.175,10.230 42.275,10.160 42.175,13.110 42.275,13.040 42.175,15.990 42.275,15.920 42.175,18.870 42.275,18.800 42.175,21.750 42.275,21.680 42.175,24.630 42.275,24.560 42.175,73.430 42.275,73.500 42.175,76.310 42.275,76.380 42.175,79.190 42.275,79.260 42.175,82.070 42.275,82.140 42.175,84.950 42.275,85.020 42.175,87.830 42.275,87.900 42.175,90.710 42.275,90.780 42.175,93.590 42.275,93.660 42.175,96.470 42.275,96.540 42.175,99.350 42.275,99.420
|
||||
000CA 42.545,2.960 42.445,3.030 42.545,5.840 42.445,5.910 42.545,8.720 42.445,8.790 42.545,11.600 42.445,11.670 42.545,14.480 42.445,14.550 42.545,17.360 42.445,17.430 42.545,20.240 42.445,20.310 42.545,23.120 42.445,23.190 42.545,26.000 42.445,26.070 42.545,72.060 42.445,71.990 42.545,74.940 42.445,74.870 42.545,77.820 42.445,77.750 42.545,80.700 42.445,80.630 42.545,83.580 42.445,83.510 42.545,86.460 42.445,86.390 42.545,89.340 42.445,89.270 42.545,92.220 42.445,92.150 42.545,95.100 42.445,95.030 42.545,97.980 42.445,97.910
|
||||
000CB 42.545,1.590 42.445,1.520 42.545,4.470 42.445,4.400 42.545,7.350 42.445,7.280 42.545,10.230 42.445,10.160 42.545,13.110 42.445,13.040 42.545,15.990 42.445,15.920 42.545,18.870 42.445,18.800 42.545,21.750 42.445,21.680 42.545,24.630 42.445,24.560 42.545,73.430 42.445,73.500 42.545,76.310 42.445,76.380 42.545,79.190 42.445,79.260 42.545,82.070 42.445,82.140 42.545,84.950 42.445,85.020 42.545,87.830 42.445,87.900 42.545,90.710 42.445,90.780 42.545,93.590 42.445,93.660 42.545,96.470 42.445,96.540 42.545,99.350 42.445,99.420
|
||||
000CC 42.715,2.960 42.815,3.030 42.715,5.840 42.815,5.910 42.715,8.720 42.815,8.790 42.715,11.600 42.815,11.670 42.715,14.480 42.815,14.550 42.715,17.360 42.815,17.430 42.715,20.240 42.815,20.310 42.715,23.120 42.815,23.190 42.715,26.000 42.815,26.070 42.715,72.060 42.815,71.990 42.715,74.940 42.815,74.870 42.715,77.820 42.815,77.750 42.715,80.700 42.815,80.630 42.715,83.580 42.815,83.510 42.715,86.460 42.815,86.390 42.715,89.340 42.815,89.270 42.715,92.220 42.815,92.150 42.715,95.100 42.815,95.030 42.715,97.980 42.815,97.910
|
||||
000CD 42.715,1.590 42.815,1.520 42.715,4.470 42.815,4.400 42.715,7.350 42.815,7.280 42.715,10.230 42.815,10.160 42.715,13.110 42.815,13.040 42.715,15.990 42.815,15.920 42.715,18.870 42.815,18.800 42.715,21.750 42.815,21.680 42.715,24.630 42.815,24.560 42.715,73.430 42.815,73.500 42.715,76.310 42.815,76.380 42.715,79.190 42.815,79.260 42.715,82.070 42.815,82.140 42.715,84.950 42.815,85.020 42.715,87.830 42.815,87.900 42.715,90.710 42.815,90.780 42.715,93.590 42.815,93.660 42.715,96.470 42.815,96.540 42.715,99.350 42.815,99.420
|
||||
000CE 43.085,2.960 42.985,3.030 43.085,5.840 42.985,5.910 43.085,8.720 42.985,8.790 43.085,11.600 42.985,11.670 43.085,14.480 42.985,14.550 43.085,17.360 42.985,17.430 43.085,20.240 42.985,20.310 43.085,23.120 42.985,23.190 43.085,26.000 42.985,26.070 43.085,72.060 42.985,71.990 43.085,74.940 42.985,74.870 43.085,77.820 42.985,77.750 43.085,80.700 42.985,80.630 43.085,83.580 42.985,83.510 43.085,86.460 42.985,86.390 43.085,89.340 42.985,89.270 43.085,92.220 42.985,92.150 43.085,95.100 42.985,95.030 43.085,97.980 42.985,97.910
|
||||
000CF 43.085,1.590 42.985,1.520 43.085,4.470 42.985,4.400 43.085,7.350 42.985,7.280 43.085,10.230 42.985,10.160 43.085,13.110 42.985,13.040 43.085,15.990 42.985,15.920 43.085,18.870 42.985,18.800 43.085,21.750 42.985,21.680 43.085,24.630 42.985,24.560 43.085,73.430 42.985,73.500 43.085,76.310 42.985,76.380 43.085,79.190 42.985,79.260 43.085,82.070 42.985,82.140 43.085,84.950 42.985,85.020 43.085,87.830 42.985,87.900 43.085,90.710 42.985,90.780 43.085,93.590 42.985,93.660 43.085,96.470 42.985,96.540 43.085,99.350 42.985,99.420
|
||||
000D0 43.255,2.960 43.355,3.030 43.255,5.840 43.355,5.910 43.255,8.720 43.355,8.790 43.255,11.600 43.355,11.670 43.255,14.480 43.355,14.550 43.255,17.360 43.355,17.430 43.255,20.240 43.355,20.310 43.255,23.120 43.355,23.190 43.255,26.000 43.355,26.070 43.255,72.060 43.355,71.990 43.255,74.940 43.355,74.870 43.255,77.820 43.355,77.750 43.255,80.700 43.355,80.630 43.255,83.580 43.355,83.510 43.255,86.460 43.355,86.390 43.255,89.340 43.355,89.270 43.255,92.220 43.355,92.150 43.255,95.100 43.355,95.030 43.255,97.980 43.355,97.910
|
||||
000D1 43.255,1.590 43.355,1.520 43.255,4.470 43.355,4.400 43.255,7.350 43.355,7.280 43.255,10.230 43.355,10.160 43.255,13.110 43.355,13.040 43.255,15.990 43.355,15.920 43.255,18.870 43.355,18.800 43.255,21.750 43.355,21.680 43.255,24.630 43.355,24.560 43.255,73.430 43.355,73.500 43.255,76.310 43.355,76.380 43.255,79.190 43.355,79.260 43.255,82.070 43.355,82.140 43.255,84.950 43.355,85.020 43.255,87.830 43.355,87.900 43.255,90.710 43.355,90.780 43.255,93.590 43.355,93.660 43.255,96.470 43.355,96.540 43.255,99.350 43.355,99.420
|
||||
000D2 43.625,2.960 43.525,3.030 43.625,5.840 43.525,5.910 43.625,8.720 43.525,8.790 43.625,11.600 43.525,11.670 43.625,14.480 43.525,14.550 43.625,17.360 43.525,17.430 43.625,20.240 43.525,20.310 43.625,23.120 43.525,23.190 43.625,26.000 43.525,26.070 43.625,72.060 43.525,71.990 43.625,74.940 43.525,74.870 43.625,77.820 43.525,77.750 43.625,80.700 43.525,80.630 43.625,83.580 43.525,83.510 43.625,86.460 43.525,86.390 43.625,89.340 43.525,89.270 43.625,92.220 43.525,92.150 43.625,95.100 43.525,95.030 43.625,97.980 43.525,97.910
|
||||
000D3 43.625,1.590 43.525,1.520 43.625,4.470 43.525,4.400 43.625,7.350 43.525,7.280 43.625,10.230 43.525,10.160 43.625,13.110 43.525,13.040 43.625,15.990 43.525,15.920 43.625,18.870 43.525,18.800 43.625,21.750 43.525,21.680 43.625,24.630 43.525,24.560 43.625,73.430 43.525,73.500 43.625,76.310 43.525,76.380 43.625,79.190 43.525,79.260 43.625,82.070 43.525,82.140 43.625,84.950 43.525,85.020 43.625,87.830 43.525,87.900 43.625,90.710 43.525,90.780 43.625,93.590 43.525,93.660 43.625,96.470 43.525,96.540 43.625,99.350 43.525,99.420
|
||||
000D4 43.795,2.960 43.895,3.030 43.795,5.840 43.895,5.910 43.795,8.720 43.895,8.790 43.795,11.600 43.895,11.670 43.795,14.480 43.895,14.550 43.795,17.360 43.895,17.430 43.795,20.240 43.895,20.310 43.795,23.120 43.895,23.190 43.795,26.000 43.895,26.070 43.795,72.060 43.895,71.990 43.795,74.940 43.895,74.870 43.795,77.820 43.895,77.750 43.795,80.700 43.895,80.630 43.795,83.580 43.895,83.510 43.795,86.460 43.895,86.390 43.795,89.340 43.895,89.270 43.795,92.220 43.895,92.150 43.795,95.100 43.895,95.030 43.795,97.980 43.895,97.910
|
||||
000D5 43.795,1.590 43.895,1.520 43.795,4.470 43.895,4.400 43.795,7.350 43.895,7.280 43.795,10.230 43.895,10.160 43.795,13.110 43.895,13.040 43.795,15.990 43.895,15.920 43.795,18.870 43.895,18.800 43.795,21.750 43.895,21.680 43.795,24.630 43.895,24.560 43.795,73.430 43.895,73.500 43.795,76.310 43.895,76.380 43.795,79.190 43.895,79.260 43.795,82.070 43.895,82.140 43.795,84.950 43.895,85.020 43.795,87.830 43.895,87.900 43.795,90.710 43.895,90.780 43.795,93.590 43.895,93.660 43.795,96.470 43.895,96.540 43.795,99.350 43.895,99.420
|
||||
000D6 44.165,2.960 44.065,3.030 44.165,5.840 44.065,5.910 44.165,8.720 44.065,8.790 44.165,11.600 44.065,11.670 44.165,14.480 44.065,14.550 44.165,17.360 44.065,17.430 44.165,20.240 44.065,20.310 44.165,23.120 44.065,23.190 44.165,26.000 44.065,26.070 44.165,72.060 44.065,71.990 44.165,74.940 44.065,74.870 44.165,77.820 44.065,77.750 44.165,80.700 44.065,80.630 44.165,83.580 44.065,83.510 44.165,86.460 44.065,86.390 44.165,89.340 44.065,89.270 44.165,92.220 44.065,92.150 44.165,95.100 44.065,95.030 44.165,97.980 44.065,97.910
|
||||
000D7 44.165,1.590 44.065,1.520 44.165,4.470 44.065,4.400 44.165,7.350 44.065,7.280 44.165,10.230 44.065,10.160 44.165,13.110 44.065,13.040 44.165,15.990 44.065,15.920 44.165,18.870 44.065,18.800 44.165,21.750 44.065,21.680 44.165,24.630 44.065,24.560 44.165,73.430 44.065,73.500 44.165,76.310 44.065,76.380 44.165,79.190 44.065,79.260 44.165,82.070 44.065,82.140 44.165,84.950 44.065,85.020 44.165,87.830 44.065,87.900 44.165,90.710 44.065,90.780 44.165,93.590 44.065,93.660 44.165,96.470 44.065,96.540 44.165,99.350 44.065,99.420
|
||||
000D8 44.335,2.960 44.435,3.030 44.335,5.840 44.435,5.910 44.335,8.720 44.435,8.790 44.335,11.600 44.435,11.670 44.335,14.480 44.435,14.550 44.335,17.360 44.435,17.430 44.335,20.240 44.435,20.310 44.335,23.120 44.435,23.190 44.335,26.000 44.435,26.070 44.335,72.060 44.435,71.990 44.335,74.940 44.435,74.870 44.335,77.820 44.435,77.750 44.335,80.700 44.435,80.630 44.335,83.580 44.435,83.510 44.335,86.460 44.435,86.390 44.335,89.340 44.435,89.270 44.335,92.220 44.435,92.150 44.335,95.100 44.435,95.030 44.335,97.980 44.435,97.910
|
||||
000D9 44.335,1.590 44.435,1.520 44.335,4.470 44.435,4.400 44.335,7.350 44.435,7.280 44.335,10.230 44.435,10.160 44.335,13.110 44.435,13.040 44.335,15.990 44.435,15.920 44.335,18.870 44.435,18.800 44.335,21.750 44.435,21.680 44.335,24.630 44.435,24.560 44.335,73.430 44.435,73.500 44.335,76.310 44.435,76.380 44.335,79.190 44.435,79.260 44.335,82.070 44.435,82.140 44.335,84.950 44.435,85.020 44.335,87.830 44.435,87.900 44.335,90.710 44.435,90.780 44.335,93.590 44.435,93.660 44.335,96.470 44.435,96.540 44.335,99.350 44.435,99.420
|
||||
000DA 44.705,2.960 44.605,3.030 44.705,5.840 44.605,5.910 44.705,8.720 44.605,8.790 44.705,11.600 44.605,11.670 44.705,14.480 44.605,14.550 44.705,17.360 44.605,17.430 44.705,20.240 44.605,20.310 44.705,23.120 44.605,23.190 44.705,26.000 44.605,26.070 44.705,72.060 44.605,71.990 44.705,74.940 44.605,74.870 44.705,77.820 44.605,77.750 44.705,80.700 44.605,80.630 44.705,83.580 44.605,83.510 44.705,86.460 44.605,86.390 44.705,89.340 44.605,89.270 44.705,92.220 44.605,92.150 44.705,95.100 44.605,95.030 44.705,97.980 44.605,97.910
|
||||
000DB 44.705,1.590 44.605,1.520 44.705,4.470 44.605,4.400 44.705,7.350 44.605,7.280 44.705,10.230 44.605,10.160 44.705,13.110 44.605,13.040 44.705,15.990 44.605,15.920 44.705,18.870 44.605,18.800 44.705,21.750 44.605,21.680 44.705,24.630 44.605,24.560 44.705,73.430 44.605,73.500 44.705,76.310 44.605,76.380 44.705,79.190 44.605,79.260 44.705,82.070 44.605,82.140 44.705,84.950 44.605,85.020 44.705,87.830 44.605,87.900 44.705,90.710 44.605,90.780 44.705,93.590 44.605,93.660 44.705,96.470 44.605,96.540 44.705,99.350 44.605,99.420
|
||||
000DC 44.875,2.960 44.975,3.030 44.875,5.840 44.975,5.910 44.875,8.720 44.975,8.790 44.875,11.600 44.975,11.670 44.875,14.480 44.975,14.550 44.875,17.360 44.975,17.430 44.875,20.240 44.975,20.310 44.875,23.120 44.975,23.190 44.875,26.000 44.975,26.070 44.875,72.060 44.975,71.990 44.875,74.940 44.975,74.870 44.875,77.820 44.975,77.750 44.875,80.700 44.975,80.630 44.875,83.580 44.975,83.510 44.875,86.460 44.975,86.390 44.875,89.340 44.975,89.270 44.875,92.220 44.975,92.150 44.875,95.100 44.975,95.030 44.875,97.980 44.975,97.910
|
||||
000DD 44.875,1.590 44.975,1.520 44.875,4.470 44.975,4.400 44.875,7.350 44.975,7.280 44.875,10.230 44.975,10.160 44.875,13.110 44.975,13.040 44.875,15.990 44.975,15.920 44.875,18.870 44.975,18.800 44.875,21.750 44.975,21.680 44.875,24.630 44.975,24.560 44.875,73.430 44.975,73.500 44.875,76.310 44.975,76.380 44.875,79.190 44.975,79.260 44.875,82.070 44.975,82.140 44.875,84.950 44.975,85.020 44.875,87.830 44.975,87.900 44.875,90.710 44.975,90.780 44.875,93.590 44.975,93.660 44.875,96.470 44.975,96.540 44.875,99.350 44.975,99.420
|
||||
000DE 45.245,2.960 45.145,3.030 45.245,5.840 45.145,5.910 45.245,8.720 45.145,8.790 45.245,11.600 45.145,11.670 45.245,14.480 45.145,14.550 45.245,17.360 45.145,17.430 45.245,20.240 45.145,20.310 45.245,23.120 45.145,23.190 45.245,26.000 45.145,26.070 45.245,72.060 45.145,71.990 45.245,74.940 45.145,74.870 45.245,77.820 45.145,77.750 45.245,80.700 45.145,80.630 45.245,83.580 45.145,83.510 45.245,86.460 45.145,86.390 45.245,89.340 45.145,89.270 45.245,92.220 45.145,92.150 45.245,95.100 45.145,95.030 45.245,97.980 45.145,97.910
|
||||
000DF 45.245,1.590 45.145,1.520 45.245,4.470 45.145,4.400 45.245,7.350 45.145,7.280 45.245,10.230 45.145,10.160 45.245,13.110 45.145,13.040 45.245,15.990 45.145,15.920 45.245,18.870 45.145,18.800 45.245,21.750 45.145,21.680 45.245,24.630 45.145,24.560 45.245,73.430 45.145,73.500 45.245,76.310 45.145,76.380 45.245,79.190 45.145,79.260 45.245,82.070 45.145,82.140 45.245,84.950 45.145,85.020 45.245,87.830 45.145,87.900 45.245,90.710 45.145,90.780 45.245,93.590 45.145,93.660 45.245,96.470 45.145,96.540 45.245,99.350 45.145,99.420
|
||||
000E0 45.415,2.960 45.515,3.030 45.415,5.840 45.515,5.910 45.415,8.720 45.515,8.790 45.415,11.600 45.515,11.670 45.415,14.480 45.515,14.550 45.415,17.360 45.515,17.430 45.415,20.240 45.515,20.310 45.415,23.120 45.515,23.190 45.415,26.000 45.515,26.070 45.415,72.060 45.515,71.990 45.415,74.940 45.515,74.870 45.415,77.820 45.515,77.750 45.415,80.700 45.515,80.630 45.415,83.580 45.515,83.510 45.415,86.460 45.515,86.390 45.415,89.340 45.515,89.270 45.415,92.220 45.515,92.150 45.415,95.100 45.515,95.030 45.415,97.980 45.515,97.910
|
||||
000E1 45.415,1.590 45.515,1.520 45.415,4.470 45.515,4.400 45.415,7.350 45.515,7.280 45.415,10.230 45.515,10.160 45.415,13.110 45.515,13.040 45.415,15.990 45.515,15.920 45.415,18.870 45.515,18.800 45.415,21.750 45.515,21.680 45.415,24.630 45.515,24.560 45.415,73.430 45.515,73.500 45.415,76.310 45.515,76.380 45.415,79.190 45.515,79.260 45.415,82.070 45.515,82.140 45.415,84.950 45.515,85.020 45.415,87.830 45.515,87.900 45.415,90.710 45.515,90.780 45.415,93.590 45.515,93.660 45.415,96.470 45.515,96.540 45.415,99.350 45.515,99.420
|
||||
000E2 45.785,2.960 45.685,3.030 45.785,5.840 45.685,5.910 45.785,8.720 45.685,8.790 45.785,11.600 45.685,11.670 45.785,14.480 45.685,14.550 45.785,17.360 45.685,17.430 45.785,20.240 45.685,20.310 45.785,23.120 45.685,23.190 45.785,26.000 45.685,26.070 45.785,72.060 45.685,71.990 45.785,74.940 45.685,74.870 45.785,77.820 45.685,77.750 45.785,80.700 45.685,80.630 45.785,83.580 45.685,83.510 45.785,86.460 45.685,86.390 45.785,89.340 45.685,89.270 45.785,92.220 45.685,92.150 45.785,95.100 45.685,95.030 45.785,97.980 45.685,97.910
|
||||
000E3 45.785,1.590 45.685,1.520 45.785,4.470 45.685,4.400 45.785,7.350 45.685,7.280 45.785,10.230 45.685,10.160 45.785,13.110 45.685,13.040 45.785,15.990 45.685,15.920 45.785,18.870 45.685,18.800 45.785,21.750 45.685,21.680 45.785,24.630 45.685,24.560 45.785,73.430 45.685,73.500 45.785,76.310 45.685,76.380 45.785,79.190 45.685,79.260 45.785,82.070 45.685,82.140 45.785,84.950 45.685,85.020 45.785,87.830 45.685,87.900 45.785,90.710 45.685,90.780 45.785,93.590 45.685,93.660 45.785,96.470 45.685,96.540 45.785,99.350 45.685,99.420
|
||||
000E4 45.955,2.960 46.055,3.030 45.955,5.840 46.055,5.910 45.955,8.720 46.055,8.790 45.955,11.600 46.055,11.670 45.955,14.480 46.055,14.550 45.955,17.360 46.055,17.430 45.955,20.240 46.055,20.310 45.955,23.120 46.055,23.190 45.955,26.000 46.055,26.070 45.955,72.060 46.055,71.990 45.955,74.940 46.055,74.870 45.955,77.820 46.055,77.750 45.955,80.700 46.055,80.630 45.955,83.580 46.055,83.510 45.955,86.460 46.055,86.390 45.955,89.340 46.055,89.270 45.955,92.220 46.055,92.150 45.955,95.100 46.055,95.030 45.955,97.980 46.055,97.910
|
||||
000E5 45.955,1.590 46.055,1.520 45.955,4.470 46.055,4.400 45.955,7.350 46.055,7.280 45.955,10.230 46.055,10.160 45.955,13.110 46.055,13.040 45.955,15.990 46.055,15.920 45.955,18.870 46.055,18.800 45.955,21.750 46.055,21.680 45.955,24.630 46.055,24.560 45.955,73.430 46.055,73.500 45.955,76.310 46.055,76.380 45.955,79.190 46.055,79.260 45.955,82.070 46.055,82.140 45.955,84.950 46.055,85.020 45.955,87.830 46.055,87.900 45.955,90.710 46.055,90.780 45.955,93.590 46.055,93.660 45.955,96.470 46.055,96.540 45.955,99.350 46.055,99.420
|
||||
000E6 46.325,2.960 46.225,3.030 46.325,5.840 46.225,5.910 46.325,8.720 46.225,8.790 46.325,11.600 46.225,11.670 46.325,14.480 46.225,14.550 46.325,17.360 46.225,17.430 46.325,20.240 46.225,20.310 46.325,23.120 46.225,23.190 46.325,26.000 46.225,26.070 46.325,72.060 46.225,71.990 46.325,74.940 46.225,74.870 46.325,77.820 46.225,77.750 46.325,80.700 46.225,80.630 46.325,83.580 46.225,83.510 46.325,86.460 46.225,86.390 46.325,89.340 46.225,89.270 46.325,92.220 46.225,92.150 46.325,95.100 46.225,95.030 46.325,97.980 46.225,97.910
|
||||
000E7 46.325,1.590 46.225,1.520 46.325,4.470 46.225,4.400 46.325,7.350 46.225,7.280 46.325,10.230 46.225,10.160 46.325,13.110 46.225,13.040 46.325,15.990 46.225,15.920 46.325,18.870 46.225,18.800 46.325,21.750 46.225,21.680 46.325,24.630 46.225,24.560 46.325,73.430 46.225,73.500 46.325,76.310 46.225,76.380 46.325,79.190 46.225,79.260 46.325,82.070 46.225,82.140 46.325,84.950 46.225,85.020 46.325,87.830 46.225,87.900 46.325,90.710 46.225,90.780 46.325,93.590 46.225,93.660 46.325,96.470 46.225,96.540 46.325,99.350 46.225,99.420
|
||||
000E8 46.495,2.960 46.595,3.030 46.495,5.840 46.595,5.910 46.495,8.720 46.595,8.790 46.495,11.600 46.595,11.670 46.495,14.480 46.595,14.550 46.495,17.360 46.595,17.430 46.495,20.240 46.595,20.310 46.495,23.120 46.595,23.190 46.495,26.000 46.595,26.070 46.495,72.060 46.595,71.990 46.495,74.940 46.595,74.870 46.495,77.820 46.595,77.750 46.495,80.700 46.595,80.630 46.495,83.580 46.595,83.510 46.495,86.460 46.595,86.390 46.495,89.340 46.595,89.270 46.495,92.220 46.595,92.150 46.495,95.100 46.595,95.030 46.495,97.980 46.595,97.910
|
||||
000E9 46.495,1.590 46.595,1.520 46.495,4.470 46.595,4.400 46.495,7.350 46.595,7.280 46.495,10.230 46.595,10.160 46.495,13.110 46.595,13.040 46.495,15.990 46.595,15.920 46.495,18.870 46.595,18.800 46.495,21.750 46.595,21.680 46.495,24.630 46.595,24.560 46.495,73.430 46.595,73.500 46.495,76.310 46.595,76.380 46.495,79.190 46.595,79.260 46.495,82.070 46.595,82.140 46.495,84.950 46.595,85.020 46.495,87.830 46.595,87.900 46.495,90.710 46.595,90.780 46.495,93.590 46.595,93.660 46.495,96.470 46.595,96.540 46.495,99.350 46.595,99.420
|
||||
000EA 46.865,2.960 46.765,3.030 46.865,5.840 46.765,5.910 46.865,8.720 46.765,8.790 46.865,11.600 46.765,11.670 46.865,14.480 46.765,14.550 46.865,17.360 46.765,17.430 46.865,20.240 46.765,20.310 46.865,23.120 46.765,23.190 46.865,26.000 46.765,26.070 46.865,72.060 46.765,71.990 46.865,74.940 46.765,74.870 46.865,77.820 46.765,77.750 46.865,80.700 46.765,80.630 46.865,83.580 46.765,83.510 46.865,86.460 46.765,86.390 46.865,89.340 46.765,89.270 46.865,92.220 46.765,92.150 46.865,95.100 46.765,95.030 46.865,97.980 46.765,97.910
|
||||
000EB 46.865,1.590 46.765,1.520 46.865,4.470 46.765,4.400 46.865,7.350 46.765,7.280 46.865,10.230 46.765,10.160 46.865,13.110 46.765,13.040 46.865,15.990 46.765,15.920 46.865,18.870 46.765,18.800 46.865,21.750 46.765,21.680 46.865,24.630 46.765,24.560 46.865,73.430 46.765,73.500 46.865,76.310 46.765,76.380 46.865,79.190 46.765,79.260 46.865,82.070 46.765,82.140 46.865,84.950 46.765,85.020 46.865,87.830 46.765,87.900 46.865,90.710 46.765,90.780 46.865,93.590 46.765,93.660 46.865,96.470 46.765,96.540 46.865,99.350 46.765,99.420
|
||||
000EC 47.035,2.960 47.135,3.030 47.035,5.840 47.135,5.910 47.035,8.720 47.135,8.790 47.035,11.600 47.135,11.670 47.035,14.480 47.135,14.550 47.035,17.360 47.135,17.430 47.035,20.240 47.135,20.310 47.035,23.120 47.135,23.190 47.035,26.000 47.135,26.070 47.035,72.060 47.135,71.990 47.035,74.940 47.135,74.870 47.035,77.820 47.135,77.750 47.035,80.700 47.135,80.630 47.035,83.580 47.135,83.510 47.035,86.460 47.135,86.390 47.035,89.340 47.135,89.270 47.035,92.220 47.135,92.150 47.035,95.100 47.135,95.030 47.035,97.980 47.135,97.910
|
||||
000ED 47.035,1.590 47.135,1.520 47.035,4.470 47.135,4.400 47.035,7.350 47.135,7.280 47.035,10.230 47.135,10.160 47.035,13.110 47.135,13.040 47.035,15.990 47.135,15.920 47.035,18.870 47.135,18.800 47.035,21.750 47.135,21.680 47.035,24.630 47.135,24.560 47.035,73.430 47.135,73.500 47.035,76.310 47.135,76.380 47.035,79.190 47.135,79.260 47.035,82.070 47.135,82.140 47.035,84.950 47.135,85.020 47.035,87.830 47.135,87.900 47.035,90.710 47.135,90.780 47.035,93.590 47.135,93.660 47.035,96.470 47.135,96.540 47.035,99.350 47.135,99.420
|
||||
000EE 47.405,2.960 47.305,3.030 47.405,5.840 47.305,5.910 47.405,8.720 47.305,8.790 47.405,11.600 47.305,11.670 47.405,14.480 47.305,14.550 47.405,17.360 47.305,17.430 47.405,20.240 47.305,20.310 47.405,23.120 47.305,23.190 47.405,26.000 47.305,26.070 47.405,72.060 47.305,71.990 47.405,74.940 47.305,74.870 47.405,77.820 47.305,77.750 47.405,80.700 47.305,80.630 47.405,83.580 47.305,83.510 47.405,86.460 47.305,86.390 47.405,89.340 47.305,89.270 47.405,92.220 47.305,92.150 47.405,95.100 47.305,95.030 47.405,97.980 47.305,97.910
|
||||
000EF 47.405,1.590 47.305,1.520 47.405,4.470 47.305,4.400 47.405,7.350 47.305,7.280 47.405,10.230 47.305,10.160 47.405,13.110 47.305,13.040 47.405,15.990 47.305,15.920 47.405,18.870 47.305,18.800 47.405,21.750 47.305,21.680 47.405,24.630 47.305,24.560 47.405,73.430 47.305,73.500 47.405,76.310 47.305,76.380 47.405,79.190 47.305,79.260 47.405,82.070 47.305,82.140 47.405,84.950 47.305,85.020 47.405,87.830 47.305,87.900 47.405,90.710 47.305,90.780 47.405,93.590 47.305,93.660 47.405,96.470 47.305,96.540 47.405,99.350 47.305,99.420
|
||||
000F0 47.575,2.960 47.675,3.030 47.575,5.840 47.675,5.910 47.575,8.720 47.675,8.790 47.575,11.600 47.675,11.670 47.575,14.480 47.675,14.550 47.575,17.360 47.675,17.430 47.575,20.240 47.675,20.310 47.575,23.120 47.675,23.190 47.575,26.000 47.675,26.070 47.575,72.060 47.675,71.990 47.575,74.940 47.675,74.870 47.575,77.820 47.675,77.750 47.575,80.700 47.675,80.630 47.575,83.580 47.675,83.510 47.575,86.460 47.675,86.390 47.575,89.340 47.675,89.270 47.575,92.220 47.675,92.150 47.575,95.100 47.675,95.030 47.575,97.980 47.675,97.910
|
||||
000F1 47.575,1.590 47.675,1.520 47.575,4.470 47.675,4.400 47.575,7.350 47.675,7.280 47.575,10.230 47.675,10.160 47.575,13.110 47.675,13.040 47.575,15.990 47.675,15.920 47.575,18.870 47.675,18.800 47.575,21.750 47.675,21.680 47.575,24.630 47.675,24.560 47.575,73.430 47.675,73.500 47.575,76.310 47.675,76.380 47.575,79.190 47.675,79.260 47.575,82.070 47.675,82.140 47.575,84.950 47.675,85.020 47.575,87.830 47.675,87.900 47.575,90.710 47.675,90.780 47.575,93.590 47.675,93.660 47.575,96.470 47.675,96.540 47.575,99.350 47.675,99.420
|
||||
000F2 47.945,2.960 47.845,3.030 47.945,5.840 47.845,5.910 47.945,8.720 47.845,8.790 47.945,11.600 47.845,11.670 47.945,14.480 47.845,14.550 47.945,17.360 47.845,17.430 47.945,20.240 47.845,20.310 47.945,23.120 47.845,23.190 47.945,26.000 47.845,26.070 47.945,72.060 47.845,71.990 47.945,74.940 47.845,74.870 47.945,77.820 47.845,77.750 47.945,80.700 47.845,80.630 47.945,83.580 47.845,83.510 47.945,86.460 47.845,86.390 47.945,89.340 47.845,89.270 47.945,92.220 47.845,92.150 47.945,95.100 47.845,95.030 47.945,97.980 47.845,97.910
|
||||
000F3 47.945,1.590 47.845,1.520 47.945,4.470 47.845,4.400 47.945,7.350 47.845,7.280 47.945,10.230 47.845,10.160 47.945,13.110 47.845,13.040 47.945,15.990 47.845,15.920 47.945,18.870 47.845,18.800 47.945,21.750 47.845,21.680 47.945,24.630 47.845,24.560 47.945,73.430 47.845,73.500 47.945,76.310 47.845,76.380 47.945,79.190 47.845,79.260 47.945,82.070 47.845,82.140 47.945,84.950 47.845,85.020 47.945,87.830 47.845,87.900 47.945,90.710 47.845,90.780 47.945,93.590 47.845,93.660 47.945,96.470 47.845,96.540 47.945,99.350 47.845,99.420
|
||||
000F4 48.115,2.960 48.215,3.030 48.115,5.840 48.215,5.910 48.115,8.720 48.215,8.790 48.115,11.600 48.215,11.670 48.115,14.480 48.215,14.550 48.115,17.360 48.215,17.430 48.115,20.240 48.215,20.310 48.115,23.120 48.215,23.190 48.115,26.000 48.215,26.070 48.115,72.060 48.215,71.990 48.115,74.940 48.215,74.870 48.115,77.820 48.215,77.750 48.115,80.700 48.215,80.630 48.115,83.580 48.215,83.510 48.115,86.460 48.215,86.390 48.115,89.340 48.215,89.270 48.115,92.220 48.215,92.150 48.115,95.100 48.215,95.030 48.115,97.980 48.215,97.910
|
||||
000F5 48.115,1.590 48.215,1.520 48.115,4.470 48.215,4.400 48.115,7.350 48.215,7.280 48.115,10.230 48.215,10.160 48.115,13.110 48.215,13.040 48.115,15.990 48.215,15.920 48.115,18.870 48.215,18.800 48.115,21.750 48.215,21.680 48.115,24.630 48.215,24.560 48.115,73.430 48.215,73.500 48.115,76.310 48.215,76.380 48.115,79.190 48.215,79.260 48.115,82.070 48.215,82.140 48.115,84.950 48.215,85.020 48.115,87.830 48.215,87.900 48.115,90.710 48.215,90.780 48.115,93.590 48.215,93.660 48.115,96.470 48.215,96.540 48.115,99.350 48.215,99.420
|
||||
000F6 48.485,2.960 48.385,3.030 48.485,5.840 48.385,5.910 48.485,8.720 48.385,8.790 48.485,11.600 48.385,11.670 48.485,14.480 48.385,14.550 48.485,17.360 48.385,17.430 48.485,20.240 48.385,20.310 48.485,23.120 48.385,23.190 48.485,26.000 48.385,26.070 48.485,72.060 48.385,71.990 48.485,74.940 48.385,74.870 48.485,77.820 48.385,77.750 48.485,80.700 48.385,80.630 48.485,83.580 48.385,83.510 48.485,86.460 48.385,86.390 48.485,89.340 48.385,89.270 48.485,92.220 48.385,92.150 48.485,95.100 48.385,95.030 48.485,97.980 48.385,97.910
|
||||
000F7 48.485,1.590 48.385,1.520 48.485,4.470 48.385,4.400 48.485,7.350 48.385,7.280 48.485,10.230 48.385,10.160 48.485,13.110 48.385,13.040 48.485,15.990 48.385,15.920 48.485,18.870 48.385,18.800 48.485,21.750 48.385,21.680 48.485,24.630 48.385,24.560 48.485,73.430 48.385,73.500 48.485,76.310 48.385,76.380 48.485,79.190 48.385,79.260 48.485,82.070 48.385,82.140 48.485,84.950 48.385,85.020 48.485,87.830 48.385,87.900 48.485,90.710 48.385,90.780 48.485,93.590 48.385,93.660 48.485,96.470 48.385,96.540 48.485,99.350 48.385,99.420
|
||||
000F8 48.655,2.960 48.755,3.030 48.655,5.840 48.755,5.910 48.655,8.720 48.755,8.790 48.655,11.600 48.755,11.670 48.655,14.480 48.755,14.550 48.655,17.360 48.755,17.430 48.655,20.240 48.755,20.310 48.655,23.120 48.755,23.190 48.655,26.000 48.755,26.070 48.655,72.060 48.755,71.990 48.655,74.940 48.755,74.870 48.655,77.820 48.755,77.750 48.655,80.700 48.755,80.630 48.655,83.580 48.755,83.510 48.655,86.460 48.755,86.390 48.655,89.340 48.755,89.270 48.655,92.220 48.755,92.150 48.655,95.100 48.755,95.030 48.655,97.980 48.755,97.910
|
||||
000F9 48.655,1.590 48.755,1.520 48.655,4.470 48.755,4.400 48.655,7.350 48.755,7.280 48.655,10.230 48.755,10.160 48.655,13.110 48.755,13.040 48.655,15.990 48.755,15.920 48.655,18.870 48.755,18.800 48.655,21.750 48.755,21.680 48.655,24.630 48.755,24.560 48.655,73.430 48.755,73.500 48.655,76.310 48.755,76.380 48.655,79.190 48.755,79.260 48.655,82.070 48.755,82.140 48.655,84.950 48.755,85.020 48.655,87.830 48.755,87.900 48.655,90.710 48.755,90.780 48.655,93.590 48.755,93.660 48.655,96.470 48.755,96.540 48.655,99.350 48.755,99.420
|
||||
000FA 49.025,2.960 48.925,3.030 49.025,5.840 48.925,5.910 49.025,8.720 48.925,8.790 49.025,11.600 48.925,11.670 49.025,14.480 48.925,14.550 49.025,17.360 48.925,17.430 49.025,20.240 48.925,20.310 49.025,23.120 48.925,23.190 49.025,26.000 48.925,26.070 49.025,72.060 48.925,71.990 49.025,74.940 48.925,74.870 49.025,77.820 48.925,77.750 49.025,80.700 48.925,80.630 49.025,83.580 48.925,83.510 49.025,86.460 48.925,86.390 49.025,89.340 48.925,89.270 49.025,92.220 48.925,92.150 49.025,95.100 48.925,95.030 49.025,97.980 48.925,97.910
|
||||
000FB 49.025,1.590 48.925,1.520 49.025,4.470 48.925,4.400 49.025,7.350 48.925,7.280 49.025,10.230 48.925,10.160 49.025,13.110 48.925,13.040 49.025,15.990 48.925,15.920 49.025,18.870 48.925,18.800 49.025,21.750 48.925,21.680 49.025,24.630 48.925,24.560 49.025,73.430 48.925,73.500 49.025,76.310 48.925,76.380 49.025,79.190 48.925,79.260 49.025,82.070 48.925,82.140 49.025,84.950 48.925,85.020 49.025,87.830 48.925,87.900 49.025,90.710 48.925,90.780 49.025,93.590 48.925,93.660 49.025,96.470 48.925,96.540 49.025,99.350 48.925,99.420
|
||||
000FC 49.195,2.960 49.295,3.030 49.195,5.840 49.295,5.910 49.195,8.720 49.295,8.790 49.195,11.600 49.295,11.670 49.195,14.480 49.295,14.550 49.195,17.360 49.295,17.430 49.195,20.240 49.295,20.310 49.195,23.120 49.295,23.190 49.195,26.000 49.295,26.070 49.195,72.060 49.295,71.990 49.195,74.940 49.295,74.870 49.195,77.820 49.295,77.750 49.195,80.700 49.295,80.630 49.195,83.580 49.295,83.510 49.195,86.460 49.295,86.390 49.195,89.340 49.295,89.270 49.195,92.220 49.295,92.150 49.195,95.100 49.295,95.030 49.195,97.980 49.295,97.910
|
||||
000FD 49.195,1.590 49.295,1.520 49.195,4.470 49.295,4.400 49.195,7.350 49.295,7.280 49.195,10.230 49.295,10.160 49.195,13.110 49.295,13.040 49.195,15.990 49.295,15.920 49.195,18.870 49.295,18.800 49.195,21.750 49.295,21.680 49.195,24.630 49.295,24.560 49.195,73.430 49.295,73.500 49.195,76.310 49.295,76.380 49.195,79.190 49.295,79.260 49.195,82.070 49.295,82.140 49.195,84.950 49.295,85.020 49.195,87.830 49.295,87.900 49.195,90.710 49.295,90.780 49.195,93.590 49.295,93.660 49.195,96.470 49.295,96.540 49.195,99.350 49.295,99.420
|
||||
000FE 49.565,2.960 49.465,3.030 49.565,5.840 49.465,5.910 49.565,8.720 49.465,8.790 49.565,11.600 49.465,11.670 49.565,14.480 49.465,14.550 49.565,17.360 49.465,17.430 49.565,20.240 49.465,20.310 49.565,23.120 49.465,23.190 49.565,26.000 49.465,26.070 49.565,72.060 49.465,71.990 49.565,74.940 49.465,74.870 49.565,77.820 49.465,77.750 49.565,80.700 49.465,80.630 49.565,83.580 49.465,83.510 49.565,86.460 49.465,86.390 49.565,89.340 49.465,89.270 49.565,92.220 49.465,92.150 49.565,95.100 49.465,95.030 49.565,97.980 49.465,97.910
|
||||
000FF 49.565,1.590 49.465,1.520 49.565,4.470 49.465,4.400 49.565,7.350 49.465,7.280 49.565,10.230 49.465,10.160 49.565,13.110 49.465,13.040 49.565,15.990 49.465,15.920 49.565,18.870 49.465,18.800 49.565,21.750 49.465,21.680 49.565,24.630 49.465,24.560 49.565,73.430 49.465,73.500 49.565,76.310 49.465,76.380 49.565,79.190 49.465,79.260 49.565,82.070 49.465,82.140 49.565,84.950 49.465,85.020 49.565,87.830 49.465,87.900 49.565,90.710 49.465,90.780 49.565,93.590 49.465,93.660 49.565,96.470 49.465,96.540 49.565,99.350 49.465,99.420
|
||||
69
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.cpf
Normal file
69
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.cpf
Normal file
@@ -0,0 +1,69 @@
|
||||
# cpf_memcomp Version: 4.0.6-EAC
|
||||
# common_memcomp Version: c0.1.0-EAC
|
||||
# lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# CPF Macro-Model for High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Instance Name: rf2_256x19_wm0
|
||||
# Words: 256
|
||||
# Bits: 19
|
||||
# Mux: 2
|
||||
# Drive: 6
|
||||
# Write Mask: Off
|
||||
# Write Thru: Off
|
||||
# Extra Margin Adjustment: On
|
||||
# Test Muxes On
|
||||
# Power Gating: Off
|
||||
# Retention: On
|
||||
# Pipeline: Off
|
||||
# Read Disturb Test: Off
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:42:51 2019
|
||||
# Version: r4p0
|
||||
#
|
||||
set_cpf_version 1.1
|
||||
set_macro_model rf2_256x19_wm0
|
||||
|
||||
#The Voltages Specified in this macro-model not real. They are dummy values suggested by Cadence.
|
||||
create_nominal_condition -name nc_on -voltage 1 -ground_voltage 0.0 -state on
|
||||
create_nominal_condition -name nc_off -voltage 0.0 -ground_voltage 0.0 -state off
|
||||
|
||||
create_power_domain -name PDPE -default \
|
||||
-boundary_ports { CENYA AYA[*] CENYB AYB[*] QA[*] SOA[*] SOB[*] CLKA CENA AA[*] CLKB CENB AB[*] DB[*] EMAA[*] EMASA EMAB[*] TENA TCENA TAA[*] TENB TCENB TAB[*] TDB[*] SIA[*] SEA DFTRAMBYP SIB[*] SEB COLLDISN } \
|
||||
-instances { clk0_int CENA_int AA_int[7] AA_int[6] AA_int[5] AA_int[4] AA_int[3] AA_int[2] AA_int[1] AA_int[0] clk1_int CENB_int AB_int[7] AB_int[6] AB_int[5] AB_int[4] AB_int[3] AB_int[2] AB_int[1] AB_int[0] DB_int[18] DB_int[17] DB_int[16] DB_int[15] DB_int[14] DB_int[13] DB_int[12] DB_int[11] DB_int[10] DB_int[9] DB_int[8] DB_int[7] DB_int[6] DB_int[5] DB_int[4] DB_int[3] DB_int[2] DB_int[1] DB_int[0] EMAA_int[2] EMAA_int[1] EMAA_int[0] EMASA_int EMAB_int[2] EMAB_int[1] EMAB_int[0] TENA_int TCENA_int TAA_int[7] TAA_int[6] TAA_int[5] TAA_int[4] TAA_int[3] TAA_int[2] TAA_int[1] TAA_int[0] TENB_int TCENB_int TAB_int[7] TAB_int[6] TAB_int[5] TAB_int[4] TAB_int[3] TAB_int[2] TAB_int[1] TAB_int[0] TDB_int[18] TDB_int[17] TDB_int[16] TDB_int[15] TDB_int[14] TDB_int[13] TDB_int[12] TDB_int[11] TDB_int[10] TDB_int[9] TDB_int[8] TDB_int[7] TDB_int[6] TDB_int[5] TDB_int[4] TDB_int[3] TDB_int[2] TDB_int[1] TDB_int[0] SIA_int[1] SIA_int[0] SEA_int DFTRAMBYP_int SIB_int[1] SIB_int[0] SEB_int COLLDISN_int }
|
||||
update_power_domain -name PDPE \
|
||||
-primary_power_net VDDPE -primary_ground_net VSSE
|
||||
|
||||
create_power_domain -name PDCE \
|
||||
-boundary_ports { RET1N } \
|
||||
-instances { mem* RET1N_int }
|
||||
update_power_domain -name PDCE \
|
||||
-primary_power_net VDDCE -primary_ground_net VSSE
|
||||
|
||||
|
||||
# mode A1/A2 - Normal/Selective_Precharge
|
||||
create_power_mode -name PM1 -domain_conditions \
|
||||
{PDPE@nc_on PDCE@nc_on} -default
|
||||
|
||||
#mode A3 - Retention mode
|
||||
create_power_mode -name PM2 -domain_conditions \
|
||||
{PDPE@nc_off PDCE@nc_on}
|
||||
|
||||
#mode A4 - power down mode
|
||||
create_power_mode -name PM3 -domain_conditions \
|
||||
{PDPE@nc_off PDCE@nc_off}
|
||||
|
||||
|
||||
end_macro_model rf2_256x19_wm0
|
||||
405
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.ctl
Normal file
405
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.ctl
Normal file
@@ -0,0 +1,405 @@
|
||||
/* ctl_memcomp Version: 4.0.5-EAC3 */
|
||||
/* common_memcomp Version: 4.0.5.2-amci */
|
||||
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
|
||||
//
|
||||
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
//
|
||||
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
//
|
||||
// Use of this Software is subject to the terms and conditions of the
|
||||
// applicable license agreement with ARM Physical IP, Inc.
|
||||
// In addition, this Software is protected by patents, copyright law
|
||||
// and international treaties.
|
||||
//
|
||||
// The copyright notice(s) in this Software does not indicate actual or
|
||||
// intended publication of this Software.
|
||||
//
|
||||
// CTL model for High Density Two Port Register File SVT MVT Compiler
|
||||
//
|
||||
// Instance Name: rf2_256x19_wm0
|
||||
// Words: 256
|
||||
// Bits: 19
|
||||
// Mux: 2
|
||||
// Drive: 6
|
||||
// Write Mask: Off
|
||||
// Write Thru: Off
|
||||
// Extra Margin Adjustment: On
|
||||
// Redundant Columns: 2
|
||||
// Test Muxes On
|
||||
// Power Gating: Off
|
||||
// Retention: On
|
||||
// Pipeline: Off
|
||||
// Read Disturb Test: Off
|
||||
//
|
||||
// Creation Date: Sun Oct 20 14:42:52 2019
|
||||
// Version: r4p0
|
||||
STIL 1.0 {
|
||||
CTL P2001.10;
|
||||
Design P2001.01;
|
||||
}
|
||||
Header {
|
||||
Title "CTL model for `rf2_256x19_wm0";
|
||||
}
|
||||
Signals {
|
||||
"CENYA" Out;
|
||||
"AYA[7]" Out;
|
||||
"AYA[6]" Out;
|
||||
"AYA[5]" Out;
|
||||
"AYA[4]" Out;
|
||||
"AYA[3]" Out;
|
||||
"AYA[2]" Out;
|
||||
"AYA[1]" Out;
|
||||
"AYA[0]" Out;
|
||||
"CENYB" Out;
|
||||
"AYB[7]" Out;
|
||||
"AYB[6]" Out;
|
||||
"AYB[5]" Out;
|
||||
"AYB[4]" Out;
|
||||
"AYB[3]" Out;
|
||||
"AYB[2]" Out;
|
||||
"AYB[1]" Out;
|
||||
"AYB[0]" Out;
|
||||
"QA[18]" Out;
|
||||
"QA[17]" Out;
|
||||
"QA[16]" Out;
|
||||
"QA[15]" Out;
|
||||
"QA[14]" Out;
|
||||
"QA[13]" Out;
|
||||
"QA[12]" Out;
|
||||
"QA[11]" Out;
|
||||
"QA[10]" Out;
|
||||
"QA[9]" Out;
|
||||
"QA[8]" Out;
|
||||
"QA[7]" Out;
|
||||
"QA[6]" Out;
|
||||
"QA[5]" Out;
|
||||
"QA[4]" Out;
|
||||
"QA[3]" Out;
|
||||
"QA[2]" Out;
|
||||
"QA[1]" Out;
|
||||
"QA[0]" Out;
|
||||
"SOA[1]" Out;
|
||||
"SOA[0]" Out;
|
||||
"SOB[1]" Out;
|
||||
"SOB[0]" Out;
|
||||
"CLKA" In;
|
||||
"CENA" In;
|
||||
"AA[7]" In;
|
||||
"AA[6]" In;
|
||||
"AA[5]" In;
|
||||
"AA[4]" In;
|
||||
"AA[3]" In;
|
||||
"AA[2]" In;
|
||||
"AA[1]" In;
|
||||
"AA[0]" In;
|
||||
"CLKB" In;
|
||||
"CENB" In;
|
||||
"AB[7]" In;
|
||||
"AB[6]" In;
|
||||
"AB[5]" In;
|
||||
"AB[4]" In;
|
||||
"AB[3]" In;
|
||||
"AB[2]" In;
|
||||
"AB[1]" In;
|
||||
"AB[0]" In;
|
||||
"DB[18]" In;
|
||||
"DB[17]" In;
|
||||
"DB[16]" In;
|
||||
"DB[15]" In;
|
||||
"DB[14]" In;
|
||||
"DB[13]" In;
|
||||
"DB[12]" In;
|
||||
"DB[11]" In;
|
||||
"DB[10]" In;
|
||||
"DB[9]" In;
|
||||
"DB[8]" In;
|
||||
"DB[7]" In;
|
||||
"DB[6]" In;
|
||||
"DB[5]" In;
|
||||
"DB[4]" In;
|
||||
"DB[3]" In;
|
||||
"DB[2]" In;
|
||||
"DB[1]" In;
|
||||
"DB[0]" In;
|
||||
"EMAA[2]" In;
|
||||
"EMAA[1]" In;
|
||||
"EMAA[0]" In;
|
||||
"EMASA" In;
|
||||
"EMAB[2]" In;
|
||||
"EMAB[1]" In;
|
||||
"EMAB[0]" In;
|
||||
"TENA" In;
|
||||
"TCENA" In;
|
||||
"TAA[7]" In;
|
||||
"TAA[6]" In;
|
||||
"TAA[5]" In;
|
||||
"TAA[4]" In;
|
||||
"TAA[3]" In;
|
||||
"TAA[2]" In;
|
||||
"TAA[1]" In;
|
||||
"TAA[0]" In;
|
||||
"TENB" In;
|
||||
"TCENB" In;
|
||||
"TAB[7]" In;
|
||||
"TAB[6]" In;
|
||||
"TAB[5]" In;
|
||||
"TAB[4]" In;
|
||||
"TAB[3]" In;
|
||||
"TAB[2]" In;
|
||||
"TAB[1]" In;
|
||||
"TAB[0]" In;
|
||||
"TDB[18]" In;
|
||||
"TDB[17]" In;
|
||||
"TDB[16]" In;
|
||||
"TDB[15]" In;
|
||||
"TDB[14]" In;
|
||||
"TDB[13]" In;
|
||||
"TDB[12]" In;
|
||||
"TDB[11]" In;
|
||||
"TDB[10]" In;
|
||||
"TDB[9]" In;
|
||||
"TDB[8]" In;
|
||||
"TDB[7]" In;
|
||||
"TDB[6]" In;
|
||||
"TDB[5]" In;
|
||||
"TDB[4]" In;
|
||||
"TDB[3]" In;
|
||||
"TDB[2]" In;
|
||||
"TDB[1]" In;
|
||||
"TDB[0]" In;
|
||||
"RET1N" In;
|
||||
"SIA[1]" In;
|
||||
"SIA[0]" In;
|
||||
"SEA" In;
|
||||
"DFTRAMBYP" In;
|
||||
"SIB[1]" In;
|
||||
"SIB[0]" In;
|
||||
"SEB" In;
|
||||
"COLLDISN" In;
|
||||
}
|
||||
SignalGroups {
|
||||
"all_inputs" = '"CLKA" + "CENA" + "AA[7]" + "AA[6]" + "AA[5]" + "AA[4]" + "AA[3]" +
|
||||
"AA[2]" + "AA[1]" + "AA[0]" + "CLKB" + "CENB" + "AB[7]" + "AB[6]" + "AB[5]" +
|
||||
"AB[4]" + "AB[3]" + "AB[2]" + "AB[1]" + "AB[0]" + "DB[18]" + "DB[17]" + "DB[16]" +
|
||||
"DB[15]" + "DB[14]" + "DB[13]" + "DB[12]" + "DB[11]" + "DB[10]" + "DB[9]" + "DB[8]" +
|
||||
"DB[7]" + "DB[6]" + "DB[5]" + "DB[4]" + "DB[3]" + "DB[2]" + "DB[1]" + "DB[0]" +
|
||||
"EMAA[2]" + "EMAA[1]" + "EMAA[0]" + "EMASA" + "EMAB[2]" + "EMAB[1]" + "EMAB[0]" +
|
||||
"TENA" + "TCENA" + "TAA[7]" + "TAA[6]" + "TAA[5]" + "TAA[4]" + "TAA[3]" + "TAA[2]" +
|
||||
"TAA[1]" + "TAA[0]" + "TENB" + "TCENB" + "TAB[7]" + "TAB[6]" + "TAB[5]" + "TAB[4]" +
|
||||
"TAB[3]" + "TAB[2]" + "TAB[1]" + "TAB[0]" + "TDB[18]" + "TDB[17]" + "TDB[16]" +
|
||||
"TDB[15]" + "TDB[14]" + "TDB[13]" + "TDB[12]" + "TDB[11]" + "TDB[10]" + "TDB[9]" +
|
||||
"TDB[8]" + "TDB[7]" + "TDB[6]" + "TDB[5]" + "TDB[4]" + "TDB[3]" + "TDB[2]" + "TDB[1]" +
|
||||
"TDB[0]" + "RET1N" + "SIA[1]" + "SIA[0]" + "SEA" + "DFTRAMBYP" + "SIB[1]" + "SIB[0]" +
|
||||
"SEB" + "COLLDISN"';
|
||||
"all_outputs" = '"CENYA" + "AYA[7]" + "AYA[6]" + "AYA[5]" + "AYA[4]" + "AYA[3]" +
|
||||
"AYA[2]" + "AYA[1]" + "AYA[0]" + "CENYB" + "AYB[7]" + "AYB[6]" + "AYB[5]" + "AYB[4]" +
|
||||
"AYB[3]" + "AYB[2]" + "AYB[1]" + "AYB[0]" + "QA[18]" + "QA[17]" + "QA[16]" + "QA[15]" +
|
||||
"QA[14]" + "QA[13]" + "QA[12]" + "QA[11]" + "QA[10]" + "QA[9]" + "QA[8]" + "QA[7]" +
|
||||
"QA[6]" + "QA[5]" + "QA[4]" + "QA[3]" + "QA[2]" + "QA[1]" + "QA[0]" + "SOA[1]" +
|
||||
"SOA[0]" + "SOB[1]" + "SOB[0]"';
|
||||
"all_ports" = '"all_inputs" + "all_outputs"';
|
||||
"_pi" = '"CLKA" + "CENA" + "AA[7]" + "AA[6]" + "AA[5]" + "AA[4]" + "AA[3]" + "AA[2]" +
|
||||
"AA[1]" + "AA[0]" + "CLKB" + "CENB" + "AB[7]" + "AB[6]" + "AB[5]" + "AB[4]" +
|
||||
"AB[3]" + "AB[2]" + "AB[1]" + "AB[0]" + "DB[18]" + "DB[17]" + "DB[16]" + "DB[15]" +
|
||||
"DB[14]" + "DB[13]" + "DB[12]" + "DB[11]" + "DB[10]" + "DB[9]" + "DB[8]" + "DB[7]" +
|
||||
"DB[6]" + "DB[5]" + "DB[4]" + "DB[3]" + "DB[2]" + "DB[1]" + "DB[0]" + "EMAA[2]" +
|
||||
"EMAA[1]" + "EMAA[0]" + "EMASA" + "EMAB[2]" + "EMAB[1]" + "EMAB[0]" + "TENA" +
|
||||
"TCENA" + "TAA[7]" + "TAA[6]" + "TAA[5]" + "TAA[4]" + "TAA[3]" + "TAA[2]" + "TAA[1]" +
|
||||
"TAA[0]" + "TENB" + "TCENB" + "TAB[7]" + "TAB[6]" + "TAB[5]" + "TAB[4]" + "TAB[3]" +
|
||||
"TAB[2]" + "TAB[1]" + "TAB[0]" + "TDB[18]" + "TDB[17]" + "TDB[16]" + "TDB[15]" +
|
||||
"TDB[14]" + "TDB[13]" + "TDB[12]" + "TDB[11]" + "TDB[10]" + "TDB[9]" + "TDB[8]" +
|
||||
"TDB[7]" + "TDB[6]" + "TDB[5]" + "TDB[4]" + "TDB[3]" + "TDB[2]" + "TDB[1]" + "TDB[0]" +
|
||||
"RET1N" + "SIA[1]" + "SIA[0]" + "SEA" + "DFTRAMBYP" + "SIB[1]" + "SIB[0]" + "SEB" +
|
||||
"COLLDISN"';
|
||||
"_po" = '"CENYA" + "AYA[7]" + "AYA[6]" + "AYA[5]" + "AYA[4]" + "AYA[3]" + "AYA[2]" +
|
||||
"AYA[1]" + "AYA[0]" + "CENYB" + "AYB[7]" + "AYB[6]" + "AYB[5]" + "AYB[4]" + "AYB[3]" +
|
||||
"AYB[2]" + "AYB[1]" + "AYB[0]" + "QA[18]" + "QA[17]" + "QA[16]" + "QA[15]" + "QA[14]" +
|
||||
"QA[13]" + "QA[12]" + "QA[11]" + "QA[10]" + "QA[9]" + "QA[8]" + "QA[7]" + "QA[6]" +
|
||||
"QA[5]" + "QA[4]" + "QA[3]" + "QA[2]" + "QA[1]" + "QA[0]" + "SOA[1]" + "SOA[0]" +
|
||||
"SOB[1]" + "SOB[0]"';
|
||||
"_si" = '"SIA[0]" + "SIA[1]" + "SIB[0]" + "SIB[1]"' {ScanIn; }
|
||||
"_so" = '"SOA[0]" + "SOA[1]" + "SOB[0]" + "SOB[1]"' {ScanOut; }
|
||||
}
|
||||
ScanStructures {
|
||||
ScanChain "chain_rf2_256x19_wm0_1" {
|
||||
ScanLength 9;
|
||||
ScanCells "uDQA8" "uDQA7" "uDQA6" "uDQA5" "uDQA4" "uDQA3" "uDQA2" "uDQA1" "uDQA0" ;
|
||||
ScanIn "SIA[0]";
|
||||
ScanOut "SOA[0]";
|
||||
ScanEnable "SEA";
|
||||
ScanMasterClock "CLKA";
|
||||
}
|
||||
ScanChain "chain_rf2_256x19_wm0_2" {
|
||||
ScanLength 10;
|
||||
ScanCells "uDQA9" "uDQA10" "uDQA11" "uDQA12" "uDQA13" "uDQA14" "uDQA15" "uDQA16" "uDQA17" "uDQA18" ;
|
||||
ScanIn "SIA[1]";
|
||||
ScanOut "SOA[1]";
|
||||
ScanEnable "SEA";
|
||||
ScanMasterClock "CLKA";
|
||||
}
|
||||
ScanChain "chain_rf2_256x19_wm0_3" {
|
||||
ScanLength 9;
|
||||
ScanCells "uDQB8" "uDQB7" "uDQB6" "uDQB5" "uDQB4" "uDQB3" "uDQB2" "uDQB1" "uDQB0" ;
|
||||
ScanIn "SIB[0]";
|
||||
ScanOut "SOB[0]";
|
||||
ScanEnable "SEB";
|
||||
ScanMasterClock "CLKB";
|
||||
}
|
||||
ScanChain "chain_rf2_256x19_wm0_4" {
|
||||
ScanLength 10;
|
||||
ScanCells "uDQB9" "uDQB10" "uDQB11" "uDQB12" "uDQB13" "uDQB14" "uDQB15" "uDQB16" "uDQB17" "uDQB18" ;
|
||||
ScanIn "SIB[1]";
|
||||
ScanOut "SOB[1]";
|
||||
ScanEnable "SEB";
|
||||
ScanMasterClock "CLKB";
|
||||
}
|
||||
}
|
||||
Timing {
|
||||
WaveformTable "_default_WFT_" {
|
||||
Period '100ns';
|
||||
Waveforms {
|
||||
"all_inputs" {
|
||||
01ZN { '0ns' D/U/Z/N; }
|
||||
}
|
||||
"all_outputs" {
|
||||
XHTL { '40ns' X/H/T/L; }
|
||||
}
|
||||
"CLKA" {
|
||||
P { '0ns' D; '45ns' U; '55ns' D; }
|
||||
}
|
||||
"CLKB" {
|
||||
P { '0ns' D; '45ns' U; '55ns' D; }
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Procedures {
|
||||
"capture" {
|
||||
W "_default_WFT_";
|
||||
V { "_pi" = #; "_po" = #; }
|
||||
}
|
||||
"capture_CLK" {
|
||||
W "_default_WFT_";
|
||||
V {"_pi" = #; "_po" = #;"CLKA" = P;"CLKB" = P; }
|
||||
}
|
||||
"load_unload" {
|
||||
W "_default_WFT_";
|
||||
V { "CLKA" = 0; "CLKB" = 0; "_si" = \r2 N; "_so" =\r2 X; "SEA" = 1; "SEB" = 1; "DFTRAMBYP" = 1; }
|
||||
Shift {
|
||||
V { "CLKA" = P; "CLKB" = P; "_si" = \r2 #; "_so" = \r2 #; }
|
||||
}
|
||||
}
|
||||
}
|
||||
MacroDefs {
|
||||
"test_setup" {
|
||||
W "_default_WFT_";
|
||||
C {"all_inputs" = \r60 N; "all_outputs" = \r34 X; }
|
||||
V { "CLKA" = P; "CLKB" = P; }
|
||||
}
|
||||
}
|
||||
Environment "rf2_256x19_wm0" {
|
||||
CTL {
|
||||
}
|
||||
CTL Internal_scan {
|
||||
TestMode InternalTest;
|
||||
Focus Top {
|
||||
}
|
||||
Internal {
|
||||
"SIA[0]" {
|
||||
CaptureClock "CLKA" {
|
||||
LeadingEdge;
|
||||
}
|
||||
DataType ScanDataIn {
|
||||
ScanDataType Internal;
|
||||
}
|
||||
ScanStyle MultiplexedData;
|
||||
}
|
||||
"SIA[1]" {
|
||||
CaptureClock "CLKA" {
|
||||
LeadingEdge;
|
||||
}
|
||||
DataType ScanDataIn {
|
||||
ScanDataType Internal;
|
||||
}
|
||||
ScanStyle MultiplexedData;
|
||||
}
|
||||
"SOA[0]" {
|
||||
LaunchClock "CLKA" {
|
||||
LeadingEdge;
|
||||
}
|
||||
DataType ScanDataOut {
|
||||
ScanDataType Internal;
|
||||
}
|
||||
ScanStyle MultiplexedData;
|
||||
}
|
||||
"SOA[1]" {
|
||||
LaunchClock "CLKA" {
|
||||
LeadingEdge;
|
||||
}
|
||||
DataType ScanDataOut {
|
||||
ScanDataType Internal;
|
||||
}
|
||||
ScanStyle MultiplexedData;
|
||||
}
|
||||
"SEA" {
|
||||
DataType ScanEnable {
|
||||
ActiveState ForceUp;
|
||||
}
|
||||
}
|
||||
"CLKA" {
|
||||
DataType ScanMasterClock MasterClock;
|
||||
}
|
||||
"SIB[0]" {
|
||||
CaptureClock "CLKB" {
|
||||
LeadingEdge;
|
||||
}
|
||||
DataType ScanDataIn {
|
||||
ScanDataType Internal;
|
||||
}
|
||||
ScanStyle MultiplexedData;
|
||||
}
|
||||
"SIB[1]" {
|
||||
CaptureClock "CLKB" {
|
||||
LeadingEdge;
|
||||
}
|
||||
DataType ScanDataIn {
|
||||
ScanDataType Internal;
|
||||
}
|
||||
ScanStyle MultiplexedData;
|
||||
}
|
||||
"SOB[0]" {
|
||||
LaunchClock "CLKB" {
|
||||
LeadingEdge;
|
||||
}
|
||||
DataType ScanDataOut {
|
||||
ScanDataType Internal;
|
||||
}
|
||||
ScanStyle MultiplexedData;
|
||||
}
|
||||
"SOB[1]" {
|
||||
LaunchClock "CLKB" {
|
||||
LeadingEdge;
|
||||
}
|
||||
DataType ScanDataOut {
|
||||
ScanDataType Internal;
|
||||
}
|
||||
ScanStyle MultiplexedData;
|
||||
}
|
||||
"SEB" {
|
||||
DataType ScanEnable {
|
||||
ActiveState ForceUp;
|
||||
}
|
||||
}
|
||||
"CLKB" {
|
||||
DataType ScanMasterClock MasterClock;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Environment dftSpec {
|
||||
CTL {
|
||||
}
|
||||
CTL all_dft {
|
||||
TestMode ForInheritOnly;
|
||||
}
|
||||
}
|
||||
13070
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.lef
Normal file
13070
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.lef
Normal file
File diff suppressed because it is too large
Load Diff
687
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.mdt
Normal file
687
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.mdt
Normal file
@@ -0,0 +1,687 @@
|
||||
// fastscan_memcomp Version: 4.0.5-EAC10
|
||||
// common_memcomp Version: 4.0.5.2-amci
|
||||
// lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37
|
||||
//
|
||||
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
//
|
||||
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
//
|
||||
// Use of this Software is subject to the terms and conditions of the
|
||||
// applicable license agreement with ARM Physical IP, Inc.
|
||||
// In addition, this Software is protected by patents, copyright law
|
||||
// and international treaties.
|
||||
//
|
||||
// The copyright notice(s) in this Software does not indicate actual or
|
||||
// intended publication of this Software.
|
||||
//
|
||||
// Fastscan model for High Density Two Port Register File SVT MVT Compiler
|
||||
//
|
||||
// Instance Name: rf2_256x19_wm0
|
||||
// Words: 256
|
||||
// Bits: 19
|
||||
// Mux: 2
|
||||
// Drive: 6
|
||||
// Write Mask: Off
|
||||
// Write Thru: Off
|
||||
// Extra Margin Adjustment: On
|
||||
// Redundant Columns: 2
|
||||
// Test Muxes On
|
||||
// Power Gating: Off
|
||||
// Retention: On
|
||||
// Pipeline: Off
|
||||
// Read Disturb Test: Off
|
||||
//
|
||||
// Creation Date: Sun Oct 20 14:42:53 2019
|
||||
// Version: r4p0
|
||||
// Modeling Assumptions: This is Sequential Synchronous Mentor model
|
||||
// with Mentor ATPG primitives used to test UTI and generate test
|
||||
// vectors.
|
||||
//
|
||||
// Modeling Limitations: None.
|
||||
//
|
||||
// Known Bugs: None.
|
||||
//
|
||||
// Known Work Arounds: N/A
|
||||
//
|
||||
model rf2_256x19_wm0_scanflop (Q, SI, D, SE, CLK, Xout) (
|
||||
input (SI) ()
|
||||
input (D) ()
|
||||
input (SE) ()
|
||||
input (CLK) ()
|
||||
input (Xout) ()
|
||||
output (Q) (
|
||||
primitive = _tiex mx_tiex (mx);
|
||||
primitive = _tie0 m0_tie0 (m0_0);
|
||||
primitive = _tie0 m1_tie0 (m0_1);
|
||||
primitive = _mux m1 (D, SI, SE, n1);
|
||||
primitive = _mux m2 (n1, mx, Xout, n2);
|
||||
primitive = _dff r1 ( m0_0, m0_1, CLK, n2, Q, );
|
||||
)
|
||||
)
|
||||
model rf2_256x19_wm0_bitcell (CLK, WRITE, READ, WA, RA, D, Xout, Q) (
|
||||
intern (WA_ram, RA_ram) (array = 7:0;)
|
||||
input (CLK) ()
|
||||
intern (READ_ram) ()
|
||||
input (WRITE) ()
|
||||
input (READ) ()
|
||||
input (D) ()
|
||||
input (WA, RA) (array = 7:0;)
|
||||
input (Xout) ()
|
||||
output (Q) (
|
||||
|
||||
|
||||
primitive = _tiex mx_tiex ( mx );
|
||||
primitive = _mux WRITE_MUX ( WRITE, mx, Xout, WRITE_ram );
|
||||
primitive = _mux D_mux ( D, mx, Xout, D_ram );
|
||||
primitive = _mux AA0_mux ( WA[0], mx, Xout, WA_ram[0] );
|
||||
primitive = _mux AA1_mux ( WA[1], mx, Xout, WA_ram[1] );
|
||||
primitive = _mux AA2_mux ( WA[2], mx, Xout, WA_ram[2] );
|
||||
primitive = _mux AA3_mux ( WA[3], mx, Xout, WA_ram[3] );
|
||||
primitive = _mux AA4_mux ( WA[4], mx, Xout, WA_ram[4] );
|
||||
primitive = _mux AA5_mux ( WA[5], mx, Xout, WA_ram[5] );
|
||||
primitive = _mux AA6_mux ( WA[6], mx, Xout, WA_ram[6] );
|
||||
primitive = _mux AA7_mux ( WA[7], mx, Xout, WA_ram[7] );
|
||||
primitive = _mux READ_MUX ( READ, mx, Xout, READ_ram );
|
||||
primitive = _mux RA0_mux ( RA[0], mx, Xout, RA_ram[0] );
|
||||
primitive = _mux RA1_mux ( RA[1], mx, Xout, RA_ram[1] );
|
||||
primitive = _mux RA2_mux ( RA[2], mx, Xout, RA_ram[2] );
|
||||
primitive = _mux RA3_mux ( RA[3], mx, Xout, RA_ram[3] );
|
||||
primitive = _mux RA4_mux ( RA[4], mx, Xout, RA_ram[4] );
|
||||
primitive = _mux RA5_mux ( RA[5], mx, Xout, RA_ram[5] );
|
||||
primitive = _mux RA6_mux ( RA[6], mx, Xout, RA_ram[6] );
|
||||
primitive = _mux RA7_mux ( RA[7], mx, Xout, RA_ram[7] );
|
||||
data_size = 1;
|
||||
address_size = 8;
|
||||
min_address = 0;
|
||||
max_address = 255;
|
||||
edge_trigger = w;
|
||||
read_write_conflict = XW;
|
||||
// Verilog RAM has no Set or Reset pin :
|
||||
primitive = _cram mem ( , ,
|
||||
// Following write port will Hold in-memory data when not writing.
|
||||
_write { , , } (CLK, WRITE_ram, WA_ram, D_ram),
|
||||
// Following read port will Hold output data after reading.
|
||||
_read { , , ,} ( , READ_ram, , RA_ram, Q)
|
||||
);
|
||||
)
|
||||
)
|
||||
model rf2_256x19_wm0 (CENYA, AYA, CENYB, AYB, QA, SOA, SOB, CLKA, CENA, AA, CLKB, CENB,
|
||||
AB, DB, EMAA, EMASA, EMAB, TENA, TCENA, TAA, TENB, TCENB, TAB, TDB, RET1N, SIA,
|
||||
SEA, DFTRAMBYP, SIB, SEB, COLLDISN) (
|
||||
input (CLKA) ()
|
||||
input (CENA) ()
|
||||
input (AA) (array = 7 : 0; )
|
||||
input (CLKB) ()
|
||||
input (CENB) ()
|
||||
input (AB) (array = 7 : 0; )
|
||||
input (DB) (array = 18 : 0; )
|
||||
input (EMAA) (array = 2 : 0; used=false;fault=none;)
|
||||
input (EMASA) (used=false;fault=none;)
|
||||
input (EMAB) (array = 2 : 0; used=false;fault=none;)
|
||||
input (TENA) ()
|
||||
input (TCENA) ()
|
||||
input (TAA) (array = 7 : 0; )
|
||||
input (TENB) ()
|
||||
input (TCENB) ()
|
||||
input (TAB) (array = 7 : 0; )
|
||||
input (TDB) (array = 18 : 0; )
|
||||
input (RET1N) (used=false;fault=none;)
|
||||
input (SIA) (array = 1 : 0; )
|
||||
input (SEA) ()
|
||||
input (DFTRAMBYP) ()
|
||||
input (SIB) (array = 1 : 0; )
|
||||
input (SEB) ()
|
||||
input (COLLDISN) (used=false;fault=none;)
|
||||
intern (mtie_sel0) (primitive = _tie0 m0_sel0 ( mtie_sel0 );)
|
||||
intern (tiex_readq) (primitive = _tiex mtiex_readq(tiex_readq);)
|
||||
intern (mlc_bmuxsel) (primitive = _tie0 m0_bmuxsel ( mlc_bmuxsel );)
|
||||
intern (BUS_SIA) (array = 1 : 0;
|
||||
primitive = _buf wbSIA0 (SIA[0], BUS_SIA[0]);
|
||||
primitive = _buf wbSIA1 (SIA[1], BUS_SIA[1]);
|
||||
)
|
||||
intern (BUS_AA) (array = 7 : 0;
|
||||
primitive = _buf bBUS_AA0 ( AA[0], BUS_AA[0]);
|
||||
primitive = _buf bBUS_AA1 ( AA[1], BUS_AA[1]);
|
||||
primitive = _buf bBUS_AA2 ( AA[2], BUS_AA[2]);
|
||||
primitive = _buf bBUS_AA3 ( AA[3], BUS_AA[3]);
|
||||
primitive = _buf bBUS_AA4 ( AA[4], BUS_AA[4]);
|
||||
primitive = _buf bBUS_AA5 ( AA[5], BUS_AA[5]);
|
||||
primitive = _buf bBUS_AA6 ( AA[6], BUS_AA[6]);
|
||||
primitive = _buf bBUS_AA7 ( AA[7], BUS_AA[7]);
|
||||
)
|
||||
intern (BMUX_AA) ( array = 7 : 0;
|
||||
primitive = _mux maA0(TAA[0], BUS_AA[0], TENA, BMUX_AA[0]);
|
||||
primitive = _mux maA1(TAA[1], BUS_AA[1], TENA, BMUX_AA[1]);
|
||||
primitive = _mux maA2(TAA[2], BUS_AA[2], TENA, BMUX_AA[2]);
|
||||
primitive = _mux maA3(TAA[3], BUS_AA[3], TENA, BMUX_AA[3]);
|
||||
primitive = _mux maA4(TAA[4], BUS_AA[4], TENA, BMUX_AA[4]);
|
||||
primitive = _mux maA5(TAA[5], BUS_AA[5], TENA, BMUX_AA[5]);
|
||||
primitive = _mux maA6(TAA[6], BUS_AA[6], TENA, BMUX_AA[6]);
|
||||
primitive = _mux maA7(TAA[7], BUS_AA[7], TENA, BMUX_AA[7]);
|
||||
)
|
||||
intern (BMUXSEL_AA) ( array = 7 : 0;
|
||||
primitive = _mux mBMUXSEL_AA0(mlc_bmuxsel, BMUX_AA[0], DFTRAMBYP, BMUXSEL_AA[0]);
|
||||
primitive = _mux mBMUXSEL_AA1(mlc_bmuxsel, BMUX_AA[1], DFTRAMBYP, BMUXSEL_AA[1]);
|
||||
primitive = _mux mBMUXSEL_AA2(mlc_bmuxsel, BMUX_AA[2], DFTRAMBYP, BMUXSEL_AA[2]);
|
||||
primitive = _mux mBMUXSEL_AA3(mlc_bmuxsel, BMUX_AA[3], DFTRAMBYP, BMUXSEL_AA[3]);
|
||||
primitive = _mux mBMUXSEL_AA4(mlc_bmuxsel, BMUX_AA[4], DFTRAMBYP, BMUXSEL_AA[4]);
|
||||
primitive = _mux mBMUXSEL_AA5(mlc_bmuxsel, BMUX_AA[5], DFTRAMBYP, BMUXSEL_AA[5]);
|
||||
primitive = _mux mBMUXSEL_AA6(mlc_bmuxsel, BMUX_AA[6], DFTRAMBYP, BMUXSEL_AA[6]);
|
||||
primitive = _mux mBMUXSEL_AA7(mlc_bmuxsel, BMUX_AA[7], DFTRAMBYP, BMUXSEL_AA[7]);
|
||||
)
|
||||
output (AYA) ( array = 7 : 0;
|
||||
primitive = _buf bAYA0(BMUXSEL_AA[0], AYA[0]);
|
||||
primitive = _buf bAYA1(BMUXSEL_AA[1], AYA[1]);
|
||||
primitive = _buf bAYA2(BMUXSEL_AA[2], AYA[2]);
|
||||
primitive = _buf bAYA3(BMUXSEL_AA[3], AYA[3]);
|
||||
primitive = _buf bAYA4(BMUXSEL_AA[4], AYA[4]);
|
||||
primitive = _buf bAYA5(BMUXSEL_AA[5], AYA[5]);
|
||||
primitive = _buf bAYA6(BMUXSEL_AA[6], AYA[6]);
|
||||
primitive = _buf bAYA7(BMUXSEL_AA[7], AYA[7]);
|
||||
)
|
||||
|
||||
intern (BMUX_CENA) (primitive = _mux mBMUX_CENA(TCENA, CENA, TENA, BMUX_CENA);)
|
||||
intern (BMUXSEL_CENA) (primitive = _mux mBMUXSEL_CENA(mlc_bmuxsel, BMUX_CENA, DFTRAMBYP, BMUXSEL_CENA);)
|
||||
output (CENYA) (primitive = _buf bCENYA(BMUXSEL_CENA, CENYA);)
|
||||
intern (BMUX_AA_n) (array = 7 : 1;
|
||||
primitive = _inv iBMUX_AA_n1 ( BMUX_AA[1], BMUX_AA_n[1] );
|
||||
primitive = _inv iBMUX_AA_n2 ( BMUX_AA[2], BMUX_AA_n[2] );
|
||||
primitive = _inv iBMUX_AA_n3 ( BMUX_AA[3], BMUX_AA_n[3] );
|
||||
primitive = _inv iBMUX_AA_n4 ( BMUX_AA[4], BMUX_AA_n[4] );
|
||||
primitive = _inv iBMUX_AA_n5 ( BMUX_AA[5], BMUX_AA_n[5] );
|
||||
primitive = _inv iBMUX_AA_n6 ( BMUX_AA[6], BMUX_AA_n[6] );
|
||||
primitive = _inv iBMUX_AA_n7 ( BMUX_AA[7], BMUX_AA_n[7] );
|
||||
)
|
||||
|
||||
intern (A_max) (array = 7 : 0;
|
||||
primitive = _tie1 bA_max0 ( A_max[0] );
|
||||
primitive = _tie1 bA_max1 ( A_max[1] );
|
||||
primitive = _tie1 bA_max2 ( A_max[2] );
|
||||
primitive = _tie1 bA_max3 ( A_max[3] );
|
||||
primitive = _tie1 bA_max4 ( A_max[4] );
|
||||
primitive = _tie1 bA_max5 ( A_max[5] );
|
||||
primitive = _tie1 bA_max6 ( A_max[6] );
|
||||
primitive = _tie1 bA_max7 ( A_max[7] );
|
||||
)
|
||||
|
||||
intern (A_max_n) (array = 7 : 0;
|
||||
primitive = _inv bA_max_n0( A_max[0], A_max_n[0] );
|
||||
primitive = _inv bA_max_n1( A_max[1], A_max_n[1] );
|
||||
primitive = _inv bA_max_n2( A_max[2], A_max_n[2] );
|
||||
primitive = _inv bA_max_n3( A_max[3], A_max_n[3] );
|
||||
primitive = _inv bA_max_n4( A_max[4], A_max_n[4] );
|
||||
primitive = _inv bA_max_n5( A_max[5], A_max_n[5] );
|
||||
primitive = _inv bA_max_n6( A_max[6], A_max_n[6] );
|
||||
primitive = _inv bA_max_n7( A_max[7], A_max_n[7] );
|
||||
)
|
||||
|
||||
intern (AA_m) (array = 7 : 0;
|
||||
primitive = _and aAA_m0(BMUX_AA[0], A_max_n[0], AA_m[0] );
|
||||
primitive = _and aAA_m1(BMUX_AA[1], A_max_n[1], AA_m[1] );
|
||||
primitive = _and aAA_m2(BMUX_AA[2], A_max_n[2], AA_m[2] );
|
||||
primitive = _and aAA_m3(BMUX_AA[3], A_max_n[3], AA_m[3] );
|
||||
primitive = _and aAA_m4(BMUX_AA[4], A_max_n[4], AA_m[4] );
|
||||
primitive = _and aAA_m5(BMUX_AA[5], A_max_n[5], AA_m[5] );
|
||||
primitive = _and aAA_m6(BMUX_AA[6], A_max_n[6], AA_m[6] );
|
||||
primitive = _and aAA_m7(BMUX_AA[7], A_max_n[7], AA_m[7] );
|
||||
)
|
||||
|
||||
intern (m_AA) (array = 7 : 1;
|
||||
primitive = _and am_AA1(BMUX_AA_n[1], A_max[1], m_AA[1] );
|
||||
primitive = _and am_AA2(BMUX_AA_n[2], A_max[2], m_AA[2] );
|
||||
primitive = _and am_AA3(BMUX_AA_n[3], A_max[3], m_AA[3] );
|
||||
primitive = _and am_AA4(BMUX_AA_n[4], A_max[4], m_AA[4] );
|
||||
primitive = _and am_AA5(BMUX_AA_n[5], A_max[5], m_AA[5] );
|
||||
primitive = _and am_AA6(BMUX_AA_n[6], A_max[6], m_AA[6] );
|
||||
primitive = _and am_AA7(BMUX_AA_n[7], A_max[7], m_AA[7] );
|
||||
)
|
||||
|
||||
intern (EQ_A) (array = 7 : 1;
|
||||
primitive = _nor nEQ_A1(m_AA[1], AA_m[1], EQ_A[1] );
|
||||
primitive = _nor nEQ_A2(m_AA[2], AA_m[2], EQ_A[2] );
|
||||
primitive = _nor nEQ_A3(m_AA[3], AA_m[3], EQ_A[3] );
|
||||
primitive = _nor nEQ_A4(m_AA[4], AA_m[4], EQ_A[4] );
|
||||
primitive = _nor nEQ_A5(m_AA[5], AA_m[5], EQ_A[5] );
|
||||
primitive = _nor nEQ_A6(m_AA[6], AA_m[6], EQ_A[6] );
|
||||
primitive = _nor nEQ_A7(m_AA[7], AA_m[7], EQ_A[7] );
|
||||
)
|
||||
|
||||
intern (XoutAi) (array = 6 : 0;
|
||||
primitive = _and aXoutAi0(AA_m[0], EQ_A[7], EQ_A[6], EQ_A[5], EQ_A[4], EQ_A[3], EQ_A[2], EQ_A[1], XoutAi[0]);
|
||||
primitive = _and aXoutAi1(AA_m[1], EQ_A[7], EQ_A[6], EQ_A[5], EQ_A[4], EQ_A[3], EQ_A[2], XoutAi[1]);
|
||||
primitive = _and aXoutAi2(AA_m[2], EQ_A[7], EQ_A[6], EQ_A[5], EQ_A[4], EQ_A[3], XoutAi[2]);
|
||||
primitive = _and aXoutAi3(AA_m[3], EQ_A[7], EQ_A[6], EQ_A[5], EQ_A[4], XoutAi[3]);
|
||||
primitive = _and aXoutAi4(AA_m[4], EQ_A[7], EQ_A[6], EQ_A[5], XoutAi[4]);
|
||||
primitive = _and aXoutAi5(AA_m[5], EQ_A[7], EQ_A[6], XoutAi[5]);
|
||||
primitive = _and aXoutAi6(AA_m[6], EQ_A[7], XoutAi[6]);
|
||||
)
|
||||
intern (XoutAifTemp) (primitive = _or oXoutAifTemp (AA_m[7], XoutAi[0], XoutAi[1], XoutAi[2], XoutAi[3], XoutAi[4], XoutAi[5], XoutAi[6], XoutAifTemp);)
|
||||
intern (XoutAif) (primitive = _and oXoutAif (XoutAifTemp, NOT_CENA, XoutAif);)
|
||||
|
||||
intern (nscanshiftA) (
|
||||
primitive = _nor nnscanshiftA (DFTRAMBYP, SEA, nscanshiftA);)
|
||||
intern (XoutaddrA) (
|
||||
primitive = _and aXoutaddrA (nscanshiftA, XoutAif, XoutaddrA);)
|
||||
intern (XoutAiff) (
|
||||
primitive = _or oXoutAiff (XoutaddrA, XoutA, XoutAiff);)
|
||||
|
||||
intern (NOT_CENA) (primitive = _inv iNOT_CENA(BMUX_CENA, NOT_CENA);)
|
||||
intern (NOT_DFTRAMBYP) (primitive = _inv iNOT_DFTRAMBYP(DFTRAMBYP, NOT_DFTRAMBYP);)
|
||||
intern (READA) (array = 18:0;
|
||||
primitive = _buf bREADA0(NOT_CENA, READA[0]);
|
||||
primitive = _buf bREADA1(NOT_CENA, READA[1]);
|
||||
primitive = _buf bREADA2(NOT_CENA, READA[2]);
|
||||
primitive = _buf bREADA3(NOT_CENA, READA[3]);
|
||||
primitive = _buf bREADA4(NOT_CENA, READA[4]);
|
||||
primitive = _buf bREADA5(NOT_CENA, READA[5]);
|
||||
primitive = _buf bREADA6(NOT_CENA, READA[6]);
|
||||
primitive = _buf bREADA7(NOT_CENA, READA[7]);
|
||||
primitive = _buf bREADA8(NOT_CENA, READA[8]);
|
||||
primitive = _buf bREADA9(NOT_CENA, READA[9]);
|
||||
primitive = _buf bREADA10(NOT_CENA, READA[10]);
|
||||
primitive = _buf bREADA11(NOT_CENA, READA[11]);
|
||||
primitive = _buf bREADA12(NOT_CENA, READA[12]);
|
||||
primitive = _buf bREADA13(NOT_CENA, READA[13]);
|
||||
primitive = _buf bREADA14(NOT_CENA, READA[14]);
|
||||
primitive = _buf bREADA15(NOT_CENA, READA[15]);
|
||||
primitive = _buf bREADA16(NOT_CENA, READA[16]);
|
||||
primitive = _buf bREADA17(NOT_CENA, READA[17]);
|
||||
primitive = _buf bREADA18(NOT_CENA, READA[18]);
|
||||
)
|
||||
intern (x_detection_CENA) (primitive = _xor xx_detection_CENA(BMUX_CENA, BMUX_CENA, x_detection_CENA);)
|
||||
intern (x_detection_CLKA) (primitive = _xor xx_detection_CLKA(CLKA, CLKA, x_detection_CLKA);)
|
||||
intern (aSEA) (primitive = _and a1SEA ( SEA, DFTRAMBYPinv, aSEA );)
|
||||
intern (acendftA) (primitive = _and a1cendft[A] (x_detection_CENA, DFTRAMBYPinv, acendftA );)
|
||||
intern (acendftCA) (primitive = _and a1cendftCA ( x_detection_CLKA, DFTRAMBYPinv, acendftCA );)
|
||||
intern (XoutA) (primitive = _or oXoutA ( aSEA, acendftA, XoutA );)
|
||||
intern (READ_QA) (array = 18:0;
|
||||
primitive = _mux mREAD_QA0(QA[0], INT_QA[0], READA[0], READ_QA[0]);
|
||||
primitive = _mux mREAD_QA1(QA[1], INT_QA[1], READA[1], READ_QA[1]);
|
||||
primitive = _mux mREAD_QA2(QA[2], INT_QA[2], READA[2], READ_QA[2]);
|
||||
primitive = _mux mREAD_QA3(QA[3], INT_QA[3], READA[3], READ_QA[3]);
|
||||
primitive = _mux mREAD_QA4(QA[4], INT_QA[4], READA[4], READ_QA[4]);
|
||||
primitive = _mux mREAD_QA5(QA[5], INT_QA[5], READA[5], READ_QA[5]);
|
||||
primitive = _mux mREAD_QA6(QA[6], INT_QA[6], READA[6], READ_QA[6]);
|
||||
primitive = _mux mREAD_QA7(QA[7], INT_QA[7], READA[7], READ_QA[7]);
|
||||
primitive = _mux mREAD_QA8(QA[8], INT_QA[8], READA[8], READ_QA[8]);
|
||||
primitive = _mux mREAD_QA9(QA[9], INT_QA[9], READA[9], READ_QA[9]);
|
||||
primitive = _mux mREAD_QA10(QA[10], INT_QA[10], READA[10], READ_QA[10]);
|
||||
primitive = _mux mREAD_QA11(QA[11], INT_QA[11], READA[11], READ_QA[11]);
|
||||
primitive = _mux mREAD_QA12(QA[12], INT_QA[12], READA[12], READ_QA[12]);
|
||||
primitive = _mux mREAD_QA13(QA[13], INT_QA[13], READA[13], READ_QA[13]);
|
||||
primitive = _mux mREAD_QA14(QA[14], INT_QA[14], READA[14], READ_QA[14]);
|
||||
primitive = _mux mREAD_QA15(QA[15], INT_QA[15], READA[15], READ_QA[15]);
|
||||
primitive = _mux mREAD_QA16(QA[16], INT_QA[16], READA[16], READ_QA[16]);
|
||||
primitive = _mux mREAD_QA17(QA[17], INT_QA[17], READA[17], READ_QA[17]);
|
||||
primitive = _mux mREAD_QA18(QA[18], INT_QA[18], READA[18], READ_QA[18]);
|
||||
)
|
||||
intern (AAXOR) (array = 7 : 0;
|
||||
primitive = _xor xAAXOR0(BMUX_AA[0], BMUX_AA[0], AAXOR[0]);
|
||||
primitive = _xor xAAXOR1(BMUX_AA[1], BMUX_AA[1], AAXOR[1]);
|
||||
primitive = _xor xAAXOR2(BMUX_AA[2], BMUX_AA[2], AAXOR[2]);
|
||||
primitive = _xor xAAXOR3(BMUX_AA[3], BMUX_AA[3], AAXOR[3]);
|
||||
primitive = _xor xAAXOR4(BMUX_AA[4], BMUX_AA[4], AAXOR[4]);
|
||||
primitive = _xor xAAXOR5(BMUX_AA[5], BMUX_AA[5], AAXOR[5]);
|
||||
primitive = _xor xAAXOR6(BMUX_AA[6], BMUX_AA[6], AAXOR[6]);
|
||||
primitive = _xor xAAXOR7(BMUX_AA[7], BMUX_AA[7], AAXOR[7]);
|
||||
)
|
||||
intern (xA_addr_temp) (primitive = _or oxA_addr_temp( AAXOR[0], AAXOR[1], AAXOR[2], AAXOR[3], AAXOR[4], AAXOR[5], AAXOR[6], AAXOR[7], xA_addr_temp);)
|
||||
intern (xA_addr) (primitive = _and oxA_addr(NOT_CENA,xA_addr_temp,xA_addr);)
|
||||
intern (READ_QAX) (array = 18 : 0;
|
||||
primitive = _mux mREAD_QAX0 (READ_QA[0], tiex_readq, xA_addr, READ_QAX[0]);
|
||||
primitive = _mux mREAD_QAX1 (READ_QA[1], tiex_readq, xA_addr, READ_QAX[1]);
|
||||
primitive = _mux mREAD_QAX2 (READ_QA[2], tiex_readq, xA_addr, READ_QAX[2]);
|
||||
primitive = _mux mREAD_QAX3 (READ_QA[3], tiex_readq, xA_addr, READ_QAX[3]);
|
||||
primitive = _mux mREAD_QAX4 (READ_QA[4], tiex_readq, xA_addr, READ_QAX[4]);
|
||||
primitive = _mux mREAD_QAX5 (READ_QA[5], tiex_readq, xA_addr, READ_QAX[5]);
|
||||
primitive = _mux mREAD_QAX6 (READ_QA[6], tiex_readq, xA_addr, READ_QAX[6]);
|
||||
primitive = _mux mREAD_QAX7 (READ_QA[7], tiex_readq, xA_addr, READ_QAX[7]);
|
||||
primitive = _mux mREAD_QAX8 (READ_QA[8], tiex_readq, xA_addr, READ_QAX[8]);
|
||||
primitive = _mux mREAD_QAX9 (READ_QA[9], tiex_readq, xA_addr, READ_QAX[9]);
|
||||
primitive = _mux mREAD_QAX10 (READ_QA[10], tiex_readq, xA_addr, READ_QAX[10]);
|
||||
primitive = _mux mREAD_QAX11 (READ_QA[11], tiex_readq, xA_addr, READ_QAX[11]);
|
||||
primitive = _mux mREAD_QAX12 (READ_QA[12], tiex_readq, xA_addr, READ_QAX[12]);
|
||||
primitive = _mux mREAD_QAX13 (READ_QA[13], tiex_readq, xA_addr, READ_QAX[13]);
|
||||
primitive = _mux mREAD_QAX14 (READ_QA[14], tiex_readq, xA_addr, READ_QAX[14]);
|
||||
primitive = _mux mREAD_QAX15 (READ_QA[15], tiex_readq, xA_addr, READ_QAX[15]);
|
||||
primitive = _mux mREAD_QAX16 (READ_QA[16], tiex_readq, xA_addr, READ_QAX[16]);
|
||||
primitive = _mux mREAD_QAX17 (READ_QA[17], tiex_readq, xA_addr, READ_QAX[17]);
|
||||
primitive = _mux mREAD_QAX18 (READ_QA[18], tiex_readq, xA_addr, READ_QAX[18]);
|
||||
)
|
||||
intern (DA_scan) (array = 18 : 0;
|
||||
primitive = _mux mDA_scan0(READ_QAX[0], QA[1], DFTRAMBYP, DA_scan[0]);
|
||||
primitive = _mux mDA_scan1(READ_QAX[1], QA[2], DFTRAMBYP, DA_scan[1]);
|
||||
primitive = _mux mDA_scan2(READ_QAX[2], QA[3], DFTRAMBYP, DA_scan[2]);
|
||||
primitive = _mux mDA_scan3(READ_QAX[3], QA[4], DFTRAMBYP, DA_scan[3]);
|
||||
primitive = _mux mDA_scan4(READ_QAX[4], QA[5], DFTRAMBYP, DA_scan[4]);
|
||||
primitive = _mux mDA_scan5(READ_QAX[5], QA[6], DFTRAMBYP, DA_scan[5]);
|
||||
primitive = _mux mDA_scan6(READ_QAX[6], QA[7], DFTRAMBYP, DA_scan[6]);
|
||||
primitive = _mux mDA_scan7(READ_QAX[7], QA[8], DFTRAMBYP, DA_scan[7]);
|
||||
primitive = _mux mDA_scan8(READ_QAX[8], mtie_sel0, DFTRAMBYP, DA_scan[8]);
|
||||
primitive = _mux mDA_scan9(READ_QAX[9], mtie_sel0, DFTRAMBYP, DA_scan[9]);
|
||||
primitive = _mux mDA_scan10(READ_QAX[10], QA[9], DFTRAMBYP, DA_scan[10]);
|
||||
primitive = _mux mDA_scan11(READ_QAX[11], QA[10], DFTRAMBYP, DA_scan[11]);
|
||||
primitive = _mux mDA_scan12(READ_QAX[12], QA[11], DFTRAMBYP, DA_scan[12]);
|
||||
primitive = _mux mDA_scan13(READ_QAX[13], QA[12], DFTRAMBYP, DA_scan[13]);
|
||||
primitive = _mux mDA_scan14(READ_QAX[14], QA[13], DFTRAMBYP, DA_scan[14]);
|
||||
primitive = _mux mDA_scan15(READ_QAX[15], QA[14], DFTRAMBYP, DA_scan[15]);
|
||||
primitive = _mux mDA_scan16(READ_QAX[16], QA[15], DFTRAMBYP, DA_scan[16]);
|
||||
primitive = _mux mDA_scan17(READ_QAX[17], QA[16], DFTRAMBYP, DA_scan[17]);
|
||||
primitive = _mux mDA_scan18(READ_QAX[18], QA[17], DFTRAMBYP, DA_scan[18]);
|
||||
)
|
||||
output (QA) ( array = 18 : 0;
|
||||
instance = rf2_256x19_wm0_scanflop uDQA0 (.CLK(CLKA), .SE(SEA), .SI(QA[1]), .D(DA_scan[0]), .Q(QA[0]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA1 (.CLK(CLKA), .SE(SEA), .SI(QA[2]), .D(DA_scan[1]), .Q(QA[1]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA2 (.CLK(CLKA), .SE(SEA), .SI(QA[3]), .D(DA_scan[2]), .Q(QA[2]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA3 (.CLK(CLKA), .SE(SEA), .SI(QA[4]), .D(DA_scan[3]), .Q(QA[3]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA4 (.CLK(CLKA), .SE(SEA), .SI(QA[5]), .D(DA_scan[4]), .Q(QA[4]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA5 (.CLK(CLKA), .SE(SEA), .SI(QA[6]), .D(DA_scan[5]), .Q(QA[5]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA6 (.CLK(CLKA), .SE(SEA), .SI(QA[7]), .D(DA_scan[6]), .Q(QA[6]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA7 (.CLK(CLKA), .SE(SEA), .SI(QA[8]), .D(DA_scan[7]), .Q(QA[7]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA8 (.CLK(CLKA), .SE(SEA), .SI(BUS_SIA[0]), .D(DA_scan[8]), .Q(QA[8]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA9 (.CLK(CLKA), .SE(SEA), .SI(BUS_SIA[1]), .D(DA_scan[9]), .Q(QA[9]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA10 (.CLK(CLKA), .SE(SEA), .SI(QA[9]), .D(DA_scan[10]), .Q(QA[10]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA11 (.CLK(CLKA), .SE(SEA), .SI(QA[10]), .D(DA_scan[11]), .Q(QA[11]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA12 (.CLK(CLKA), .SE(SEA), .SI(QA[11]), .D(DA_scan[12]), .Q(QA[12]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA13 (.CLK(CLKA), .SE(SEA), .SI(QA[12]), .D(DA_scan[13]), .Q(QA[13]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA14 (.CLK(CLKA), .SE(SEA), .SI(QA[13]), .D(DA_scan[14]), .Q(QA[14]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA15 (.CLK(CLKA), .SE(SEA), .SI(QA[14]), .D(DA_scan[15]), .Q(QA[15]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA16 (.CLK(CLKA), .SE(SEA), .SI(QA[15]), .D(DA_scan[16]), .Q(QA[16]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA17 (.CLK(CLKA), .SE(SEA), .SI(QA[16]), .D(DA_scan[17]), .Q(QA[17]), .Xout(XoutAiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQA18 (.CLK(CLKA), .SE(SEA), .SI(QA[17]), .D(DA_scan[18]), .Q(QA[18]), .Xout(XoutAiff));
|
||||
)
|
||||
output (SOA) ( array = 1 : 0;
|
||||
primitive = _buf bSOA0 ( QA[0], SOA[0] );
|
||||
primitive = _buf bSOA1 ( QA[18], SOA[1] );
|
||||
)
|
||||
intern (BUS_SIB) (array = 1 : 0;
|
||||
primitive = _buf wbSIB0 (SIB[0], BUS_SIB[0]);
|
||||
primitive = _buf wbSIB1 (SIB[1], BUS_SIB[1]);
|
||||
)
|
||||
intern (BUS_AB) (array = 7 : 0;
|
||||
primitive = _buf bBUS_AB0 ( AB[0], BUS_AB[0]);
|
||||
primitive = _buf bBUS_AB1 ( AB[1], BUS_AB[1]);
|
||||
primitive = _buf bBUS_AB2 ( AB[2], BUS_AB[2]);
|
||||
primitive = _buf bBUS_AB3 ( AB[3], BUS_AB[3]);
|
||||
primitive = _buf bBUS_AB4 ( AB[4], BUS_AB[4]);
|
||||
primitive = _buf bBUS_AB5 ( AB[5], BUS_AB[5]);
|
||||
primitive = _buf bBUS_AB6 ( AB[6], BUS_AB[6]);
|
||||
primitive = _buf bBUS_AB7 ( AB[7], BUS_AB[7]);
|
||||
)
|
||||
intern (BUS_DB) (array = 18 : 0;
|
||||
primitive = _buf bBUS_DB0( DB[0], BUS_DB[0] );
|
||||
primitive = _buf bBUS_DB1( DB[1], BUS_DB[1] );
|
||||
primitive = _buf bBUS_DB2( DB[2], BUS_DB[2] );
|
||||
primitive = _buf bBUS_DB3( DB[3], BUS_DB[3] );
|
||||
primitive = _buf bBUS_DB4( DB[4], BUS_DB[4] );
|
||||
primitive = _buf bBUS_DB5( DB[5], BUS_DB[5] );
|
||||
primitive = _buf bBUS_DB6( DB[6], BUS_DB[6] );
|
||||
primitive = _buf bBUS_DB7( DB[7], BUS_DB[7] );
|
||||
primitive = _buf bBUS_DB8( DB[8], BUS_DB[8] );
|
||||
primitive = _buf bBUS_DB9( DB[9], BUS_DB[9] );
|
||||
primitive = _buf bBUS_DB10( DB[10], BUS_DB[10] );
|
||||
primitive = _buf bBUS_DB11( DB[11], BUS_DB[11] );
|
||||
primitive = _buf bBUS_DB12( DB[12], BUS_DB[12] );
|
||||
primitive = _buf bBUS_DB13( DB[13], BUS_DB[13] );
|
||||
primitive = _buf bBUS_DB14( DB[14], BUS_DB[14] );
|
||||
primitive = _buf bBUS_DB15( DB[15], BUS_DB[15] );
|
||||
primitive = _buf bBUS_DB16( DB[16], BUS_DB[16] );
|
||||
primitive = _buf bBUS_DB17( DB[17], BUS_DB[17] );
|
||||
primitive = _buf bBUS_DB18( DB[18], BUS_DB[18] );
|
||||
)
|
||||
intern (BMUX_AB) ( array = 7 : 0;
|
||||
primitive = _mux maB0(TAB[0], BUS_AB[0], TENB, BMUX_AB[0]);
|
||||
primitive = _mux maB1(TAB[1], BUS_AB[1], TENB, BMUX_AB[1]);
|
||||
primitive = _mux maB2(TAB[2], BUS_AB[2], TENB, BMUX_AB[2]);
|
||||
primitive = _mux maB3(TAB[3], BUS_AB[3], TENB, BMUX_AB[3]);
|
||||
primitive = _mux maB4(TAB[4], BUS_AB[4], TENB, BMUX_AB[4]);
|
||||
primitive = _mux maB5(TAB[5], BUS_AB[5], TENB, BMUX_AB[5]);
|
||||
primitive = _mux maB6(TAB[6], BUS_AB[6], TENB, BMUX_AB[6]);
|
||||
primitive = _mux maB7(TAB[7], BUS_AB[7], TENB, BMUX_AB[7]);
|
||||
)
|
||||
intern (BMUXSEL_AB) ( array = 7 : 0;
|
||||
primitive = _mux mBMUXSEL_AB0(mlc_bmuxsel, BMUX_AB[0], DFTRAMBYP, BMUXSEL_AB[0]);
|
||||
primitive = _mux mBMUXSEL_AB1(mlc_bmuxsel, BMUX_AB[1], DFTRAMBYP, BMUXSEL_AB[1]);
|
||||
primitive = _mux mBMUXSEL_AB2(mlc_bmuxsel, BMUX_AB[2], DFTRAMBYP, BMUXSEL_AB[2]);
|
||||
primitive = _mux mBMUXSEL_AB3(mlc_bmuxsel, BMUX_AB[3], DFTRAMBYP, BMUXSEL_AB[3]);
|
||||
primitive = _mux mBMUXSEL_AB4(mlc_bmuxsel, BMUX_AB[4], DFTRAMBYP, BMUXSEL_AB[4]);
|
||||
primitive = _mux mBMUXSEL_AB5(mlc_bmuxsel, BMUX_AB[5], DFTRAMBYP, BMUXSEL_AB[5]);
|
||||
primitive = _mux mBMUXSEL_AB6(mlc_bmuxsel, BMUX_AB[6], DFTRAMBYP, BMUXSEL_AB[6]);
|
||||
primitive = _mux mBMUXSEL_AB7(mlc_bmuxsel, BMUX_AB[7], DFTRAMBYP, BMUXSEL_AB[7]);
|
||||
)
|
||||
output (AYB) ( array = 7 : 0;
|
||||
primitive = _buf bAYB0(BMUXSEL_AB[0], AYB[0]);
|
||||
primitive = _buf bAYB1(BMUXSEL_AB[1], AYB[1]);
|
||||
primitive = _buf bAYB2(BMUXSEL_AB[2], AYB[2]);
|
||||
primitive = _buf bAYB3(BMUXSEL_AB[3], AYB[3]);
|
||||
primitive = _buf bAYB4(BMUXSEL_AB[4], AYB[4]);
|
||||
primitive = _buf bAYB5(BMUXSEL_AB[5], AYB[5]);
|
||||
primitive = _buf bAYB6(BMUXSEL_AB[6], AYB[6]);
|
||||
primitive = _buf bAYB7(BMUXSEL_AB[7], AYB[7]);
|
||||
)
|
||||
|
||||
intern (BMUX_DB) ( array = 18 : 0;
|
||||
primitive = _mux mBMUX_DB0(TDB[0], BUS_DB[0], TENB, BMUX_DB[0]);
|
||||
primitive = _mux mBMUX_DB1(TDB[1], BUS_DB[1], TENB, BMUX_DB[1]);
|
||||
primitive = _mux mBMUX_DB2(TDB[2], BUS_DB[2], TENB, BMUX_DB[2]);
|
||||
primitive = _mux mBMUX_DB3(TDB[3], BUS_DB[3], TENB, BMUX_DB[3]);
|
||||
primitive = _mux mBMUX_DB4(TDB[4], BUS_DB[4], TENB, BMUX_DB[4]);
|
||||
primitive = _mux mBMUX_DB5(TDB[5], BUS_DB[5], TENB, BMUX_DB[5]);
|
||||
primitive = _mux mBMUX_DB6(TDB[6], BUS_DB[6], TENB, BMUX_DB[6]);
|
||||
primitive = _mux mBMUX_DB7(TDB[7], BUS_DB[7], TENB, BMUX_DB[7]);
|
||||
primitive = _mux mBMUX_DB8(TDB[8], BUS_DB[8], TENB, BMUX_DB[8]);
|
||||
primitive = _mux mBMUX_DB9(TDB[9], BUS_DB[9], TENB, BMUX_DB[9]);
|
||||
primitive = _mux mBMUX_DB10(TDB[10], BUS_DB[10], TENB, BMUX_DB[10]);
|
||||
primitive = _mux mBMUX_DB11(TDB[11], BUS_DB[11], TENB, BMUX_DB[11]);
|
||||
primitive = _mux mBMUX_DB12(TDB[12], BUS_DB[12], TENB, BMUX_DB[12]);
|
||||
primitive = _mux mBMUX_DB13(TDB[13], BUS_DB[13], TENB, BMUX_DB[13]);
|
||||
primitive = _mux mBMUX_DB14(TDB[14], BUS_DB[14], TENB, BMUX_DB[14]);
|
||||
primitive = _mux mBMUX_DB15(TDB[15], BUS_DB[15], TENB, BMUX_DB[15]);
|
||||
primitive = _mux mBMUX_DB16(TDB[16], BUS_DB[16], TENB, BMUX_DB[16]);
|
||||
primitive = _mux mBMUX_DB17(TDB[17], BUS_DB[17], TENB, BMUX_DB[17]);
|
||||
primitive = _mux mBMUX_DB18(TDB[18], BUS_DB[18], TENB, BMUX_DB[18]);
|
||||
)
|
||||
|
||||
intern (BMUX_CENB) (primitive = _mux mBMUX_CENB(TCENB, CENB, TENB, BMUX_CENB);)
|
||||
intern (BMUXSEL_CENB) (primitive = _mux mBMUXSEL_CENB(mlc_bmuxsel, BMUX_CENB, DFTRAMBYP, BMUXSEL_CENB);)
|
||||
output (CENYB) (primitive = _buf bCENYB(BMUXSEL_CENB, CENYB);)
|
||||
intern (BMUX_AB_n) (array = 7 : 1;
|
||||
primitive = _inv iBMUX_AB_n1 ( BMUX_AB[1], BMUX_AB_n[1] );
|
||||
primitive = _inv iBMUX_AB_n2 ( BMUX_AB[2], BMUX_AB_n[2] );
|
||||
primitive = _inv iBMUX_AB_n3 ( BMUX_AB[3], BMUX_AB_n[3] );
|
||||
primitive = _inv iBMUX_AB_n4 ( BMUX_AB[4], BMUX_AB_n[4] );
|
||||
primitive = _inv iBMUX_AB_n5 ( BMUX_AB[5], BMUX_AB_n[5] );
|
||||
primitive = _inv iBMUX_AB_n6 ( BMUX_AB[6], BMUX_AB_n[6] );
|
||||
primitive = _inv iBMUX_AB_n7 ( BMUX_AB[7], BMUX_AB_n[7] );
|
||||
)
|
||||
|
||||
intern (B_max) (array = 7 : 0;
|
||||
primitive = _tie1 bB_max0 ( B_max[0] );
|
||||
primitive = _tie1 bB_max1 ( B_max[1] );
|
||||
primitive = _tie1 bB_max2 ( B_max[2] );
|
||||
primitive = _tie1 bB_max3 ( B_max[3] );
|
||||
primitive = _tie1 bB_max4 ( B_max[4] );
|
||||
primitive = _tie1 bB_max5 ( B_max[5] );
|
||||
primitive = _tie1 bB_max6 ( B_max[6] );
|
||||
primitive = _tie1 bB_max7 ( B_max[7] );
|
||||
)
|
||||
|
||||
intern (B_max_n) (array = 7 : 0;
|
||||
primitive = _inv bB_max_n0( B_max[0], B_max_n[0] );
|
||||
primitive = _inv bB_max_n1( B_max[1], B_max_n[1] );
|
||||
primitive = _inv bB_max_n2( B_max[2], B_max_n[2] );
|
||||
primitive = _inv bB_max_n3( B_max[3], B_max_n[3] );
|
||||
primitive = _inv bB_max_n4( B_max[4], B_max_n[4] );
|
||||
primitive = _inv bB_max_n5( B_max[5], B_max_n[5] );
|
||||
primitive = _inv bB_max_n6( B_max[6], B_max_n[6] );
|
||||
primitive = _inv bB_max_n7( B_max[7], B_max_n[7] );
|
||||
)
|
||||
|
||||
intern (AB_m) (array = 7 : 0;
|
||||
primitive = _and aAB_m0(BMUX_AB[0], B_max_n[0], AB_m[0] );
|
||||
primitive = _and aAB_m1(BMUX_AB[1], B_max_n[1], AB_m[1] );
|
||||
primitive = _and aAB_m2(BMUX_AB[2], B_max_n[2], AB_m[2] );
|
||||
primitive = _and aAB_m3(BMUX_AB[3], B_max_n[3], AB_m[3] );
|
||||
primitive = _and aAB_m4(BMUX_AB[4], B_max_n[4], AB_m[4] );
|
||||
primitive = _and aAB_m5(BMUX_AB[5], B_max_n[5], AB_m[5] );
|
||||
primitive = _and aAB_m6(BMUX_AB[6], B_max_n[6], AB_m[6] );
|
||||
primitive = _and aAB_m7(BMUX_AB[7], B_max_n[7], AB_m[7] );
|
||||
)
|
||||
|
||||
intern (m_AB) (array = 7 : 1;
|
||||
primitive = _and am_AB1(BMUX_AB_n[1], B_max[1], m_AB[1] );
|
||||
primitive = _and am_AB2(BMUX_AB_n[2], B_max[2], m_AB[2] );
|
||||
primitive = _and am_AB3(BMUX_AB_n[3], B_max[3], m_AB[3] );
|
||||
primitive = _and am_AB4(BMUX_AB_n[4], B_max[4], m_AB[4] );
|
||||
primitive = _and am_AB5(BMUX_AB_n[5], B_max[5], m_AB[5] );
|
||||
primitive = _and am_AB6(BMUX_AB_n[6], B_max[6], m_AB[6] );
|
||||
primitive = _and am_AB7(BMUX_AB_n[7], B_max[7], m_AB[7] );
|
||||
)
|
||||
|
||||
intern (EQ_B) (array = 7 : 1;
|
||||
primitive = _nor nEQ_B1(m_AB[1], AB_m[1], EQ_B[1] );
|
||||
primitive = _nor nEQ_B2(m_AB[2], AB_m[2], EQ_B[2] );
|
||||
primitive = _nor nEQ_B3(m_AB[3], AB_m[3], EQ_B[3] );
|
||||
primitive = _nor nEQ_B4(m_AB[4], AB_m[4], EQ_B[4] );
|
||||
primitive = _nor nEQ_B5(m_AB[5], AB_m[5], EQ_B[5] );
|
||||
primitive = _nor nEQ_B6(m_AB[6], AB_m[6], EQ_B[6] );
|
||||
primitive = _nor nEQ_B7(m_AB[7], AB_m[7], EQ_B[7] );
|
||||
)
|
||||
|
||||
intern (XoutBi) (array = 6 : 0;
|
||||
primitive = _and aXoutBi0(AB_m[0], EQ_B[7], EQ_B[6], EQ_B[5], EQ_B[4], EQ_B[3], EQ_B[2], EQ_B[1], XoutBi[0]);
|
||||
primitive = _and aXoutBi1(AB_m[1], EQ_B[7], EQ_B[6], EQ_B[5], EQ_B[4], EQ_B[3], EQ_B[2], XoutBi[1]);
|
||||
primitive = _and aXoutBi2(AB_m[2], EQ_B[7], EQ_B[6], EQ_B[5], EQ_B[4], EQ_B[3], XoutBi[2]);
|
||||
primitive = _and aXoutBi3(AB_m[3], EQ_B[7], EQ_B[6], EQ_B[5], EQ_B[4], XoutBi[3]);
|
||||
primitive = _and aXoutBi4(AB_m[4], EQ_B[7], EQ_B[6], EQ_B[5], XoutBi[4]);
|
||||
primitive = _and aXoutBi5(AB_m[5], EQ_B[7], EQ_B[6], XoutBi[5]);
|
||||
primitive = _and aXoutBi6(AB_m[6], EQ_B[7], XoutBi[6]);
|
||||
)
|
||||
intern (XoutBifTemp) (primitive = _or oXoutBifTemp (AB_m[7], XoutBi[0], XoutBi[1], XoutBi[2], XoutBi[3], XoutBi[4], XoutBi[5], XoutBi[6], XoutBifTemp);)
|
||||
intern (XoutBif) (primitive = _and oXoutBif (XoutBifTemp, NOT_CENB, XoutBif);)
|
||||
|
||||
intern (nscanshiftB) (
|
||||
primitive = _nor nnscanshiftB (DFTRAMBYP, SEB, nscanshiftB);)
|
||||
intern (XoutaddrB) (
|
||||
primitive = _and aXoutaddrB (nscanshiftB, XoutBif, XoutaddrB);)
|
||||
intern (XoutBiff) (
|
||||
primitive = _or oXoutBiff (XoutaddrB, XoutB, XoutBiff);)
|
||||
|
||||
intern (NOT_CENB) (primitive = _inv iNOT_CENB(BMUX_CENB, NOT_CENB);)
|
||||
intern (WRITEB) (array = 18 : 0;
|
||||
primitive = _and aWRITEB0(NOT_DFTRAMBYP, NOT_CENB, WRITEB[0]);
|
||||
primitive = _and aWRITEB1(NOT_DFTRAMBYP, NOT_CENB, WRITEB[1]);
|
||||
primitive = _and aWRITEB2(NOT_DFTRAMBYP, NOT_CENB, WRITEB[2]);
|
||||
primitive = _and aWRITEB3(NOT_DFTRAMBYP, NOT_CENB, WRITEB[3]);
|
||||
primitive = _and aWRITEB4(NOT_DFTRAMBYP, NOT_CENB, WRITEB[4]);
|
||||
primitive = _and aWRITEB5(NOT_DFTRAMBYP, NOT_CENB, WRITEB[5]);
|
||||
primitive = _and aWRITEB6(NOT_DFTRAMBYP, NOT_CENB, WRITEB[6]);
|
||||
primitive = _and aWRITEB7(NOT_DFTRAMBYP, NOT_CENB, WRITEB[7]);
|
||||
primitive = _and aWRITEB8(NOT_DFTRAMBYP, NOT_CENB, WRITEB[8]);
|
||||
primitive = _and aWRITEB9(NOT_DFTRAMBYP, NOT_CENB, WRITEB[9]);
|
||||
primitive = _and aWRITEB10(NOT_DFTRAMBYP, NOT_CENB, WRITEB[10]);
|
||||
primitive = _and aWRITEB11(NOT_DFTRAMBYP, NOT_CENB, WRITEB[11]);
|
||||
primitive = _and aWRITEB12(NOT_DFTRAMBYP, NOT_CENB, WRITEB[12]);
|
||||
primitive = _and aWRITEB13(NOT_DFTRAMBYP, NOT_CENB, WRITEB[13]);
|
||||
primitive = _and aWRITEB14(NOT_DFTRAMBYP, NOT_CENB, WRITEB[14]);
|
||||
primitive = _and aWRITEB15(NOT_DFTRAMBYP, NOT_CENB, WRITEB[15]);
|
||||
primitive = _and aWRITEB16(NOT_DFTRAMBYP, NOT_CENB, WRITEB[16]);
|
||||
primitive = _and aWRITEB17(NOT_DFTRAMBYP, NOT_CENB, WRITEB[17]);
|
||||
primitive = _and aWRITEB18(NOT_DFTRAMBYP, NOT_CENB, WRITEB[18]);
|
||||
)
|
||||
intern (INT_QA) (array = 18 : 0;
|
||||
instance = rf2_256x19_wm0_bitcell memB0 (.CLK(CLKB), .WRITE(WRITEB[0]), .READ(READA[0]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[0]), .Xout(XoutBiff), .Q(INT_QA[0]));
|
||||
instance = rf2_256x19_wm0_bitcell memB1 (.CLK(CLKB), .WRITE(WRITEB[1]), .READ(READA[1]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[1]), .Xout(XoutBiff), .Q(INT_QA[1]));
|
||||
instance = rf2_256x19_wm0_bitcell memB2 (.CLK(CLKB), .WRITE(WRITEB[2]), .READ(READA[2]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[2]), .Xout(XoutBiff), .Q(INT_QA[2]));
|
||||
instance = rf2_256x19_wm0_bitcell memB3 (.CLK(CLKB), .WRITE(WRITEB[3]), .READ(READA[3]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[3]), .Xout(XoutBiff), .Q(INT_QA[3]));
|
||||
instance = rf2_256x19_wm0_bitcell memB4 (.CLK(CLKB), .WRITE(WRITEB[4]), .READ(READA[4]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[4]), .Xout(XoutBiff), .Q(INT_QA[4]));
|
||||
instance = rf2_256x19_wm0_bitcell memB5 (.CLK(CLKB), .WRITE(WRITEB[5]), .READ(READA[5]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[5]), .Xout(XoutBiff), .Q(INT_QA[5]));
|
||||
instance = rf2_256x19_wm0_bitcell memB6 (.CLK(CLKB), .WRITE(WRITEB[6]), .READ(READA[6]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[6]), .Xout(XoutBiff), .Q(INT_QA[6]));
|
||||
instance = rf2_256x19_wm0_bitcell memB7 (.CLK(CLKB), .WRITE(WRITEB[7]), .READ(READA[7]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[7]), .Xout(XoutBiff), .Q(INT_QA[7]));
|
||||
instance = rf2_256x19_wm0_bitcell memB8 (.CLK(CLKB), .WRITE(WRITEB[8]), .READ(READA[8]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[8]), .Xout(XoutBiff), .Q(INT_QA[8]));
|
||||
instance = rf2_256x19_wm0_bitcell memB9 (.CLK(CLKB), .WRITE(WRITEB[9]), .READ(READA[9]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[9]), .Xout(XoutBiff), .Q(INT_QA[9]));
|
||||
instance = rf2_256x19_wm0_bitcell memB10 (.CLK(CLKB), .WRITE(WRITEB[10]), .READ(READA[10]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[10]), .Xout(XoutBiff), .Q(INT_QA[10]));
|
||||
instance = rf2_256x19_wm0_bitcell memB11 (.CLK(CLKB), .WRITE(WRITEB[11]), .READ(READA[11]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[11]), .Xout(XoutBiff), .Q(INT_QA[11]));
|
||||
instance = rf2_256x19_wm0_bitcell memB12 (.CLK(CLKB), .WRITE(WRITEB[12]), .READ(READA[12]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[12]), .Xout(XoutBiff), .Q(INT_QA[12]));
|
||||
instance = rf2_256x19_wm0_bitcell memB13 (.CLK(CLKB), .WRITE(WRITEB[13]), .READ(READA[13]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[13]), .Xout(XoutBiff), .Q(INT_QA[13]));
|
||||
instance = rf2_256x19_wm0_bitcell memB14 (.CLK(CLKB), .WRITE(WRITEB[14]), .READ(READA[14]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[14]), .Xout(XoutBiff), .Q(INT_QA[14]));
|
||||
instance = rf2_256x19_wm0_bitcell memB15 (.CLK(CLKB), .WRITE(WRITEB[15]), .READ(READA[15]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[15]), .Xout(XoutBiff), .Q(INT_QA[15]));
|
||||
instance = rf2_256x19_wm0_bitcell memB16 (.CLK(CLKB), .WRITE(WRITEB[16]), .READ(READA[16]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[16]), .Xout(XoutBiff), .Q(INT_QA[16]));
|
||||
instance = rf2_256x19_wm0_bitcell memB17 (.CLK(CLKB), .WRITE(WRITEB[17]), .READ(READA[17]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[17]), .Xout(XoutBiff), .Q(INT_QA[17]));
|
||||
instance = rf2_256x19_wm0_bitcell memB18 (.CLK(CLKB), .WRITE(WRITEB[18]), .READ(READA[18]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[18]), .Xout(XoutBiff), .Q(INT_QA[18]));
|
||||
)
|
||||
intern (x_detection_CENB) (primitive = _xor xx_detection_CENB(BMUX_CENB, BMUX_CENB, x_detection_CENB);)
|
||||
intern (x_detection_CLKB) (primitive = _xor xx_detection_CLKB(CLKB, CLKB, x_detection_CLKB);)
|
||||
intern (aSEB) (primitive = _and a1SEB ( SEB, DFTRAMBYPinv, aSEB );)
|
||||
intern (acendftB) (primitive = _and a1cendft[B] (x_detection_CENB, DFTRAMBYPinv, acendftB );)
|
||||
intern (acendftCB) (primitive = _and a1cendftCB ( x_detection_CLKB, DFTRAMBYPinv, acendftCB );)
|
||||
intern (XoutB) (primitive = _or oXoutB ( aSEB, acendftB, acendftCA, acendftCB, XoutB );)
|
||||
intern (DFTRAMBYPinv) (primitive = _inv imDFTRAMBYP ( DFTRAMBYP, DFTRAMBYPinv );)
|
||||
intern (DB_hold) (array = 18:0;
|
||||
primitive = _mux mDB_hold0 (BMUX_DB[0], QB_int[0], BMUX_CENB, DB_hold[0] );
|
||||
primitive = _mux mDB_hold1 (BMUX_DB[1], QB_int[1], BMUX_CENB, DB_hold[1] );
|
||||
primitive = _mux mDB_hold2 (BMUX_DB[2], QB_int[2], BMUX_CENB, DB_hold[2] );
|
||||
primitive = _mux mDB_hold3 (BMUX_DB[3], QB_int[3], BMUX_CENB, DB_hold[3] );
|
||||
primitive = _mux mDB_hold4 (BMUX_DB[4], QB_int[4], BMUX_CENB, DB_hold[4] );
|
||||
primitive = _mux mDB_hold5 (BMUX_DB[5], QB_int[5], BMUX_CENB, DB_hold[5] );
|
||||
primitive = _mux mDB_hold6 (BMUX_DB[6], QB_int[6], BMUX_CENB, DB_hold[6] );
|
||||
primitive = _mux mDB_hold7 (BMUX_DB[7], QB_int[7], BMUX_CENB, DB_hold[7] );
|
||||
primitive = _mux mDB_hold8 (BMUX_DB[8], QB_int[8], BMUX_CENB, DB_hold[8] );
|
||||
primitive = _mux mDB_hold9 (BMUX_DB[9], QB_int[9], BMUX_CENB, DB_hold[9] );
|
||||
primitive = _mux mDB_hold10 (BMUX_DB[10], QB_int[10], BMUX_CENB, DB_hold[10] );
|
||||
primitive = _mux mDB_hold11 (BMUX_DB[11], QB_int[11], BMUX_CENB, DB_hold[11] );
|
||||
primitive = _mux mDB_hold12 (BMUX_DB[12], QB_int[12], BMUX_CENB, DB_hold[12] );
|
||||
primitive = _mux mDB_hold13 (BMUX_DB[13], QB_int[13], BMUX_CENB, DB_hold[13] );
|
||||
primitive = _mux mDB_hold14 (BMUX_DB[14], QB_int[14], BMUX_CENB, DB_hold[14] );
|
||||
primitive = _mux mDB_hold15 (BMUX_DB[15], QB_int[15], BMUX_CENB, DB_hold[15] );
|
||||
primitive = _mux mDB_hold16 (BMUX_DB[16], QB_int[16], BMUX_CENB, DB_hold[16] );
|
||||
primitive = _mux mDB_hold17 (BMUX_DB[17], QB_int[17], BMUX_CENB, DB_hold[17] );
|
||||
primitive = _mux mDB_hold18 (BMUX_DB[18], QB_int[18], BMUX_CENB, DB_hold[18] );
|
||||
)
|
||||
intern (DB_scan) (array = 18:0;
|
||||
primitive = _mux mDB_scan0 (DB_hold[0], BMUX_DB[0], DFTRAMBYP, DB_scan[0] );
|
||||
primitive = _mux mDB_scan1 (DB_hold[1], BMUX_DB[1], DFTRAMBYP, DB_scan[1] );
|
||||
primitive = _mux mDB_scan2 (DB_hold[2], BMUX_DB[2], DFTRAMBYP, DB_scan[2] );
|
||||
primitive = _mux mDB_scan3 (DB_hold[3], BMUX_DB[3], DFTRAMBYP, DB_scan[3] );
|
||||
primitive = _mux mDB_scan4 (DB_hold[4], BMUX_DB[4], DFTRAMBYP, DB_scan[4] );
|
||||
primitive = _mux mDB_scan5 (DB_hold[5], BMUX_DB[5], DFTRAMBYP, DB_scan[5] );
|
||||
primitive = _mux mDB_scan6 (DB_hold[6], BMUX_DB[6], DFTRAMBYP, DB_scan[6] );
|
||||
primitive = _mux mDB_scan7 (DB_hold[7], BMUX_DB[7], DFTRAMBYP, DB_scan[7] );
|
||||
primitive = _mux mDB_scan8 (DB_hold[8], BMUX_DB[8], DFTRAMBYP, DB_scan[8] );
|
||||
primitive = _mux mDB_scan9 (DB_hold[9], BMUX_DB[9], DFTRAMBYP, DB_scan[9] );
|
||||
primitive = _mux mDB_scan10 (DB_hold[10], BMUX_DB[10], DFTRAMBYP, DB_scan[10] );
|
||||
primitive = _mux mDB_scan11 (DB_hold[11], BMUX_DB[11], DFTRAMBYP, DB_scan[11] );
|
||||
primitive = _mux mDB_scan12 (DB_hold[12], BMUX_DB[12], DFTRAMBYP, DB_scan[12] );
|
||||
primitive = _mux mDB_scan13 (DB_hold[13], BMUX_DB[13], DFTRAMBYP, DB_scan[13] );
|
||||
primitive = _mux mDB_scan14 (DB_hold[14], BMUX_DB[14], DFTRAMBYP, DB_scan[14] );
|
||||
primitive = _mux mDB_scan15 (DB_hold[15], BMUX_DB[15], DFTRAMBYP, DB_scan[15] );
|
||||
primitive = _mux mDB_scan16 (DB_hold[16], BMUX_DB[16], DFTRAMBYP, DB_scan[16] );
|
||||
primitive = _mux mDB_scan17 (DB_hold[17], BMUX_DB[17], DFTRAMBYP, DB_scan[17] );
|
||||
primitive = _mux mDB_scan18 (DB_hold[18], BMUX_DB[18], DFTRAMBYP, DB_scan[18] );
|
||||
)
|
||||
intern (QB_int) (array = 18 : 0;
|
||||
instance = rf2_256x19_wm0_scanflop uDQB0 (.CLK(CLKB), .SE(SEB), .SI(QB_int[1]), .D(DB_scan[0]), .Q(QB_int[0]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB1 (.CLK(CLKB), .SE(SEB), .SI(QB_int[2]), .D(DB_scan[1]), .Q(QB_int[1]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB2 (.CLK(CLKB), .SE(SEB), .SI(QB_int[3]), .D(DB_scan[2]), .Q(QB_int[2]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB3 (.CLK(CLKB), .SE(SEB), .SI(QB_int[4]), .D(DB_scan[3]), .Q(QB_int[3]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB4 (.CLK(CLKB), .SE(SEB), .SI(QB_int[5]), .D(DB_scan[4]), .Q(QB_int[4]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB5 (.CLK(CLKB), .SE(SEB), .SI(QB_int[6]), .D(DB_scan[5]), .Q(QB_int[5]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB6 (.CLK(CLKB), .SE(SEB), .SI(QB_int[7]), .D(DB_scan[6]), .Q(QB_int[6]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB7 (.CLK(CLKB), .SE(SEB), .SI(QB_int[8]), .D(DB_scan[7]), .Q(QB_int[7]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB8 (.CLK(CLKB), .SE(SEB), .SI(BUS_SIB[0]), .D(DB_scan[8]), .Q(QB_int[8]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB9 (.CLK(CLKB), .SE(SEB), .SI(BUS_SIB[1]), .D(DB_scan[9]), .Q(QB_int[9]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB10 (.CLK(CLKB), .SE(SEB), .SI(QB_int[9]), .D(DB_scan[10]), .Q(QB_int[10]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB11 (.CLK(CLKB), .SE(SEB), .SI(QB_int[10]), .D(DB_scan[11]), .Q(QB_int[11]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB12 (.CLK(CLKB), .SE(SEB), .SI(QB_int[11]), .D(DB_scan[12]), .Q(QB_int[12]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB13 (.CLK(CLKB), .SE(SEB), .SI(QB_int[12]), .D(DB_scan[13]), .Q(QB_int[13]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB14 (.CLK(CLKB), .SE(SEB), .SI(QB_int[13]), .D(DB_scan[14]), .Q(QB_int[14]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB15 (.CLK(CLKB), .SE(SEB), .SI(QB_int[14]), .D(DB_scan[15]), .Q(QB_int[15]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB16 (.CLK(CLKB), .SE(SEB), .SI(QB_int[15]), .D(DB_scan[16]), .Q(QB_int[16]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB17 (.CLK(CLKB), .SE(SEB), .SI(QB_int[16]), .D(DB_scan[17]), .Q(QB_int[17]), .Xout(XoutBiff));
|
||||
instance = rf2_256x19_wm0_scanflop uDQB18 (.CLK(CLKB), .SE(SEB), .SI(QB_int[17]), .D(DB_scan[18]), .Q(QB_int[18]), .Xout(XoutBiff));
|
||||
)
|
||||
output (SOB) ( array = 1 : 0;
|
||||
primitive = _buf bSOB0 (QB_int[0], SOB[0] );
|
||||
primitive = _buf bSOB1 (QB_int[18], SOB[1] );
|
||||
)
|
||||
)
|
||||
241
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.memlib
Normal file
241
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.memlib
Normal file
@@ -0,0 +1,241 @@
|
||||
/* logicvision_memcomp Version: c0.1.2-beta */
|
||||
/* common_memcomp Version: c0.1.0-EAC */
|
||||
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
|
||||
//
|
||||
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
//
|
||||
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
//
|
||||
// Use of this Software is subject to the terms and conditions of the
|
||||
// applicable license agreement with ARM Physical IP, Inc.
|
||||
// In addition, this Software is protected by patents, copyright law
|
||||
// and international treaties.
|
||||
//
|
||||
// The copyright notice(s) in this Software does not indicate actual or
|
||||
// intended publication of this Software.
|
||||
//
|
||||
// logicvision model for High Density Two Port Register File SVT MVT Compiler
|
||||
//
|
||||
// Instance Name: rf2_256x19_wm0
|
||||
// Words: 256
|
||||
// Bits: 19
|
||||
// Mux: 2
|
||||
// Drive: 6
|
||||
// Write Mask: Off
|
||||
// Extra Margin Adjustment: On
|
||||
// Redundant Rows: 0
|
||||
// Redundant Columns: 2
|
||||
// Test Muxes On
|
||||
//
|
||||
// Creation Date: Sun Oct 20 14:43:55 2019
|
||||
// Version: r4p0
|
||||
//
|
||||
// Modeling Assumptions:
|
||||
//
|
||||
// Modeling Limitations: None
|
||||
//
|
||||
// Known Bugs: None.
|
||||
//
|
||||
// Known Work Arounds: N/A
|
||||
//
|
||||
MemoryTemplate (rf2_256x19_wm0) {
|
||||
Algorithm : SmarchChkbvcd;
|
||||
DataOutStage : None;
|
||||
LogicalPorts : 1R1W;
|
||||
BitGrouping : 1;
|
||||
MemoryType : SRAM;
|
||||
MinHold : 0.5;
|
||||
OperationSet : SyncWRvcd;
|
||||
SelectDuringWriteThru : Off;
|
||||
ShadowRead : On;
|
||||
ShadowWrite : On;
|
||||
TransparentMode : None;
|
||||
ObservationLogic: On;
|
||||
InternalScanLogic: On;
|
||||
CellName : rf2_256x19_wm0;
|
||||
NumberOfWords : 256;
|
||||
AddressCounter{
|
||||
Function (Address) {
|
||||
LogicalAddressMap{
|
||||
ColumnAddress[0] : Address[0];
|
||||
RowAddress[6:0] : Address[7:1];
|
||||
}
|
||||
}
|
||||
Function (ColumnAddress) {
|
||||
CountRange [0:1];
|
||||
}
|
||||
Function (RowAddress) {
|
||||
CountRange [0:127];
|
||||
}
|
||||
}
|
||||
PhysicalAddressMap{
|
||||
ColumnAddress[0] : c[0];
|
||||
RowAddress[0] : r[0];
|
||||
RowAddress[1] : r[1];
|
||||
RowAddress[2] : r[2];
|
||||
RowAddress[3] : r[3];
|
||||
RowAddress[4] : r[4];
|
||||
RowAddress[5] : r[5];
|
||||
RowAddress[6] : r[6];
|
||||
}
|
||||
PhysicalDataMap{
|
||||
Data[0] : NOT d[0];
|
||||
Data[1] : NOT d[1];
|
||||
Data[2] : NOT d[2];
|
||||
Data[3] : NOT d[3];
|
||||
Data[4] : NOT d[4];
|
||||
Data[5] : NOT d[5];
|
||||
Data[6] : NOT d[6];
|
||||
Data[7] : NOT d[7];
|
||||
Data[8] : NOT d[8];
|
||||
Data[9] : d[9];
|
||||
Data[10] : d[10];
|
||||
Data[11] : d[11];
|
||||
Data[12] : d[12];
|
||||
Data[13] : d[13];
|
||||
Data[14] : d[14];
|
||||
Data[15] : d[15];
|
||||
Data[16] : d[16];
|
||||
Data[17] : d[17];
|
||||
Data[18] : d[18];
|
||||
}
|
||||
Port (AA[7:0]) {
|
||||
Function : Address;
|
||||
LogicalPort : A;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TAA[7:0];
|
||||
TestOutput : AYA[7:0];
|
||||
}
|
||||
}
|
||||
Port (QA[18:0]) {
|
||||
Function : Data;
|
||||
Direction : output;
|
||||
LogicalPort : A;
|
||||
}
|
||||
Port (CENA) {
|
||||
Function : ReadEnable;
|
||||
LogicalPort : A;
|
||||
Polarity : ActiveLow;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TCENA;
|
||||
TestOutput : CENYA;
|
||||
}
|
||||
}
|
||||
Port (TENA) {
|
||||
Function : BISTOn;
|
||||
Direction : Input;
|
||||
LogicalPort : A;
|
||||
Polarity : ActiveLow;
|
||||
}
|
||||
Port (CLKA) {
|
||||
Function : Clock;
|
||||
LogicalPort : A;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (EMAA[2:0]) {
|
||||
Function : None;
|
||||
SafeValue : 0;
|
||||
Direction : Input;
|
||||
LogicalPort : A;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (EMASA) {
|
||||
Function : None;
|
||||
SafeValue : 0;
|
||||
Direction : Input;
|
||||
LogicalPort : A;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SEA){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 0;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SIA[1:0]){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 0;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SOA[1:0]){
|
||||
Function : None;
|
||||
Direction : Output;
|
||||
}
|
||||
port (DFTRAMBYP){
|
||||
Function : ScanTest;
|
||||
Direction : Input;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (AB[7:0]) {
|
||||
Function : Address;
|
||||
LogicalPort : B;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TAB[7:0];
|
||||
TestOutput : AYB[7:0];
|
||||
}
|
||||
}
|
||||
Port (DB[18:0]) {
|
||||
Function : Data;
|
||||
Direction : input;
|
||||
LogicalPort : B;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TDB[18:0];
|
||||
}
|
||||
}
|
||||
Port (CENB) {
|
||||
Function : WriteEnable;
|
||||
LogicalPort : B;
|
||||
Polarity : ActiveLow;
|
||||
EmbeddedTestLogic {
|
||||
TestInput : TCENB;
|
||||
TestOutput : CENYB;
|
||||
}
|
||||
}
|
||||
Port (TENB) {
|
||||
Function : BISTOn;
|
||||
Direction : Input;
|
||||
LogicalPort : B;
|
||||
Polarity : ActiveLow;
|
||||
}
|
||||
Port (CLKB) {
|
||||
Function : Clock;
|
||||
LogicalPort : B;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (EMAB[2:0]) {
|
||||
Function : None;
|
||||
SafeValue : 0;
|
||||
Direction : Input;
|
||||
LogicalPort : B;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
Port (COLLDISN) {
|
||||
Function : None;
|
||||
SafeValue : 1;
|
||||
Direction : Input;
|
||||
Polarity : ActiveLow;
|
||||
}
|
||||
port (SEB){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 0;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SIB[1:0]){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 0;
|
||||
Polarity : ActiveHigh;
|
||||
}
|
||||
port (SOB[1:0]){
|
||||
Function : None;
|
||||
Direction : Output;
|
||||
}
|
||||
port (RET1N){
|
||||
Function : None;
|
||||
Direction : Input;
|
||||
SafeValue : 1;
|
||||
Polarity : Activelow;
|
||||
}
|
||||
}
|
||||
634
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.tv
Normal file
634
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.tv
Normal file
@@ -0,0 +1,634 @@
|
||||
/* tetramax_memcomp Version: 4.0.5-EAC3 */
|
||||
/* common_memcomp Version: 4.0.5.2-amci */
|
||||
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
|
||||
//
|
||||
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
//
|
||||
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
//
|
||||
// Use of this Software is subject to the terms and conditions of the
|
||||
// applicable license agreement with ARM Physical IP, Inc.
|
||||
// In addition, this Software is protected by patents, copyright law
|
||||
// and international treaties.
|
||||
//
|
||||
// The copyright notice(s) in this Software does not indicate actual or
|
||||
// intended publication of this Software.
|
||||
//
|
||||
// Tetramax model for High Density Two Port Register File SVT MVT Compiler
|
||||
//
|
||||
// Instance Name: rf2_256x19_wm0
|
||||
// Words: 256
|
||||
// Bits: 19
|
||||
// Mux: 2
|
||||
// Drive: 6
|
||||
// Write Mask: Off
|
||||
// Write Thru: Off
|
||||
// Extra Margin Adjustment: On
|
||||
// Redundant Columns: 2
|
||||
// Test Muxes On
|
||||
// Power Gating: Off
|
||||
// Retention: On
|
||||
// Pipeline: Off
|
||||
// Read Disturb Test: Off
|
||||
//
|
||||
// Creation Date: Sun Oct 20 14:44:19 2019
|
||||
// Version: r4p0
|
||||
//
|
||||
// Verified
|
||||
//
|
||||
// Modeling Assumptions:
|
||||
// This model is for use by only TetraMax ATPG tool.
|
||||
// It is not intended to be used by any Verilog Simulator.
|
||||
//
|
||||
// Modeling Limitations: These models have limited functionality as
|
||||
// defined by the TetraMax modelling guidelines. These models are
|
||||
// developed on Verilog syntax but they don't fully represent the
|
||||
// functionality of the memory model as they are restricted by
|
||||
// the ATPG tool. We have used fast sequential ATPG engine for verification
|
||||
// of all the memories on recommendation from Synopsys Tetramax expert.
|
||||
// The models have been tested by generating the ATPG vectors and simulating them
|
||||
// as well as running functional vectors through tetramax logical simulation engine.
|
||||
//
|
||||
// Known Bugs: None.
|
||||
//
|
||||
// Known Work Arounds: N/A
|
||||
//
|
||||
|
||||
|
||||
`timescale 1ns/1ps
|
||||
`define read_write readx
|
||||
`celldefine
|
||||
module rf2_256x19_wm0_scanflop (Q, SI, D, SE, CLK, Xout);
|
||||
output Q;
|
||||
input SI, D, SE, CLK, Xout;
|
||||
_MUX m1 (SE, D, SI, n1);
|
||||
_MUX m2 (Xout, n1, 1'bX, n2);
|
||||
_DFF r1 (1'b0, 1'b0, CLK, n2, Q);
|
||||
endmodule
|
||||
`endcelldefine
|
||||
`celldefine
|
||||
module rf2_256x19_wm0_bitcell (CLK, WRITE, WA, RA, D, Xout, Q);
|
||||
input CLK, WRITE, D, Xout;
|
||||
input [7:0] WA, RA;
|
||||
output Q;
|
||||
|
||||
reg Q;
|
||||
reg mem [255:0];
|
||||
wire WRITE_ram, D_ram;
|
||||
wire [7:0] WA_ram;
|
||||
|
||||
_MUX WRITE_MUX (Xout, WRITE, 1'bX, WRITE_ram);
|
||||
_MUX D_mux (Xout, D, 1'bX, D_ram);
|
||||
_MUX A0_mux (Xout, WA[0], 1'bX, WA_ram[0]);
|
||||
_MUX A1_mux (Xout, WA[1], 1'bX, WA_ram[1]);
|
||||
_MUX A2_mux (Xout, WA[2], 1'bX, WA_ram[2]);
|
||||
_MUX A3_mux (Xout, WA[3], 1'bX, WA_ram[3]);
|
||||
_MUX A4_mux (Xout, WA[4], 1'bX, WA_ram[4]);
|
||||
_MUX A5_mux (Xout, WA[5], 1'bX, WA_ram[5]);
|
||||
_MUX A6_mux (Xout, WA[6], 1'bX, WA_ram[6]);
|
||||
_MUX A7_mux (Xout, WA[7], 1'bX, WA_ram[7]);
|
||||
|
||||
event WRITE_OP;
|
||||
always @ (posedge CLK) if(WRITE_ram) begin
|
||||
mem[WA_ram]=D_ram;
|
||||
#0; -> WRITE_OP;
|
||||
end
|
||||
|
||||
wire TIE1;
|
||||
assign TIE1 = 1'b1;
|
||||
always @ (TIE1 or RA or WRITE_OP) if(TIE1) Q=mem[RA];
|
||||
endmodule
|
||||
`endcelldefine
|
||||
`suppress_faults
|
||||
`enable_portfaults
|
||||
`ifdef POWER_PINS
|
||||
module rf2_256x19_wm0 (VDDCE, VDDPE, VSSE, CENYA, AYA, CENYB, AYB, QA, SOA, SOB, CLKA,
|
||||
CENA, AA, CLKB, CENB, AB, DB, EMAA, EMASA, EMAB, TENA, TCENA, TAA, TENB, TCENB,
|
||||
TAB, TDB, RET1N, SIA, SEA, DFTRAMBYP, SIB, SEB, COLLDISN);
|
||||
`else
|
||||
module rf2_256x19_wm0 (CENYA, AYA, CENYB, AYB, QA, SOA, SOB, CLKA, CENA, AA, CLKB,
|
||||
CENB, AB, DB, EMAA, EMASA, EMAB, TENA, TCENA, TAA, TENB, TCENB, TAB, TDB, RET1N,
|
||||
SIA, SEA, DFTRAMBYP, SIB, SEB, COLLDISN);
|
||||
`endif
|
||||
|
||||
output CENYA;
|
||||
output [7:0] AYA;
|
||||
output CENYB;
|
||||
output [7:0] AYB;
|
||||
output [18:0] QA;
|
||||
output [1:0] SOA;
|
||||
output [1:0] SOB;
|
||||
input CLKA;
|
||||
input CENA;
|
||||
input [7:0] AA;
|
||||
input CLKB;
|
||||
input CENB;
|
||||
input [7:0] AB;
|
||||
input [18:0] DB;
|
||||
input [2:0] EMAA;
|
||||
input EMASA;
|
||||
input [2:0] EMAB;
|
||||
input TENA;
|
||||
input TCENA;
|
||||
input [7:0] TAA;
|
||||
input TENB;
|
||||
input TCENB;
|
||||
input [7:0] TAB;
|
||||
input [18:0] TDB;
|
||||
input RET1N;
|
||||
input [1:0] SIA;
|
||||
input SEA;
|
||||
input DFTRAMBYP;
|
||||
input [1:0] SIB;
|
||||
input SEB;
|
||||
input COLLDISN;
|
||||
`ifdef POWER_PINS
|
||||
inout VDDCE;
|
||||
inout VDDPE;
|
||||
inout VSSE;
|
||||
`endif
|
||||
wire [1:0] BUS_SIA;
|
||||
assign BUS_SIA[0] = SIA[0];
|
||||
assign BUS_SIA[1] = SIA[1];
|
||||
wire [7:0] BUS_AA;
|
||||
assign BUS_AA = AA;
|
||||
wire [7:0] BMUX_AA;
|
||||
wire [7:0] BMUXSEL_AA;
|
||||
wire BMUX_CENA;
|
||||
wire BMUXSEL_CENA;
|
||||
wire [18:0] INT_QA;
|
||||
wire [18:0] READ_QA;
|
||||
_MUX maA0 (TENA, TAA[0], BUS_AA[0], BMUX_AA[0]);
|
||||
_MUX maselA0 (DFTRAMBYP, 1'b0, BMUX_AA[0], BMUXSEL_AA[0]);
|
||||
buf bufmaA0(AYA[0],BMUXSEL_AA[0]);
|
||||
_MUX maA1 (TENA, TAA[1], BUS_AA[1], BMUX_AA[1]);
|
||||
_MUX maselA1 (DFTRAMBYP, 1'b0, BMUX_AA[1], BMUXSEL_AA[1]);
|
||||
buf bufmaA1(AYA[1],BMUXSEL_AA[1]);
|
||||
_MUX maA2 (TENA, TAA[2], BUS_AA[2], BMUX_AA[2]);
|
||||
_MUX maselA2 (DFTRAMBYP, 1'b0, BMUX_AA[2], BMUXSEL_AA[2]);
|
||||
buf bufmaA2(AYA[2],BMUXSEL_AA[2]);
|
||||
_MUX maA3 (TENA, TAA[3], BUS_AA[3], BMUX_AA[3]);
|
||||
_MUX maselA3 (DFTRAMBYP, 1'b0, BMUX_AA[3], BMUXSEL_AA[3]);
|
||||
buf bufmaA3(AYA[3],BMUXSEL_AA[3]);
|
||||
_MUX maA4 (TENA, TAA[4], BUS_AA[4], BMUX_AA[4]);
|
||||
_MUX maselA4 (DFTRAMBYP, 1'b0, BMUX_AA[4], BMUXSEL_AA[4]);
|
||||
buf bufmaA4(AYA[4],BMUXSEL_AA[4]);
|
||||
_MUX maA5 (TENA, TAA[5], BUS_AA[5], BMUX_AA[5]);
|
||||
_MUX maselA5 (DFTRAMBYP, 1'b0, BMUX_AA[5], BMUXSEL_AA[5]);
|
||||
buf bufmaA5(AYA[5],BMUXSEL_AA[5]);
|
||||
_MUX maA6 (TENA, TAA[6], BUS_AA[6], BMUX_AA[6]);
|
||||
_MUX maselA6 (DFTRAMBYP, 1'b0, BMUX_AA[6], BMUXSEL_AA[6]);
|
||||
buf bufmaA6(AYA[6],BMUXSEL_AA[6]);
|
||||
_MUX maA7 (TENA, TAA[7], BUS_AA[7], BMUX_AA[7]);
|
||||
_MUX maselA7 (DFTRAMBYP, 1'b0, BMUX_AA[7], BMUXSEL_AA[7]);
|
||||
buf bufmaA7(AYA[7],BMUXSEL_AA[7]);
|
||||
|
||||
_MUX mcenA (TENA, TCENA, CENA, BMUX_CENA);
|
||||
_MUX mcenselA (DFTRAMBYP, 1'b0,BMUX_CENA, BMUXSEL_CENA);
|
||||
buf bufmcenA (CENYA, BMUXSEL_CENA);
|
||||
wire [7:0] A_max, A_max_n, AA_m;
|
||||
wire XoutAif, XoutAiff;
|
||||
wire [7:1] BMUX_AA_n, EQ_A, m_AA;
|
||||
wire [6:0] XoutAi;
|
||||
not BMUX_AA1_n (BMUX_AA_n[1], BMUX_AA[1]);
|
||||
not BMUX_AA2_n (BMUX_AA_n[2], BMUX_AA[2]);
|
||||
not BMUX_AA3_n (BMUX_AA_n[3], BMUX_AA[3]);
|
||||
not BMUX_AA4_n (BMUX_AA_n[4], BMUX_AA[4]);
|
||||
not BMUX_AA5_n (BMUX_AA_n[5], BMUX_AA[5]);
|
||||
not BMUX_AA6_n (BMUX_AA_n[6], BMUX_AA[6]);
|
||||
not BMUX_AA7_n (BMUX_AA_n[7], BMUX_AA[7]);
|
||||
|
||||
assign A_max[0] = 1;
|
||||
assign A_max[1] = 1;
|
||||
assign A_max[2] = 1;
|
||||
assign A_max[3] = 1;
|
||||
assign A_max[4] = 1;
|
||||
assign A_max[5] = 1;
|
||||
assign A_max[6] = 1;
|
||||
assign A_max[7] = 1;
|
||||
|
||||
not Amax0_n (A_max_n[0], A_max[0]);
|
||||
not Amax1_n (A_max_n[1], A_max[1]);
|
||||
not Amax2_n (A_max_n[2], A_max[2]);
|
||||
not Amax3_n (A_max_n[3], A_max[3]);
|
||||
not Amax4_n (A_max_n[4], A_max[4]);
|
||||
not Amax5_n (A_max_n[5], A_max[5]);
|
||||
not Amax6_n (A_max_n[6], A_max[6]);
|
||||
not Amax7_n (A_max_n[7], A_max[7]);
|
||||
|
||||
and andBMUXAAAmax0 (AA_m[0], BMUX_AA[0], A_max_n[0]);
|
||||
and andBMUXAAAmax1 (AA_m[1], BMUX_AA[1], A_max_n[1]);
|
||||
and andBMUXAAAmax2 (AA_m[2], BMUX_AA[2], A_max_n[2]);
|
||||
and andBMUXAAAmax3 (AA_m[3], BMUX_AA[3], A_max_n[3]);
|
||||
and andBMUXAAAmax4 (AA_m[4], BMUX_AA[4], A_max_n[4]);
|
||||
and andBMUXAAAmax5 (AA_m[5], BMUX_AA[5], A_max_n[5]);
|
||||
and andBMUXAAAmax6 (AA_m[6], BMUX_AA[6], A_max_n[6]);
|
||||
and andBMUXAAAmax7 (AA_m[7], BMUX_AA[7], A_max_n[7]);
|
||||
|
||||
and andBMUXAAAmax1_n (m_AA[1], BMUX_AA_n[1], A_max[1]);
|
||||
and andBMUXAAAmax2_n (m_AA[2], BMUX_AA_n[2], A_max[2]);
|
||||
and andBMUXAAAmax3_n (m_AA[3], BMUX_AA_n[3], A_max[3]);
|
||||
and andBMUXAAAmax4_n (m_AA[4], BMUX_AA_n[4], A_max[4]);
|
||||
and andBMUXAAAmax5_n (m_AA[5], BMUX_AA_n[5], A_max[5]);
|
||||
and andBMUXAAAmax6_n (m_AA[6], BMUX_AA_n[6], A_max[6]);
|
||||
and andBMUXAAAmax7_n (m_AA[7], BMUX_AA_n[7], A_max[7]);
|
||||
|
||||
nor norAAAmax1 (EQ_A[1], m_AA[1], AA_m[1]);
|
||||
nor norAAAmax2 (EQ_A[2], m_AA[2], AA_m[2]);
|
||||
nor norAAAmax3 (EQ_A[3], m_AA[3], AA_m[3]);
|
||||
nor norAAAmax4 (EQ_A[4], m_AA[4], AA_m[4]);
|
||||
nor norAAAmax5 (EQ_A[5], m_AA[5], AA_m[5]);
|
||||
nor norAAAmax6 (EQ_A[6], m_AA[6], AA_m[6]);
|
||||
nor norAAAmax7 (EQ_A[7], m_AA[7], AA_m[7]);
|
||||
|
||||
and XfAAAmax0 (XoutAi[0], AA_m[0], EQ_A[7], EQ_A[6], EQ_A[5], EQ_A[4], EQ_A[3], EQ_A[2], EQ_A[1]);
|
||||
and XfAAAmax1 (XoutAi[1], AA_m[1], EQ_A[7], EQ_A[6], EQ_A[5], EQ_A[4], EQ_A[3], EQ_A[2]);
|
||||
and XfAAAmax2 (XoutAi[2], AA_m[2], EQ_A[7], EQ_A[6], EQ_A[5], EQ_A[4], EQ_A[3]);
|
||||
and XfAAAmax3 (XoutAi[3], AA_m[3], EQ_A[7], EQ_A[6], EQ_A[5], EQ_A[4]);
|
||||
and XfAAAmax4 (XoutAi[4], AA_m[4], EQ_A[7], EQ_A[6], EQ_A[5]);
|
||||
and XfAAAmax5 (XoutAi[5], AA_m[5], EQ_A[7], EQ_A[6]);
|
||||
and XfAAAmax6 (XoutAi[6], AA_m[6], EQ_A[7]);
|
||||
or orXfAAAmax7 (XoutAif, AA_m[7], XoutAi[0], XoutAi[1], XoutAi[2], XoutAi[3], XoutAi[4], XoutAi[5], XoutAi[6]);
|
||||
|
||||
wire [7:0] xDetectionAddrBusA;
|
||||
xor addrHandleA0 (xDetectionAddrBusA[0], BMUX_AA[0], BMUX_AA[0]);
|
||||
xor addrHandleA1 (xDetectionAddrBusA[1], BMUX_AA[1], BMUX_AA[1]);
|
||||
xor addrHandleA2 (xDetectionAddrBusA[2], BMUX_AA[2], BMUX_AA[2]);
|
||||
xor addrHandleA3 (xDetectionAddrBusA[3], BMUX_AA[3], BMUX_AA[3]);
|
||||
xor addrHandleA4 (xDetectionAddrBusA[4], BMUX_AA[4], BMUX_AA[4]);
|
||||
xor addrHandleA5 (xDetectionAddrBusA[5], BMUX_AA[5], BMUX_AA[5]);
|
||||
xor addrHandleA6 (xDetectionAddrBusA[6], BMUX_AA[6], BMUX_AA[6]);
|
||||
xor addrHandleA7 (xDetectionAddrBusA[7], BMUX_AA[7], BMUX_AA[7]);
|
||||
or addrFinalA (xAddrA,xDetectionAddrBusA[0],xDetectionAddrBusA[1],xDetectionAddrBusA[2],xDetectionAddrBusA[3],xDetectionAddrBusA[4],xDetectionAddrBusA[5],xDetectionAddrBusA[6],xDetectionAddrBusA[7]);
|
||||
or xBoundA (XoutAFinal, XoutAif, xAddrA);
|
||||
nor scanshiftA (nscanshiftA, DFTRAMBYP, SEA);
|
||||
and XoutaddrA (XoutaddrA, nscanshiftA, XoutAFinal);
|
||||
or XoutAFF0 (XoutAiff, XoutaddrA, XoutA);
|
||||
|
||||
wire NOT_CENA;
|
||||
not (NOT_CENA, BMUX_CENA);
|
||||
wire NOT_DFTRAMBYP;
|
||||
not (NOT_DFTRAMBYP, DFTRAMBYP);
|
||||
wire [18:0] READA;
|
||||
buf (READA[0], NOT_CENA);
|
||||
buf (READA[1], NOT_CENA);
|
||||
buf (READA[2], NOT_CENA);
|
||||
buf (READA[3], NOT_CENA);
|
||||
buf (READA[4], NOT_CENA);
|
||||
buf (READA[5], NOT_CENA);
|
||||
buf (READA[6], NOT_CENA);
|
||||
buf (READA[7], NOT_CENA);
|
||||
buf (READA[8], NOT_CENA);
|
||||
buf (READA[9], NOT_CENA);
|
||||
buf (READA[10], NOT_CENA);
|
||||
buf (READA[11], NOT_CENA);
|
||||
buf (READA[12], NOT_CENA);
|
||||
buf (READA[13], NOT_CENA);
|
||||
buf (READA[14], NOT_CENA);
|
||||
buf (READA[15], NOT_CENA);
|
||||
buf (READA[16], NOT_CENA);
|
||||
buf (READA[17], NOT_CENA);
|
||||
buf (READA[18], NOT_CENA);
|
||||
xor (x_detection_CENA, BMUX_CENA, BMUX_CENA);
|
||||
and (acendftA, x_detection_CENA, NOT_DFTRAMBYP);
|
||||
assign XoutA = (SEA & ~DFTRAMBYP) | acendftA;
|
||||
_MUX reA0 (READA[0], QA[0], INT_QA[0], READ_QA[0]);
|
||||
_MUX reA1 (READA[1], QA[1], INT_QA[1], READ_QA[1]);
|
||||
_MUX reA2 (READA[2], QA[2], INT_QA[2], READ_QA[2]);
|
||||
_MUX reA3 (READA[3], QA[3], INT_QA[3], READ_QA[3]);
|
||||
_MUX reA4 (READA[4], QA[4], INT_QA[4], READ_QA[4]);
|
||||
_MUX reA5 (READA[5], QA[5], INT_QA[5], READ_QA[5]);
|
||||
_MUX reA6 (READA[6], QA[6], INT_QA[6], READ_QA[6]);
|
||||
_MUX reA7 (READA[7], QA[7], INT_QA[7], READ_QA[7]);
|
||||
_MUX reA8 (READA[8], QA[8], INT_QA[8], READ_QA[8]);
|
||||
_MUX reA9 (READA[9], QA[9], INT_QA[9], READ_QA[9]);
|
||||
_MUX reA10 (READA[10], QA[10], INT_QA[10], READ_QA[10]);
|
||||
_MUX reA11 (READA[11], QA[11], INT_QA[11], READ_QA[11]);
|
||||
_MUX reA12 (READA[12], QA[12], INT_QA[12], READ_QA[12]);
|
||||
_MUX reA13 (READA[13], QA[13], INT_QA[13], READ_QA[13]);
|
||||
_MUX reA14 (READA[14], QA[14], INT_QA[14], READ_QA[14]);
|
||||
_MUX reA15 (READA[15], QA[15], INT_QA[15], READ_QA[15]);
|
||||
_MUX reA16 (READA[16], QA[16], INT_QA[16], READ_QA[16]);
|
||||
_MUX reA17 (READA[17], QA[17], INT_QA[17], READ_QA[17]);
|
||||
_MUX reA18 (READA[18], QA[18], INT_QA[18], READ_QA[18]);
|
||||
wire [7:0] AAXOR;
|
||||
xor (AAXOR[0], BMUX_AA[0], BMUX_AA[0]);
|
||||
xor (AAXOR[1], BMUX_AA[1], BMUX_AA[1]);
|
||||
xor (AAXOR[2], BMUX_AA[2], BMUX_AA[2]);
|
||||
xor (AAXOR[3], BMUX_AA[3], BMUX_AA[3]);
|
||||
xor (AAXOR[4], BMUX_AA[4], BMUX_AA[4]);
|
||||
xor (AAXOR[5], BMUX_AA[5], BMUX_AA[5]);
|
||||
xor (AAXOR[6], BMUX_AA[6], BMUX_AA[6]);
|
||||
xor (AAXOR[7], BMUX_AA[7], BMUX_AA[7]);
|
||||
wire xA_addr;
|
||||
or (xA_addr, AAXOR[0], AAXOR[1], AAXOR[2], AAXOR[3], AAXOR[4], AAXOR[5], AAXOR[6], AAXOR[7]);
|
||||
_MUX rxA0 (xA_addr, READ_QA[0], 1'bX, READ_QAX[0]);
|
||||
_MUX rxA1 (xA_addr, READ_QA[1], 1'bX, READ_QAX[1]);
|
||||
_MUX rxA2 (xA_addr, READ_QA[2], 1'bX, READ_QAX[2]);
|
||||
_MUX rxA3 (xA_addr, READ_QA[3], 1'bX, READ_QAX[3]);
|
||||
_MUX rxA4 (xA_addr, READ_QA[4], 1'bX, READ_QAX[4]);
|
||||
_MUX rxA5 (xA_addr, READ_QA[5], 1'bX, READ_QAX[5]);
|
||||
_MUX rxA6 (xA_addr, READ_QA[6], 1'bX, READ_QAX[6]);
|
||||
_MUX rxA7 (xA_addr, READ_QA[7], 1'bX, READ_QAX[7]);
|
||||
_MUX rxA8 (xA_addr, READ_QA[8], 1'bX, READ_QAX[8]);
|
||||
_MUX rxA9 (xA_addr, READ_QA[9], 1'bX, READ_QAX[9]);
|
||||
_MUX rxA10 (xA_addr, READ_QA[10], 1'bX, READ_QAX[10]);
|
||||
_MUX rxA11 (xA_addr, READ_QA[11], 1'bX, READ_QAX[11]);
|
||||
_MUX rxA12 (xA_addr, READ_QA[12], 1'bX, READ_QAX[12]);
|
||||
_MUX rxA13 (xA_addr, READ_QA[13], 1'bX, READ_QAX[13]);
|
||||
_MUX rxA14 (xA_addr, READ_QA[14], 1'bX, READ_QAX[14]);
|
||||
_MUX rxA15 (xA_addr, READ_QA[15], 1'bX, READ_QAX[15]);
|
||||
_MUX rxA16 (xA_addr, READ_QA[16], 1'bX, READ_QAX[16]);
|
||||
_MUX rxA17 (xA_addr, READ_QA[17], 1'bX, READ_QAX[17]);
|
||||
_MUX rxA18 (xA_addr, READ_QA[18], 1'bX, READ_QAX[18]);
|
||||
_MUX mqA0 (DFTRAMBYP, READ_QAX[0], QA[1], DA_scan[0]);
|
||||
_MUX mqA1 (DFTRAMBYP, READ_QAX[1], QA[2], DA_scan[1]);
|
||||
_MUX mqA2 (DFTRAMBYP, READ_QAX[2], QA[3], DA_scan[2]);
|
||||
_MUX mqA3 (DFTRAMBYP, READ_QAX[3], QA[4], DA_scan[3]);
|
||||
_MUX mqA4 (DFTRAMBYP, READ_QAX[4], QA[5], DA_scan[4]);
|
||||
_MUX mqA5 (DFTRAMBYP, READ_QAX[5], QA[6], DA_scan[5]);
|
||||
_MUX mqA6 (DFTRAMBYP, READ_QAX[6], QA[7], DA_scan[6]);
|
||||
_MUX mqA7 (DFTRAMBYP, READ_QAX[7], QA[8], DA_scan[7]);
|
||||
_MUX mqA8 (DFTRAMBYP, READ_QAX[8], 1'b0, DA_scan[8]);
|
||||
_MUX mqA9 (DFTRAMBYP, READ_QAX[9], 1'b0, DA_scan[9]);
|
||||
_MUX mqA10 (DFTRAMBYP, READ_QAX[10], QA[9], DA_scan[10]);
|
||||
_MUX mqA11 (DFTRAMBYP, READ_QAX[11], QA[10], DA_scan[11]);
|
||||
_MUX mqA12 (DFTRAMBYP, READ_QAX[12], QA[11], DA_scan[12]);
|
||||
_MUX mqA13 (DFTRAMBYP, READ_QAX[13], QA[12], DA_scan[13]);
|
||||
_MUX mqA14 (DFTRAMBYP, READ_QAX[14], QA[13], DA_scan[14]);
|
||||
_MUX mqA15 (DFTRAMBYP, READ_QAX[15], QA[14], DA_scan[15]);
|
||||
_MUX mqA16 (DFTRAMBYP, READ_QAX[16], QA[15], DA_scan[16]);
|
||||
_MUX mqA17 (DFTRAMBYP, READ_QAX[17], QA[16], DA_scan[17]);
|
||||
_MUX mqA18 (DFTRAMBYP, READ_QAX[18], QA[17], DA_scan[18]);
|
||||
rf2_256x19_wm0_scanflop uDQA0 (.CLK(CLKA), .SE(SEA), .SI(QA[1]), .D(DA_scan[0]), .Q(QA[0]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA1 (.CLK(CLKA), .SE(SEA), .SI(QA[2]), .D(DA_scan[1]), .Q(QA[1]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA2 (.CLK(CLKA), .SE(SEA), .SI(QA[3]), .D(DA_scan[2]), .Q(QA[2]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA3 (.CLK(CLKA), .SE(SEA), .SI(QA[4]), .D(DA_scan[3]), .Q(QA[3]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA4 (.CLK(CLKA), .SE(SEA), .SI(QA[5]), .D(DA_scan[4]), .Q(QA[4]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA5 (.CLK(CLKA), .SE(SEA), .SI(QA[6]), .D(DA_scan[5]), .Q(QA[5]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA6 (.CLK(CLKA), .SE(SEA), .SI(QA[7]), .D(DA_scan[6]), .Q(QA[6]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA7 (.CLK(CLKA), .SE(SEA), .SI(QA[8]), .D(DA_scan[7]), .Q(QA[7]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA8 (.CLK(CLKA), .SE(SEA), .SI(BUS_SIA[0]), .D(DA_scan[8]), .Q(QA[8]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA9 (.CLK(CLKA), .SE(SEA), .SI(BUS_SIA[1]), .D(DA_scan[9]), .Q(QA[9]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA10 (.CLK(CLKA), .SE(SEA), .SI(QA[9]), .D(DA_scan[10]), .Q(QA[10]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA11 (.CLK(CLKA), .SE(SEA), .SI(QA[10]), .D(DA_scan[11]), .Q(QA[11]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA12 (.CLK(CLKA), .SE(SEA), .SI(QA[11]), .D(DA_scan[12]), .Q(QA[12]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA13 (.CLK(CLKA), .SE(SEA), .SI(QA[12]), .D(DA_scan[13]), .Q(QA[13]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA14 (.CLK(CLKA), .SE(SEA), .SI(QA[13]), .D(DA_scan[14]), .Q(QA[14]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA15 (.CLK(CLKA), .SE(SEA), .SI(QA[14]), .D(DA_scan[15]), .Q(QA[15]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA16 (.CLK(CLKA), .SE(SEA), .SI(QA[15]), .D(DA_scan[16]), .Q(QA[16]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA17 (.CLK(CLKA), .SE(SEA), .SI(QA[16]), .D(DA_scan[17]), .Q(QA[17]), .Xout(XoutAiff));
|
||||
rf2_256x19_wm0_scanflop uDQA18 (.CLK(CLKA), .SE(SEA), .SI(QA[17]), .D(DA_scan[18]), .Q(QA[18]), .Xout(XoutAiff));
|
||||
assign SOA[0] = QA[0];
|
||||
assign SOA[1] = QA[18];
|
||||
wire [1:0] BUS_SIB;
|
||||
assign BUS_SIB[0] = SIB[0];
|
||||
assign BUS_SIB[1] = SIB[1];
|
||||
wire [7:0] BUS_AB;
|
||||
assign BUS_AB = AB;
|
||||
wire [18:0] BUS_DB;
|
||||
assign BUS_DB = DB;
|
||||
wire [18:0] DB_scan;
|
||||
wire [7:0] BMUX_AB;
|
||||
wire [7:0] BMUXSEL_AB;
|
||||
wire [18:0] BMUX_DB;
|
||||
wire BMUX_CENB;
|
||||
wire BMUXSEL_CENB;
|
||||
_MUX maB0 (TENB, TAB[0], BUS_AB[0], BMUX_AB[0]);
|
||||
_MUX maselB0 (DFTRAMBYP, 1'b0, BMUX_AB[0], BMUXSEL_AB[0]);
|
||||
buf bufmaB0(AYB[0],BMUXSEL_AB[0]);
|
||||
_MUX maB1 (TENB, TAB[1], BUS_AB[1], BMUX_AB[1]);
|
||||
_MUX maselB1 (DFTRAMBYP, 1'b0, BMUX_AB[1], BMUXSEL_AB[1]);
|
||||
buf bufmaB1(AYB[1],BMUXSEL_AB[1]);
|
||||
_MUX maB2 (TENB, TAB[2], BUS_AB[2], BMUX_AB[2]);
|
||||
_MUX maselB2 (DFTRAMBYP, 1'b0, BMUX_AB[2], BMUXSEL_AB[2]);
|
||||
buf bufmaB2(AYB[2],BMUXSEL_AB[2]);
|
||||
_MUX maB3 (TENB, TAB[3], BUS_AB[3], BMUX_AB[3]);
|
||||
_MUX maselB3 (DFTRAMBYP, 1'b0, BMUX_AB[3], BMUXSEL_AB[3]);
|
||||
buf bufmaB3(AYB[3],BMUXSEL_AB[3]);
|
||||
_MUX maB4 (TENB, TAB[4], BUS_AB[4], BMUX_AB[4]);
|
||||
_MUX maselB4 (DFTRAMBYP, 1'b0, BMUX_AB[4], BMUXSEL_AB[4]);
|
||||
buf bufmaB4(AYB[4],BMUXSEL_AB[4]);
|
||||
_MUX maB5 (TENB, TAB[5], BUS_AB[5], BMUX_AB[5]);
|
||||
_MUX maselB5 (DFTRAMBYP, 1'b0, BMUX_AB[5], BMUXSEL_AB[5]);
|
||||
buf bufmaB5(AYB[5],BMUXSEL_AB[5]);
|
||||
_MUX maB6 (TENB, TAB[6], BUS_AB[6], BMUX_AB[6]);
|
||||
_MUX maselB6 (DFTRAMBYP, 1'b0, BMUX_AB[6], BMUXSEL_AB[6]);
|
||||
buf bufmaB6(AYB[6],BMUXSEL_AB[6]);
|
||||
_MUX maB7 (TENB, TAB[7], BUS_AB[7], BMUX_AB[7]);
|
||||
_MUX maselB7 (DFTRAMBYP, 1'b0, BMUX_AB[7], BMUXSEL_AB[7]);
|
||||
buf bufmaB7(AYB[7],BMUXSEL_AB[7]);
|
||||
|
||||
_MUX mdB0 (TENB, TDB[0], BUS_DB[0], BMUX_DB[0]);
|
||||
_MUX mdB1 (TENB, TDB[1], BUS_DB[1], BMUX_DB[1]);
|
||||
_MUX mdB2 (TENB, TDB[2], BUS_DB[2], BMUX_DB[2]);
|
||||
_MUX mdB3 (TENB, TDB[3], BUS_DB[3], BMUX_DB[3]);
|
||||
_MUX mdB4 (TENB, TDB[4], BUS_DB[4], BMUX_DB[4]);
|
||||
_MUX mdB5 (TENB, TDB[5], BUS_DB[5], BMUX_DB[5]);
|
||||
_MUX mdB6 (TENB, TDB[6], BUS_DB[6], BMUX_DB[6]);
|
||||
_MUX mdB7 (TENB, TDB[7], BUS_DB[7], BMUX_DB[7]);
|
||||
_MUX mdB8 (TENB, TDB[8], BUS_DB[8], BMUX_DB[8]);
|
||||
_MUX mdB9 (TENB, TDB[9], BUS_DB[9], BMUX_DB[9]);
|
||||
_MUX mdB10 (TENB, TDB[10], BUS_DB[10], BMUX_DB[10]);
|
||||
_MUX mdB11 (TENB, TDB[11], BUS_DB[11], BMUX_DB[11]);
|
||||
_MUX mdB12 (TENB, TDB[12], BUS_DB[12], BMUX_DB[12]);
|
||||
_MUX mdB13 (TENB, TDB[13], BUS_DB[13], BMUX_DB[13]);
|
||||
_MUX mdB14 (TENB, TDB[14], BUS_DB[14], BMUX_DB[14]);
|
||||
_MUX mdB15 (TENB, TDB[15], BUS_DB[15], BMUX_DB[15]);
|
||||
_MUX mdB16 (TENB, TDB[16], BUS_DB[16], BMUX_DB[16]);
|
||||
_MUX mdB17 (TENB, TDB[17], BUS_DB[17], BMUX_DB[17]);
|
||||
_MUX mdB18 (TENB, TDB[18], BUS_DB[18], BMUX_DB[18]);
|
||||
|
||||
_MUX mcenB (TENB, TCENB, CENB, BMUX_CENB);
|
||||
_MUX mcenselB (DFTRAMBYP, 1'b0,BMUX_CENB, BMUXSEL_CENB);
|
||||
buf bufmcenB (CENYB, BMUXSEL_CENB);
|
||||
wire [7:0] B_max, B_max_n, AB_m;
|
||||
wire XoutBif, XoutBiff;
|
||||
wire [7:1] BMUX_AB_n, EQ_B, m_AB;
|
||||
wire [6:0] XoutBi;
|
||||
not BMUX_AB1_n (BMUX_AB_n[1], BMUX_AB[1]);
|
||||
not BMUX_AB2_n (BMUX_AB_n[2], BMUX_AB[2]);
|
||||
not BMUX_AB3_n (BMUX_AB_n[3], BMUX_AB[3]);
|
||||
not BMUX_AB4_n (BMUX_AB_n[4], BMUX_AB[4]);
|
||||
not BMUX_AB5_n (BMUX_AB_n[5], BMUX_AB[5]);
|
||||
not BMUX_AB6_n (BMUX_AB_n[6], BMUX_AB[6]);
|
||||
not BMUX_AB7_n (BMUX_AB_n[7], BMUX_AB[7]);
|
||||
|
||||
assign B_max[0] = 1;
|
||||
assign B_max[1] = 1;
|
||||
assign B_max[2] = 1;
|
||||
assign B_max[3] = 1;
|
||||
assign B_max[4] = 1;
|
||||
assign B_max[5] = 1;
|
||||
assign B_max[6] = 1;
|
||||
assign B_max[7] = 1;
|
||||
|
||||
not Bmax0_n (B_max_n[0], B_max[0]);
|
||||
not Bmax1_n (B_max_n[1], B_max[1]);
|
||||
not Bmax2_n (B_max_n[2], B_max[2]);
|
||||
not Bmax3_n (B_max_n[3], B_max[3]);
|
||||
not Bmax4_n (B_max_n[4], B_max[4]);
|
||||
not Bmax5_n (B_max_n[5], B_max[5]);
|
||||
not Bmax6_n (B_max_n[6], B_max[6]);
|
||||
not Bmax7_n (B_max_n[7], B_max[7]);
|
||||
|
||||
and andBMUXABAmax0 (AB_m[0], BMUX_AB[0], B_max_n[0]);
|
||||
and andBMUXABAmax1 (AB_m[1], BMUX_AB[1], B_max_n[1]);
|
||||
and andBMUXABAmax2 (AB_m[2], BMUX_AB[2], B_max_n[2]);
|
||||
and andBMUXABAmax3 (AB_m[3], BMUX_AB[3], B_max_n[3]);
|
||||
and andBMUXABAmax4 (AB_m[4], BMUX_AB[4], B_max_n[4]);
|
||||
and andBMUXABAmax5 (AB_m[5], BMUX_AB[5], B_max_n[5]);
|
||||
and andBMUXABAmax6 (AB_m[6], BMUX_AB[6], B_max_n[6]);
|
||||
and andBMUXABAmax7 (AB_m[7], BMUX_AB[7], B_max_n[7]);
|
||||
|
||||
and andBMUXABAmax1_n (m_AB[1], BMUX_AB_n[1], B_max[1]);
|
||||
and andBMUXABAmax2_n (m_AB[2], BMUX_AB_n[2], B_max[2]);
|
||||
and andBMUXABAmax3_n (m_AB[3], BMUX_AB_n[3], B_max[3]);
|
||||
and andBMUXABAmax4_n (m_AB[4], BMUX_AB_n[4], B_max[4]);
|
||||
and andBMUXABAmax5_n (m_AB[5], BMUX_AB_n[5], B_max[5]);
|
||||
and andBMUXABAmax6_n (m_AB[6], BMUX_AB_n[6], B_max[6]);
|
||||
and andBMUXABAmax7_n (m_AB[7], BMUX_AB_n[7], B_max[7]);
|
||||
|
||||
nor norABAmax1 (EQ_B[1], m_AB[1], AB_m[1]);
|
||||
nor norABAmax2 (EQ_B[2], m_AB[2], AB_m[2]);
|
||||
nor norABAmax3 (EQ_B[3], m_AB[3], AB_m[3]);
|
||||
nor norABAmax4 (EQ_B[4], m_AB[4], AB_m[4]);
|
||||
nor norABAmax5 (EQ_B[5], m_AB[5], AB_m[5]);
|
||||
nor norABAmax6 (EQ_B[6], m_AB[6], AB_m[6]);
|
||||
nor norABAmax7 (EQ_B[7], m_AB[7], AB_m[7]);
|
||||
|
||||
and XfABAmax0 (XoutBi[0], AB_m[0], EQ_B[7], EQ_B[6], EQ_B[5], EQ_B[4], EQ_B[3], EQ_B[2], EQ_B[1]);
|
||||
and XfABAmax1 (XoutBi[1], AB_m[1], EQ_B[7], EQ_B[6], EQ_B[5], EQ_B[4], EQ_B[3], EQ_B[2]);
|
||||
and XfABAmax2 (XoutBi[2], AB_m[2], EQ_B[7], EQ_B[6], EQ_B[5], EQ_B[4], EQ_B[3]);
|
||||
and XfABAmax3 (XoutBi[3], AB_m[3], EQ_B[7], EQ_B[6], EQ_B[5], EQ_B[4]);
|
||||
and XfABAmax4 (XoutBi[4], AB_m[4], EQ_B[7], EQ_B[6], EQ_B[5]);
|
||||
and XfABAmax5 (XoutBi[5], AB_m[5], EQ_B[7], EQ_B[6]);
|
||||
and XfABAmax6 (XoutBi[6], AB_m[6], EQ_B[7]);
|
||||
or orXfABAmax7 (XoutBif, AB_m[7], XoutBi[0], XoutBi[1], XoutBi[2], XoutBi[3], XoutBi[4], XoutBi[5], XoutBi[6]);
|
||||
|
||||
wire [7:0] xDetectionAddrBusB;
|
||||
xor addrHandleB0 (xDetectionAddrBusB[0], BMUX_AB[0], BMUX_AB[0]);
|
||||
xor addrHandleB1 (xDetectionAddrBusB[1], BMUX_AB[1], BMUX_AB[1]);
|
||||
xor addrHandleB2 (xDetectionAddrBusB[2], BMUX_AB[2], BMUX_AB[2]);
|
||||
xor addrHandleB3 (xDetectionAddrBusB[3], BMUX_AB[3], BMUX_AB[3]);
|
||||
xor addrHandleB4 (xDetectionAddrBusB[4], BMUX_AB[4], BMUX_AB[4]);
|
||||
xor addrHandleB5 (xDetectionAddrBusB[5], BMUX_AB[5], BMUX_AB[5]);
|
||||
xor addrHandleB6 (xDetectionAddrBusB[6], BMUX_AB[6], BMUX_AB[6]);
|
||||
xor addrHandleB7 (xDetectionAddrBusB[7], BMUX_AB[7], BMUX_AB[7]);
|
||||
or addrFinalB (xAddrB,xDetectionAddrBusB[0],xDetectionAddrBusB[1],xDetectionAddrBusB[2],xDetectionAddrBusB[3],xDetectionAddrBusB[4],xDetectionAddrBusB[5],xDetectionAddrBusB[6],xDetectionAddrBusB[7]);
|
||||
or xBoundB (XoutBFinal, XoutBif, xAddrB);
|
||||
nor scanshiftB (nscanshiftB, DFTRAMBYP, SEB);
|
||||
and XoutaddrB (XoutaddrB, nscanshiftB, XoutBFinal);
|
||||
or XoutBFF0 (XoutBiff, XoutaddrB, XoutB);
|
||||
|
||||
wire NOT_CENB;
|
||||
not (NOT_CENB, BMUX_CENB);
|
||||
wire NOT_DFTRAMBYP;
|
||||
not (NOT_DFTRAMBYP, DFTRAMBYP);
|
||||
wire [18:0] WRITEB;
|
||||
and (WRITEB[0], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[1], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[2], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[3], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[4], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[5], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[6], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[7], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[8], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[9], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[10], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[11], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[12], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[13], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[14], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[15], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[16], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[17], NOT_DFTRAMBYP, NOT_CENB);
|
||||
and (WRITEB[18], NOT_DFTRAMBYP, NOT_CENB);
|
||||
rf2_256x19_wm0_bitcell memB0 (.CLK(CLKB), .WRITE(WRITEB[0]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[0]), .Xout(XoutBiff), .Q(INT_QA[0]));
|
||||
rf2_256x19_wm0_bitcell memB1 (.CLK(CLKB), .WRITE(WRITEB[1]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[1]), .Xout(XoutBiff), .Q(INT_QA[1]));
|
||||
rf2_256x19_wm0_bitcell memB2 (.CLK(CLKB), .WRITE(WRITEB[2]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[2]), .Xout(XoutBiff), .Q(INT_QA[2]));
|
||||
rf2_256x19_wm0_bitcell memB3 (.CLK(CLKB), .WRITE(WRITEB[3]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[3]), .Xout(XoutBiff), .Q(INT_QA[3]));
|
||||
rf2_256x19_wm0_bitcell memB4 (.CLK(CLKB), .WRITE(WRITEB[4]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[4]), .Xout(XoutBiff), .Q(INT_QA[4]));
|
||||
rf2_256x19_wm0_bitcell memB5 (.CLK(CLKB), .WRITE(WRITEB[5]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[5]), .Xout(XoutBiff), .Q(INT_QA[5]));
|
||||
rf2_256x19_wm0_bitcell memB6 (.CLK(CLKB), .WRITE(WRITEB[6]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[6]), .Xout(XoutBiff), .Q(INT_QA[6]));
|
||||
rf2_256x19_wm0_bitcell memB7 (.CLK(CLKB), .WRITE(WRITEB[7]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[7]), .Xout(XoutBiff), .Q(INT_QA[7]));
|
||||
rf2_256x19_wm0_bitcell memB8 (.CLK(CLKB), .WRITE(WRITEB[8]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[8]), .Xout(XoutBiff), .Q(INT_QA[8]));
|
||||
rf2_256x19_wm0_bitcell memB9 (.CLK(CLKB), .WRITE(WRITEB[9]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[9]), .Xout(XoutBiff), .Q(INT_QA[9]));
|
||||
rf2_256x19_wm0_bitcell memB10 (.CLK(CLKB), .WRITE(WRITEB[10]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[10]), .Xout(XoutBiff), .Q(INT_QA[10]));
|
||||
rf2_256x19_wm0_bitcell memB11 (.CLK(CLKB), .WRITE(WRITEB[11]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[11]), .Xout(XoutBiff), .Q(INT_QA[11]));
|
||||
rf2_256x19_wm0_bitcell memB12 (.CLK(CLKB), .WRITE(WRITEB[12]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[12]), .Xout(XoutBiff), .Q(INT_QA[12]));
|
||||
rf2_256x19_wm0_bitcell memB13 (.CLK(CLKB), .WRITE(WRITEB[13]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[13]), .Xout(XoutBiff), .Q(INT_QA[13]));
|
||||
rf2_256x19_wm0_bitcell memB14 (.CLK(CLKB), .WRITE(WRITEB[14]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[14]), .Xout(XoutBiff), .Q(INT_QA[14]));
|
||||
rf2_256x19_wm0_bitcell memB15 (.CLK(CLKB), .WRITE(WRITEB[15]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[15]), .Xout(XoutBiff), .Q(INT_QA[15]));
|
||||
rf2_256x19_wm0_bitcell memB16 (.CLK(CLKB), .WRITE(WRITEB[16]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[16]), .Xout(XoutBiff), .Q(INT_QA[16]));
|
||||
rf2_256x19_wm0_bitcell memB17 (.CLK(CLKB), .WRITE(WRITEB[17]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[17]), .Xout(XoutBiff), .Q(INT_QA[17]));
|
||||
rf2_256x19_wm0_bitcell memB18 (.CLK(CLKB), .WRITE(WRITEB[18]), .WA(BMUX_AB), .RA(BMUX_AA), .D(BMUX_DB[18]), .Xout(XoutBiff), .Q(INT_QA[18]));
|
||||
xor (x_detection_CENB, BMUX_CENB, BMUX_CENB);
|
||||
and (acendftB, x_detection_CENB, NOT_DFTRAMBYP);
|
||||
assign XoutB = (SEB & ~DFTRAMBYP) | acendftB;
|
||||
wire [18:0] QB_int;
|
||||
wire [18:0] DB_hold;
|
||||
_MUX mhB0 (BMUX_CENB, BMUX_DB[0], QB_int[0], DB_hold[0]);
|
||||
_MUX mhB1 (BMUX_CENB, BMUX_DB[1], QB_int[1], DB_hold[1]);
|
||||
_MUX mhB2 (BMUX_CENB, BMUX_DB[2], QB_int[2], DB_hold[2]);
|
||||
_MUX mhB3 (BMUX_CENB, BMUX_DB[3], QB_int[3], DB_hold[3]);
|
||||
_MUX mhB4 (BMUX_CENB, BMUX_DB[4], QB_int[4], DB_hold[4]);
|
||||
_MUX mhB5 (BMUX_CENB, BMUX_DB[5], QB_int[5], DB_hold[5]);
|
||||
_MUX mhB6 (BMUX_CENB, BMUX_DB[6], QB_int[6], DB_hold[6]);
|
||||
_MUX mhB7 (BMUX_CENB, BMUX_DB[7], QB_int[7], DB_hold[7]);
|
||||
_MUX mhB8 (BMUX_CENB, BMUX_DB[8], QB_int[8], DB_hold[8]);
|
||||
_MUX mhB9 (BMUX_CENB, BMUX_DB[9], QB_int[9], DB_hold[9]);
|
||||
_MUX mhB10 (BMUX_CENB, BMUX_DB[10], QB_int[10], DB_hold[10]);
|
||||
_MUX mhB11 (BMUX_CENB, BMUX_DB[11], QB_int[11], DB_hold[11]);
|
||||
_MUX mhB12 (BMUX_CENB, BMUX_DB[12], QB_int[12], DB_hold[12]);
|
||||
_MUX mhB13 (BMUX_CENB, BMUX_DB[13], QB_int[13], DB_hold[13]);
|
||||
_MUX mhB14 (BMUX_CENB, BMUX_DB[14], QB_int[14], DB_hold[14]);
|
||||
_MUX mhB15 (BMUX_CENB, BMUX_DB[15], QB_int[15], DB_hold[15]);
|
||||
_MUX mhB16 (BMUX_CENB, BMUX_DB[16], QB_int[16], DB_hold[16]);
|
||||
_MUX mhB17 (BMUX_CENB, BMUX_DB[17], QB_int[17], DB_hold[17]);
|
||||
_MUX mhB18 (BMUX_CENB, BMUX_DB[18], QB_int[18], DB_hold[18]);
|
||||
_MUX mqB0 (DFTRAMBYP, DB_hold[0], BMUX_DB[0], DB_scan[0]);
|
||||
_MUX mqB1 (DFTRAMBYP, DB_hold[1], BMUX_DB[1], DB_scan[1]);
|
||||
_MUX mqB2 (DFTRAMBYP, DB_hold[2], BMUX_DB[2], DB_scan[2]);
|
||||
_MUX mqB3 (DFTRAMBYP, DB_hold[3], BMUX_DB[3], DB_scan[3]);
|
||||
_MUX mqB4 (DFTRAMBYP, DB_hold[4], BMUX_DB[4], DB_scan[4]);
|
||||
_MUX mqB5 (DFTRAMBYP, DB_hold[5], BMUX_DB[5], DB_scan[5]);
|
||||
_MUX mqB6 (DFTRAMBYP, DB_hold[6], BMUX_DB[6], DB_scan[6]);
|
||||
_MUX mqB7 (DFTRAMBYP, DB_hold[7], BMUX_DB[7], DB_scan[7]);
|
||||
_MUX mqB8 (DFTRAMBYP, DB_hold[8], BMUX_DB[8], DB_scan[8]);
|
||||
_MUX mqB9 (DFTRAMBYP, DB_hold[9], BMUX_DB[9], DB_scan[9]);
|
||||
_MUX mqB10 (DFTRAMBYP, DB_hold[10], BMUX_DB[10], DB_scan[10]);
|
||||
_MUX mqB11 (DFTRAMBYP, DB_hold[11], BMUX_DB[11], DB_scan[11]);
|
||||
_MUX mqB12 (DFTRAMBYP, DB_hold[12], BMUX_DB[12], DB_scan[12]);
|
||||
_MUX mqB13 (DFTRAMBYP, DB_hold[13], BMUX_DB[13], DB_scan[13]);
|
||||
_MUX mqB14 (DFTRAMBYP, DB_hold[14], BMUX_DB[14], DB_scan[14]);
|
||||
_MUX mqB15 (DFTRAMBYP, DB_hold[15], BMUX_DB[15], DB_scan[15]);
|
||||
_MUX mqB16 (DFTRAMBYP, DB_hold[16], BMUX_DB[16], DB_scan[16]);
|
||||
_MUX mqB17 (DFTRAMBYP, DB_hold[17], BMUX_DB[17], DB_scan[17]);
|
||||
_MUX mqB18 (DFTRAMBYP, DB_hold[18], BMUX_DB[18], DB_scan[18]);
|
||||
rf2_256x19_wm0_scanflop uDQB0 (.CLK(CLKB), .SE(SEB), .SI(QB_int[1]), .D(DB_scan[0]), .Q(QB_int[0]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB1 (.CLK(CLKB), .SE(SEB), .SI(QB_int[2]), .D(DB_scan[1]), .Q(QB_int[1]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB2 (.CLK(CLKB), .SE(SEB), .SI(QB_int[3]), .D(DB_scan[2]), .Q(QB_int[2]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB3 (.CLK(CLKB), .SE(SEB), .SI(QB_int[4]), .D(DB_scan[3]), .Q(QB_int[3]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB4 (.CLK(CLKB), .SE(SEB), .SI(QB_int[5]), .D(DB_scan[4]), .Q(QB_int[4]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB5 (.CLK(CLKB), .SE(SEB), .SI(QB_int[6]), .D(DB_scan[5]), .Q(QB_int[5]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB6 (.CLK(CLKB), .SE(SEB), .SI(QB_int[7]), .D(DB_scan[6]), .Q(QB_int[6]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB7 (.CLK(CLKB), .SE(SEB), .SI(QB_int[8]), .D(DB_scan[7]), .Q(QB_int[7]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB8 (.CLK(CLKB), .SE(SEB), .SI(BUS_SIB[0]), .D(DB_scan[8]), .Q(QB_int[8]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB9 (.CLK(CLKB), .SE(SEB), .SI(BUS_SIB[1]), .D(DB_scan[9]), .Q(QB_int[9]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB10 (.CLK(CLKB), .SE(SEB), .SI(QB_int[9]), .D(DB_scan[10]), .Q(QB_int[10]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB11 (.CLK(CLKB), .SE(SEB), .SI(QB_int[10]), .D(DB_scan[11]), .Q(QB_int[11]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB12 (.CLK(CLKB), .SE(SEB), .SI(QB_int[11]), .D(DB_scan[12]), .Q(QB_int[12]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB13 (.CLK(CLKB), .SE(SEB), .SI(QB_int[12]), .D(DB_scan[13]), .Q(QB_int[13]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB14 (.CLK(CLKB), .SE(SEB), .SI(QB_int[13]), .D(DB_scan[14]), .Q(QB_int[14]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB15 (.CLK(CLKB), .SE(SEB), .SI(QB_int[14]), .D(DB_scan[15]), .Q(QB_int[15]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB16 (.CLK(CLKB), .SE(SEB), .SI(QB_int[15]), .D(DB_scan[16]), .Q(QB_int[16]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB17 (.CLK(CLKB), .SE(SEB), .SI(QB_int[16]), .D(DB_scan[17]), .Q(QB_int[17]), .Xout(XoutBiff));
|
||||
rf2_256x19_wm0_scanflop uDQB18 (.CLK(CLKB), .SE(SEB), .SI(QB_int[17]), .D(DB_scan[18]), .Q(QB_int[18]), .Xout(XoutBiff));
|
||||
assign SOB[0] = QB_int[0];
|
||||
assign SOB[1] = QB_int[18];
|
||||
endmodule
|
||||
`undef read_write
|
||||
`disable_portfaults
|
||||
`nosuppress_faults
|
||||
8695
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v
Normal file
8695
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v
Normal file
File diff suppressed because it is too large
Load Diff
197
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0_antenna.clf
Normal file
197
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0_antenna.clf
Normal file
@@ -0,0 +1,197 @@
|
||||
# Copyright (c) 1993 - 2019 ARM Limited. All Rights Reserved.
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Limited.
|
||||
|
||||
# PhyVGen V 8.3.0
|
||||
# ARM Version r4p0
|
||||
# Creation Date: Sun Oct 20 14:43:11 2019
|
||||
|
||||
|
||||
defineGateSize "rf2_256x19_wm0" "AA[0]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AA[0]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AA[1]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AA[1]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AA[2]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AA[2]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AA[3]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AA[3]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AA[4]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AA[4]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AA[5]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AA[5]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AA[6]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AA[6]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AA[7]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AA[7]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AB[0]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AB[0]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AB[1]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AB[1]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AB[2]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AB[2]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AB[3]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AB[3]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AB[4]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AB[4]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AB[5]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AB[5]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AB[6]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AB[6]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "AB[7]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "AB[7]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "CENA" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "CENA" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "CENB" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "CENB" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "CLKA" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "CLKA" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "CLKB" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "CLKB" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "COLLDISN" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "COLLDISN" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[0]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[0]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[10]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[10]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[11]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[11]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[12]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[12]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[13]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[13]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[14]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[14]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[15]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[15]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[16]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[16]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[17]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[17]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[18]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[18]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[1]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[1]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[2]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[2]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[3]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[3]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[4]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[4]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[5]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[5]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[6]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[6]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[7]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[7]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[8]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[8]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DB[9]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DB[9]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "DFTRAMBYP" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "DFTRAMBYP" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "EMAA[0]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "EMAA[0]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "EMAA[1]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "EMAA[1]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "EMAA[2]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "EMAA[2]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "EMAB[0]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "EMAB[0]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "EMAB[1]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "EMAB[1]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "EMAB[2]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "EMAB[2]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "EMASA" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "EMASA" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "RET1N" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "RET1N" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "SEA" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "SEA" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "SEB" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "SEB" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "SIA[0]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "SIA[0]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "SIA[1]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "SIA[1]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "SIB[0]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "SIB[0]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "SIB[1]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "SIB[1]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAA[0]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAA[0]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAA[1]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAA[1]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAA[2]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAA[2]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAA[3]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAA[3]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAA[4]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAA[4]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAA[5]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAA[5]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAA[6]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAA[6]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAA[7]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAA[7]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAB[0]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAB[0]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAB[1]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAB[1]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAB[2]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAB[2]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAB[3]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAB[3]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAB[4]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAB[4]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAB[5]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAB[5]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAB[6]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAB[6]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TAB[7]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TAB[7]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TCENA" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TCENA" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TCENB" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TCENB" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[0]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[0]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[10]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[10]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[11]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[11]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[12]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[12]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[13]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[13]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[14]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[14]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[15]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[15]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[16]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[16]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[17]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[17]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[18]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[18]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[1]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[1]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[2]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[2]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[3]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[3]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[4]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[4]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[5]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[5]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[6]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[6]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[7]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[7]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[8]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[8]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TDB[9]" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TDB[9]" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TENA" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TENA" '(0.018)
|
||||
defineGateSize "rf2_256x19_wm0" "TENB" 0.014
|
||||
defineDiodeProtection "rf2_256x19_wm0" "TENB" '(0.018)
|
||||
@@ -0,0 +1,162 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:42:10 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_256x19_wm0
|
||||
# Number of Words: 256
|
||||
# Number of Bits: 19
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: off
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: avm
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# avm_memcomp Version: 2.1.1-EAC
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
rf2_256x19_wm0 {
|
||||
MEMORY_TYPE RegFile
|
||||
EQUIV_GATE_COUNT 5350
|
||||
VDD_PIN VDDCE VDDPE
|
||||
GND_PIN VSSE
|
||||
#This file is for PROCESS FF, CORNER FF_0P99V_0P99V_125C
|
||||
#However, RedHawk needs the process to be specified as 'PROCESS XX'
|
||||
PROCESS XX
|
||||
Cload 3.5e-05nF
|
||||
VDD 0.99 0.99
|
||||
|
||||
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
|
||||
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
|
||||
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
|
||||
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
|
||||
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
|
||||
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
|
||||
|
||||
Cpd avm_into_lowpwr {
|
||||
VDDCE VSSE 1.73242e-04nF
|
||||
VDDPE VSSE 9.45426e-05nF
|
||||
}
|
||||
PEAK_I avm_into_lowpwr {
|
||||
VDDCE VSSE 4.02906mA
|
||||
VDDPE VSSE 3.25356mA
|
||||
}
|
||||
Cpd avm_outof_lowpwr {
|
||||
VDDCE VSSE 1.90566e-04nF
|
||||
VDDPE VSSE 3.09007e-03nF
|
||||
}
|
||||
PEAK_I avm_outof_lowpwr {
|
||||
VDDCE VSSE 4.43196mA
|
||||
VDDPE VSSE 26.58102mA
|
||||
}
|
||||
Cpd avm_read_write {
|
||||
VDDCE VSSE 1.26875e-04nF
|
||||
VDDPE VSSE 2.26423e-03nF
|
||||
}
|
||||
PEAK_I avm_read_write {
|
||||
VDDCE VSSE 4.20219mA
|
||||
VDDPE VSSE 27.91007mA
|
||||
}
|
||||
Cpd avm_read_desel {
|
||||
VDDCE VSSE 5.53268e-05nF
|
||||
VDDPE VSSE 1.05400e-03nF
|
||||
}
|
||||
PEAK_I avm_read_desel {
|
||||
VDDCE VSSE 1.75082mA
|
||||
VDDPE VSSE 13.34667mA
|
||||
}
|
||||
Cpd avm_desel_write {
|
||||
VDDCE VSSE 7.15481e-05nF
|
||||
VDDPE VSSE 1.21023e-03nF
|
||||
}
|
||||
PEAK_I avm_desel_write {
|
||||
VDDCE VSSE 1.84066mA
|
||||
VDDPE VSSE 15.58574mA
|
||||
}
|
||||
Cpd avm_scan_capture {
|
||||
VDDCE VSSE 8.27046e-06nF
|
||||
VDDPE VSSE 2.20337e-03nF
|
||||
}
|
||||
PEAK_I avm_scan_capture {
|
||||
VDDCE VSSE 0.42769mA
|
||||
VDDPE VSSE 11.39868mA
|
||||
}
|
||||
Cpd avm_scan_shift {
|
||||
VDDCE VSSE 8.27046e-06nF
|
||||
VDDPE VSSE 2.20337e-03nF
|
||||
}
|
||||
PEAK_I avm_scan_shift {
|
||||
VDDCE VSSE 0.42769mA
|
||||
VDDPE VSSE 11.39868mA
|
||||
}
|
||||
Cpd standby_trig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.95501e-05nF
|
||||
}
|
||||
Cpd standby_ntrig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 2.17223e-05nF
|
||||
}
|
||||
LEAKAGE_I {
|
||||
VDDCE VSSE 0.29933mA
|
||||
VDDPE VSSE 0.62518mA
|
||||
}
|
||||
tsu 0.105188ns
|
||||
ck2q_delay 0.301316ns
|
||||
tr_q 0.0134386ns
|
||||
tf_q 0.0156072ns
|
||||
CHARACTERIZATION_MODE accurate
|
||||
}
|
||||
@@ -0,0 +1,322 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:42:33 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_256x19_wm0
|
||||
# Number of Words: 256
|
||||
# Number of Bits: 19
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: off
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: datatable
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# datatable_memcomp Version: 1.3.0-amci
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
# Units used in Datatable :
|
||||
# geomx: micron
|
||||
# geomy: micron
|
||||
# Voltage: volts
|
||||
# Temprature: Degree Celsius
|
||||
# Current: mA
|
||||
# Time: ns
|
||||
#
|
||||
name ff_0p99v_0p99v_125c
|
||||
S N
|
||||
geomx 51.4050
|
||||
geomy 100.9400
|
||||
volt 0.9900
|
||||
temp 125.0000
|
||||
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
|
||||
tcenacenya 0.0917
|
||||
ttcenacenya 0.0905
|
||||
ttenacenyapu 0.1191
|
||||
ttenacenyanu 0.1399
|
||||
tdftrambypcenya 0.0912
|
||||
taaaya 0.0751
|
||||
ttaaaya 0.0751
|
||||
ttenaayapu 0.1377
|
||||
ttenaayanu 0.1335
|
||||
tdftrambypaya 0.0823
|
||||
tcenbcenyb 0.0947
|
||||
ttcenbcenyb 0.0939
|
||||
ttenbcenybpu 0.1240
|
||||
ttenbcenybnu 0.1515
|
||||
tdftrambypcenyb 0.0907
|
||||
tabayb 0.0753
|
||||
ttabayb 0.0779
|
||||
ttenbaybpu 0.1447
|
||||
ttenbaybnu 0.1398
|
||||
tdftrambypayb 0.0822
|
||||
taccqa_rd0 0.2902
|
||||
taccqa_rd1 0.2970
|
||||
taccqa_rd2 0.2986
|
||||
taccqa_rd3 0.3013
|
||||
taccqa_rd4 0.3433
|
||||
taccqa_rd5 0.3800
|
||||
taccqa_rd6 0.4188
|
||||
taccqa_rd7 0.4555
|
||||
taccqa_scan0 0.2902
|
||||
taccqa_scan1 0.2970
|
||||
taccqa_scan2 0.2986
|
||||
taccqa_scan3 0.3013
|
||||
taccqa_scan4 0.3433
|
||||
taccqa_scan5 0.3800
|
||||
taccqa_scan6 0.4188
|
||||
taccqa_scan7 0.4555
|
||||
tclkasoa_rd0 0.3088
|
||||
tclkasoa_rd1 0.3156
|
||||
tclkasoa_rd2 0.3171
|
||||
tclkasoa_rd3 0.3199
|
||||
tclkasoa_rd4 0.3619
|
||||
tclkasoa_rd5 0.3986
|
||||
tclkasoa_rd6 0.4374
|
||||
tclkasoa_rd7 0.4741
|
||||
tclkasoa_scan0 0.3088
|
||||
tclkasoa_scan1 0.3156
|
||||
tclkasoa_scan2 0.3171
|
||||
tclkasoa_scan3 0.3199
|
||||
tclkasoa_scan4 0.3619
|
||||
tclkasoa_scan5 0.3986
|
||||
tclkasoa_scan6 0.4374
|
||||
tclkasoa_scan7 0.4741
|
||||
tclkbsob 0.1612
|
||||
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
|
||||
kload_cenya 1.7116
|
||||
kload_aya 1.4236
|
||||
kload_cenyb 1.6712
|
||||
kload_ayb 1.4006
|
||||
kload_qa 0.5053
|
||||
kload_soa 1.3720
|
||||
kload_sob 1.4401
|
||||
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
|
||||
tcyca_ema0 0.4005
|
||||
tcyca_ema1 0.4074
|
||||
tcyca_ema2 0.4090
|
||||
tcyca_ema3 0.4118
|
||||
tcyca_ema4 0.4545
|
||||
tcyca_ema5 0.4917
|
||||
tcyca_ema6 0.5311
|
||||
tcyca_ema7 0.5684
|
||||
tcycb_ema0 0.4531
|
||||
tcycb_ema1 0.4946
|
||||
tcycb_ema2 0.5085
|
||||
tcycb_ema3 0.5397
|
||||
tcycb_ema4 0.5914
|
||||
tcycb_ema5 0.6268
|
||||
tcycb_ema6 0.6747
|
||||
tcycb_ema7 0.7104
|
||||
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
|
||||
tcracwb_rd0 0.2152
|
||||
tcracwb_rd1 0.2220
|
||||
tcracwb_rd2 0.2235
|
||||
tcracwb_rd3 0.2263
|
||||
tcracwb_rd4 0.2683
|
||||
tcracwb_rd5 0.3050
|
||||
tcracwb_rd6 0.3438
|
||||
tcracwb_rd7 0.3805
|
||||
tcwbcra_wr0 0.2939
|
||||
tcwbcra_wr1 0.3347
|
||||
tcwbcra_wr2 0.3484
|
||||
tcwbcra_wr3 0.3792
|
||||
tcwbcra_wr4 0.4300
|
||||
tcwbcra_wr5 0.4650
|
||||
tcwbcra_wr6 0.5122
|
||||
tcwbcra_wr7 0.5474
|
||||
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
|
||||
tckah 0.0927
|
||||
tckal 0.0898
|
||||
tckbh 0.0959
|
||||
tckbl 0.0907
|
||||
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
|
||||
tcenas 0.1050
|
||||
taas 0.1052
|
||||
tcenbs 0.1076
|
||||
tabs 0.1109
|
||||
tdbs 0.0373
|
||||
temaas 0.4371
|
||||
temasas 0.4371
|
||||
temabs 0.5650
|
||||
ttenas 0.1861
|
||||
ttcenas 0.1053
|
||||
ttaas 0.1072
|
||||
ttenbs 0.2464
|
||||
ttcenbs 0.1081
|
||||
ttabs 0.1146
|
||||
ttdbs 0.0382
|
||||
tsias 0.2047
|
||||
tseas 0.2047
|
||||
tdftrambypas 0.1675
|
||||
tdftrambypbs 0.1675
|
||||
tsibs 0.0373
|
||||
tsebs 0.2464
|
||||
tcolldisnas 0.4371
|
||||
tcolldisnbs 0.5650
|
||||
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
|
||||
tcenah 0.0403
|
||||
tcenaf_ret1nfh 0.5747
|
||||
tcenaf_ret1nrh 0.3886
|
||||
taah 0.0702
|
||||
tcenbh 0.0423
|
||||
tcenbf_ret1nfh 0.5747
|
||||
tcenbf_ret1nrh 0.3886
|
||||
tabh 0.0649
|
||||
tdbh 0.0950
|
||||
temaah 0.6605
|
||||
temasah 0.6605
|
||||
temabh 0.7454
|
||||
ttenah 0.0772
|
||||
ttcenah 0.0415
|
||||
ttcenaf_ret1nfh 0.5747
|
||||
ttcenaf_ret1nrh 0.3886
|
||||
ttaah 0.0702
|
||||
ttenbh 0.1045
|
||||
ttcenbh 0.0436
|
||||
ttcenbf_ret1nfh 0.5747
|
||||
ttcenbf_ret1nrh 0.3886
|
||||
ttabh 0.0649
|
||||
ttdbh 0.0950
|
||||
tret1nf_dftrambypfh 0.0270
|
||||
tret1nr_dftrambypfh 0.5747
|
||||
tret1nf_cenbrh 0.0270
|
||||
tret1nf_cenarh 0.0263
|
||||
tret1nf_tcenarh 0.0263
|
||||
tret1nf_tcenbrh 0.0270
|
||||
tret1nr_tcenbrh 0.5747
|
||||
tret1nr_tcenarh 0.4468
|
||||
tret1nr_cenbrh 0.5747
|
||||
tret1nr_cenarh 0.4468
|
||||
tsiah 0.0756
|
||||
tseah 0.6605
|
||||
tdftrambypah 0.6605
|
||||
tdftrambypbh 0.5747
|
||||
tdftrambypr_ret1nfh 0.5747
|
||||
tdftrambypr_ret1nrh 0.3886
|
||||
tsibh 0.0950
|
||||
tsebh 0.1045
|
||||
tcolldisnah 0.6605
|
||||
tcolldisnbh 0.7454
|
||||
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
|
||||
icap_clka 0.0105
|
||||
icap_cena 0.0018
|
||||
icap_aa 0.0012
|
||||
icap_clkb 0.0106
|
||||
icap_cenb 0.0015
|
||||
icap_ab 0.0012
|
||||
icap_db 0.0019
|
||||
icap_emaa 0.0059
|
||||
icap_emasa 0.0021
|
||||
icap_emab 0.0057
|
||||
icap_tena 0.0010
|
||||
icap_tcena 0.0016
|
||||
icap_taa 0.0014
|
||||
icap_tenb 0.0012
|
||||
icap_tcenb 0.0016
|
||||
icap_tab 0.0014
|
||||
icap_tdb 0.0016
|
||||
icap_sia 0.0015
|
||||
icap_sea 0.0019
|
||||
icap_dftrambyp 0.0021
|
||||
icap_sib 0.0056
|
||||
icap_seb 0.0019
|
||||
icap_colldisn 0.0024
|
||||
icap_ret1n 0.0035
|
||||
# High Density Two Port Register File SVT MVT Compiler : current specific information.
|
||||
icc_standby_c_chipdisable 0.29933
|
||||
icc_standby_p_chipdisable 0.625182
|
||||
icc_standby_c_ret1 0.328285
|
||||
icc_standby_p_ret1 0.061257
|
||||
icc_standby_c_selective_precharge 0.282523
|
||||
icc_standby_p_selective_precharge 0.521972
|
||||
icc_c_rd0_a 5.448e-05
|
||||
icc_c_rd1_a 5.463e-05
|
||||
icc_c_rd2_a 5.477e-05
|
||||
icc_c_rd3_a 5.477e-05
|
||||
icc_c_rd4_a 5.486e-05
|
||||
icc_c_rd5_a 5.486e-05
|
||||
icc_c_rd6_a 5.508e-05
|
||||
icc_c_rd7_a 5.508e-05
|
||||
icc_p_rd0_a 1.035e-03
|
||||
icc_p_rd1_a 1.041e-03
|
||||
icc_p_rd2_a 1.043e-03
|
||||
icc_p_rd3_a 1.043e-03
|
||||
icc_p_rd4_a 1.078e-03
|
||||
icc_p_rd5_a 1.105e-03
|
||||
icc_p_rd6_a 1.135e-03
|
||||
icc_p_rd7_a 1.149e-03
|
||||
icc_c_wr0_b 7.054e-05
|
||||
icc_c_wr1_b 7.068e-05
|
||||
icc_c_wr2_b 7.083e-05
|
||||
icc_c_wr3_b 7.083e-05
|
||||
icc_c_wr4_b 7.092e-05
|
||||
icc_c_wr5_b 7.092e-05
|
||||
icc_c_wr6_b 7.113e-05
|
||||
icc_c_wr7_b 7.113e-05
|
||||
icc_p_wr0_b 1.189e-03
|
||||
icc_p_wr1_b 1.196e-03
|
||||
icc_p_wr2_b 1.198e-03
|
||||
icc_p_wr3_b 1.198e-03
|
||||
icc_p_wr4_b 1.232e-03
|
||||
icc_p_wr5_b 1.260e-03
|
||||
icc_p_wr6_b 1.289e-03
|
||||
icc_p_wr7_b 1.304e-03
|
||||
icc_c_desela 0.000e+00
|
||||
icc_p_desela 1.083e-04
|
||||
icc_c_deselb 0.000e+00
|
||||
icc_p_deselb 1.788e-04
|
||||
icc_c_peak 4.20219
|
||||
icc_p_peak 27.910073
|
||||
icc_c_inrush 4.002086
|
||||
icc_p_inrush 26.581022
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
257
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0_rtl.v
Normal file
257
models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0_rtl.v
Normal file
@@ -0,0 +1,257 @@
|
||||
/* verilog_rtl_memcomp Version: 4.0.5-beta11 */
|
||||
/* common_memcomp Version: 4.0.5.2-amci */
|
||||
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
|
||||
//
|
||||
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
//
|
||||
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
//
|
||||
// Use of this Software is subject to the terms and conditions of the
|
||||
// applicable license agreement with ARM Physical IP, Inc.
|
||||
// In addition, this Software is protected by patents, copyright law
|
||||
// and international treaties.
|
||||
//
|
||||
// The copyright notice(s) in this Software does not indicate actual or
|
||||
// intended publication of this Software.
|
||||
//
|
||||
// Repair Verilog RTL for High Density Two Port Register File SVT MVT Compiler
|
||||
//
|
||||
// Instance Name: rf2_256x19_wm0_rtl_top
|
||||
// Words: 256
|
||||
// User Bits: 19
|
||||
// Mux: 2
|
||||
// Drive: 6
|
||||
// Write Mask: Off
|
||||
// Extra Margin Adjustment: On
|
||||
// Redundancy: off
|
||||
// Redundant Rows: 0
|
||||
// Redundant Columns: 2
|
||||
// Test Muxes On
|
||||
// Ser: none
|
||||
// Retention: on
|
||||
// Power Gating: off
|
||||
//
|
||||
// Creation Date: Sun Oct 20 14:44:23 2019
|
||||
// Version: r4p0
|
||||
//
|
||||
// Verified
|
||||
//
|
||||
// Known Bugs: None.
|
||||
//
|
||||
// Known Work Arounds: N/A
|
||||
//
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module rf2_256x19_wm0_rtl_top (
|
||||
CENYA,
|
||||
AYA,
|
||||
CENYB,
|
||||
AYB,
|
||||
QA,
|
||||
SOA,
|
||||
SOB,
|
||||
CLKA,
|
||||
CENA,
|
||||
AA,
|
||||
CLKB,
|
||||
CENB,
|
||||
AB,
|
||||
DB,
|
||||
EMAA,
|
||||
EMASA,
|
||||
EMAB,
|
||||
TENA,
|
||||
TCENA,
|
||||
TAA,
|
||||
TENB,
|
||||
TCENB,
|
||||
TAB,
|
||||
TDB,
|
||||
RET1N,
|
||||
SIA,
|
||||
SEA,
|
||||
DFTRAMBYP,
|
||||
SIB,
|
||||
SEB,
|
||||
COLLDISN
|
||||
);
|
||||
|
||||
output CENYA;
|
||||
output [7:0] AYA;
|
||||
output CENYB;
|
||||
output [7:0] AYB;
|
||||
output [18:0] QA;
|
||||
output [1:0] SOA;
|
||||
output [1:0] SOB;
|
||||
input CLKA;
|
||||
input CENA;
|
||||
input [7:0] AA;
|
||||
input CLKB;
|
||||
input CENB;
|
||||
input [7:0] AB;
|
||||
input [18:0] DB;
|
||||
input [2:0] EMAA;
|
||||
input EMASA;
|
||||
input [2:0] EMAB;
|
||||
input TENA;
|
||||
input TCENA;
|
||||
input [7:0] TAA;
|
||||
input TENB;
|
||||
input TCENB;
|
||||
input [7:0] TAB;
|
||||
input [18:0] TDB;
|
||||
input RET1N;
|
||||
input [1:0] SIA;
|
||||
input SEA;
|
||||
input DFTRAMBYP;
|
||||
input [1:0] SIB;
|
||||
input SEB;
|
||||
input COLLDISN;
|
||||
wire [18:0] QOA;
|
||||
wire [18:0] DIB;
|
||||
|
||||
assign QA = QOA;
|
||||
assign DIB = DB;
|
||||
rf2_256x19_wm0_fr_top u0 (
|
||||
.CENYA(CENYA),
|
||||
.AYA(AYA),
|
||||
.CENYB(CENYB),
|
||||
.AYB(AYB),
|
||||
.QOA(QOA),
|
||||
.SOA(SOA),
|
||||
.SOB(SOB),
|
||||
.CLKA(CLKA),
|
||||
.CENA(CENA),
|
||||
.AA(AA),
|
||||
.CLKB(CLKB),
|
||||
.CENB(CENB),
|
||||
.AB(AB),
|
||||
.DIB(DIB),
|
||||
.EMAA(EMAA),
|
||||
.EMASA(EMASA),
|
||||
.EMAB(EMAB),
|
||||
.TENA(TENA),
|
||||
.TCENA(TCENA),
|
||||
.TAA(TAA),
|
||||
.TENB(TENB),
|
||||
.TCENB(TCENB),
|
||||
.TAB(TAB),
|
||||
.TDB(TDB),
|
||||
.RET1N(RET1N),
|
||||
.SIA(SIA),
|
||||
.SEA(SEA),
|
||||
.DFTRAMBYP(DFTRAMBYP),
|
||||
.SIB(SIB),
|
||||
.SEB(SEB),
|
||||
.COLLDISN(COLLDISN)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
module rf2_256x19_wm0_fr_top (
|
||||
CENYA,
|
||||
AYA,
|
||||
CENYB,
|
||||
AYB,
|
||||
QOA,
|
||||
SOA,
|
||||
SOB,
|
||||
CLKA,
|
||||
CENA,
|
||||
AA,
|
||||
CLKB,
|
||||
CENB,
|
||||
AB,
|
||||
DIB,
|
||||
EMAA,
|
||||
EMASA,
|
||||
EMAB,
|
||||
TENA,
|
||||
TCENA,
|
||||
TAA,
|
||||
TENB,
|
||||
TCENB,
|
||||
TAB,
|
||||
TDB,
|
||||
RET1N,
|
||||
SIA,
|
||||
SEA,
|
||||
DFTRAMBYP,
|
||||
SIB,
|
||||
SEB,
|
||||
COLLDISN
|
||||
);
|
||||
|
||||
output CENYA;
|
||||
output [7:0] AYA;
|
||||
output CENYB;
|
||||
output [7:0] AYB;
|
||||
output [18:0] QOA;
|
||||
output [1:0] SOA;
|
||||
output [1:0] SOB;
|
||||
input CLKA;
|
||||
input CENA;
|
||||
input [7:0] AA;
|
||||
input CLKB;
|
||||
input CENB;
|
||||
input [7:0] AB;
|
||||
input [18:0] DIB;
|
||||
input [2:0] EMAA;
|
||||
input EMASA;
|
||||
input [2:0] EMAB;
|
||||
input TENA;
|
||||
input TCENA;
|
||||
input [7:0] TAA;
|
||||
input TENB;
|
||||
input TCENB;
|
||||
input [7:0] TAB;
|
||||
input [18:0] TDB;
|
||||
input RET1N;
|
||||
input [1:0] SIA;
|
||||
input SEA;
|
||||
input DFTRAMBYP;
|
||||
input [1:0] SIB;
|
||||
input SEB;
|
||||
input COLLDISN;
|
||||
|
||||
wire [18:0] DB;
|
||||
wire [18:0] QA;
|
||||
|
||||
assign DB=DIB;
|
||||
assign QOA=QA;
|
||||
rf2_256x19_wm0 u0 (
|
||||
.CENYA(CENYA),
|
||||
.AYA(AYA),
|
||||
.CENYB(CENYB),
|
||||
.AYB(AYB),
|
||||
.QA(QA),
|
||||
.SOA(SOA),
|
||||
.SOB(SOB),
|
||||
.CLKA(CLKA),
|
||||
.CENA(CENA),
|
||||
.AA(AA),
|
||||
.CLKB(CLKB),
|
||||
.CENB(CENB),
|
||||
.AB(AB),
|
||||
.DB(DB),
|
||||
.EMAA(EMAA),
|
||||
.EMASA(EMASA),
|
||||
.EMAB(EMAB),
|
||||
.TENA(TENA),
|
||||
.TCENA(TCENA),
|
||||
.TAA(TAA),
|
||||
.TENB(TENB),
|
||||
.TCENB(TCENB),
|
||||
.TAB(TAB),
|
||||
.TDB(TDB),
|
||||
.RET1N(RET1N),
|
||||
.SIA(SIA),
|
||||
.SEA(SEA),
|
||||
.DFTRAMBYP(DFTRAMBYP),
|
||||
.SIB(SIB),
|
||||
.SEB(SEB),
|
||||
.COLLDISN(COLLDISN)
|
||||
);
|
||||
|
||||
endmodule // rf2_256x19_wm0_fr_top
|
||||
|
||||
@@ -0,0 +1,162 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:42:16 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_256x19_wm0
|
||||
# Number of Words: 256
|
||||
# Number of Bits: 19
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: off
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: avm
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# avm_memcomp Version: 2.1.1-EAC
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
rf2_256x19_wm0 {
|
||||
MEMORY_TYPE RegFile
|
||||
EQUIV_GATE_COUNT 5350
|
||||
VDD_PIN VDDCE VDDPE
|
||||
GND_PIN VSSE
|
||||
#This file is for PROCESS SS, CORNER SS_0P81V_0P81V_M40C
|
||||
#However, RedHawk needs the process to be specified as 'PROCESS XX'
|
||||
PROCESS XX
|
||||
Cload 3.5e-05nF
|
||||
VDD 0.81 0.81
|
||||
|
||||
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
|
||||
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
|
||||
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
|
||||
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
|
||||
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
|
||||
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
|
||||
|
||||
Cpd avm_into_lowpwr {
|
||||
VDDCE VSSE 1.48673e-04nF
|
||||
VDDPE VSSE 9.01115e-05nF
|
||||
}
|
||||
PEAK_I avm_into_lowpwr {
|
||||
VDDCE VSSE 1.38817mA
|
||||
VDDPE VSSE 0.97135mA
|
||||
}
|
||||
Cpd avm_outof_lowpwr {
|
||||
VDDCE VSSE 1.63540e-04nF
|
||||
VDDPE VSSE 3.10890e-03nF
|
||||
}
|
||||
PEAK_I avm_outof_lowpwr {
|
||||
VDDCE VSSE 1.52699mA
|
||||
VDDPE VSSE 8.69205mA
|
||||
}
|
||||
Cpd avm_read_write {
|
||||
VDDCE VSSE 1.13854e-04nF
|
||||
VDDPE VSSE 2.11867e-03nF
|
||||
}
|
||||
PEAK_I avm_read_write {
|
||||
VDDCE VSSE 1.45098mA
|
||||
VDDPE VSSE 9.09066mA
|
||||
}
|
||||
Cpd avm_read_desel {
|
||||
VDDCE VSSE 5.23159e-05nF
|
||||
VDDPE VSSE 9.65228e-04nF
|
||||
}
|
||||
PEAK_I avm_read_desel {
|
||||
VDDCE VSSE 0.60711mA
|
||||
VDDPE VSSE 4.24643mA
|
||||
}
|
||||
Cpd avm_desel_write {
|
||||
VDDCE VSSE 6.15378e-05nF
|
||||
VDDPE VSSE 1.15344e-03nF
|
||||
}
|
||||
PEAK_I avm_desel_write {
|
||||
VDDCE VSSE 0.59437mA
|
||||
VDDPE VSSE 5.38193mA
|
||||
}
|
||||
Cpd avm_scan_capture {
|
||||
VDDCE VSSE 8.45177e-06nF
|
||||
VDDPE VSSE 2.05103e-03nF
|
||||
}
|
||||
PEAK_I avm_scan_capture {
|
||||
VDDCE VSSE 0.13288mA
|
||||
VDDPE VSSE 3.77962mA
|
||||
}
|
||||
Cpd avm_scan_shift {
|
||||
VDDCE VSSE 8.45177e-06nF
|
||||
VDDPE VSSE 2.05103e-03nF
|
||||
}
|
||||
PEAK_I avm_scan_shift {
|
||||
VDDCE VSSE 0.13288mA
|
||||
VDDPE VSSE 3.77962mA
|
||||
}
|
||||
Cpd standby_trig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.69190e-05nF
|
||||
}
|
||||
Cpd standby_ntrig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.87989e-05nF
|
||||
}
|
||||
LEAKAGE_I {
|
||||
VDDCE VSSE 3.40800e-04mA
|
||||
VDDPE VSSE 1.89600e-04mA
|
||||
}
|
||||
tsu 0.30673ns
|
||||
ck2q_delay 0.764671ns
|
||||
tr_q 0.0346427ns
|
||||
tf_q 0.0394933ns
|
||||
CHARACTERIZATION_MODE accurate
|
||||
}
|
||||
@@ -0,0 +1,322 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:42:37 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_256x19_wm0
|
||||
# Number of Words: 256
|
||||
# Number of Bits: 19
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: off
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: datatable
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# datatable_memcomp Version: 1.3.0-amci
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
# Units used in Datatable :
|
||||
# geomx: micron
|
||||
# geomy: micron
|
||||
# Voltage: volts
|
||||
# Temprature: Degree Celsius
|
||||
# Current: mA
|
||||
# Time: ns
|
||||
#
|
||||
name ss_0p81v_0p81v_m40c
|
||||
S N
|
||||
geomx 51.4050
|
||||
geomy 100.9400
|
||||
volt 0.8100
|
||||
temp -40.0000
|
||||
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
|
||||
tcenacenya 0.2145
|
||||
ttcenacenya 0.2108
|
||||
ttenacenyapu 0.3031
|
||||
ttenacenyanu 0.3532
|
||||
tdftrambypcenya 0.2178
|
||||
taaaya 0.2110
|
||||
ttaaaya 0.2184
|
||||
ttenaayapu 0.3903
|
||||
ttenaayanu 0.3746
|
||||
tdftrambypaya 0.2078
|
||||
tcenbcenyb 0.2113
|
||||
ttcenbcenyb 0.2108
|
||||
ttenbcenybpu 0.3062
|
||||
ttenbcenybnu 0.3744
|
||||
tdftrambypcenyb 0.2168
|
||||
tabayb 0.2105
|
||||
ttabayb 0.2161
|
||||
ttenbaybpu 0.4138
|
||||
ttenbaybnu 0.3794
|
||||
tdftrambypayb 0.2083
|
||||
taccqa_rd0 0.7194
|
||||
taccqa_rd1 0.7473
|
||||
taccqa_rd2 0.7553
|
||||
taccqa_rd3 0.7647
|
||||
taccqa_rd4 0.8825
|
||||
taccqa_rd5 0.9986
|
||||
taccqa_rd6 1.1296
|
||||
taccqa_rd7 1.2442
|
||||
taccqa_scan0 0.7194
|
||||
taccqa_scan1 0.7473
|
||||
taccqa_scan2 0.7553
|
||||
taccqa_scan3 0.7647
|
||||
taccqa_scan4 0.8825
|
||||
taccqa_scan5 0.9986
|
||||
taccqa_scan6 1.1296
|
||||
taccqa_scan7 1.2442
|
||||
tclkasoa_rd0 0.8235
|
||||
tclkasoa_rd1 0.8514
|
||||
tclkasoa_rd2 0.8595
|
||||
tclkasoa_rd3 0.8688
|
||||
tclkasoa_rd4 0.9866
|
||||
tclkasoa_rd5 1.1028
|
||||
tclkasoa_rd6 1.2337
|
||||
tclkasoa_rd7 1.3484
|
||||
tclkasoa_scan0 0.8235
|
||||
tclkasoa_scan1 0.8514
|
||||
tclkasoa_scan2 0.8595
|
||||
tclkasoa_scan3 0.8688
|
||||
tclkasoa_scan4 0.9866
|
||||
tclkasoa_scan5 1.1028
|
||||
tclkasoa_scan6 1.2337
|
||||
tclkasoa_scan7 1.3484
|
||||
tclkbsob 0.4155
|
||||
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
|
||||
kload_cenya 3.3060
|
||||
kload_aya 2.7500
|
||||
kload_cenyb 3.3440
|
||||
kload_ayb 2.7720
|
||||
kload_qa 1.0935
|
||||
kload_soa 2.7600
|
||||
kload_sob 3.1660
|
||||
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
|
||||
tcyca_ema0 1.0230
|
||||
tcyca_ema1 1.0514
|
||||
tcyca_ema2 1.0595
|
||||
tcyca_ema3 1.0690
|
||||
tcyca_ema4 1.1886
|
||||
tcyca_ema5 1.3065
|
||||
tcyca_ema6 1.4394
|
||||
tcyca_ema7 1.5558
|
||||
tcycb_ema0 1.3567
|
||||
tcycb_ema1 1.5235
|
||||
tcycb_ema2 1.5936
|
||||
tcycb_ema3 1.7094
|
||||
tcycb_ema4 1.8473
|
||||
tcycb_ema5 1.9592
|
||||
tcycb_ema6 2.1113
|
||||
tcycb_ema7 2.2259
|
||||
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
|
||||
tcracwb_rd0 0.5071
|
||||
tcracwb_rd1 0.5350
|
||||
tcracwb_rd2 0.5431
|
||||
tcracwb_rd3 0.5524
|
||||
tcracwb_rd4 0.6703
|
||||
tcracwb_rd5 0.7864
|
||||
tcracwb_rd6 0.9174
|
||||
tcracwb_rd7 1.0320
|
||||
tcwbcra_wr0 0.8059
|
||||
tcwbcra_wr1 0.9703
|
||||
tcwbcra_wr2 1.0393
|
||||
tcwbcra_wr3 1.1534
|
||||
tcwbcra_wr4 1.2892
|
||||
tcwbcra_wr5 1.3995
|
||||
tcwbcra_wr6 1.5494
|
||||
tcwbcra_wr7 1.6622
|
||||
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
|
||||
tckah 0.1789
|
||||
tckal 0.1936
|
||||
tckbh 0.1811
|
||||
tckbl 0.1760
|
||||
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
|
||||
tcenas 0.2616
|
||||
taas 0.3067
|
||||
tcenbs 0.2580
|
||||
tabs 0.3108
|
||||
tdbs 0.2167
|
||||
temaas 1.1524
|
||||
temasas 1.1524
|
||||
temabs 1.7928
|
||||
ttenas 0.4973
|
||||
ttcenas 0.2628
|
||||
ttaas 0.3154
|
||||
ttenbs 0.6238
|
||||
ttcenbs 0.2586
|
||||
ttabs 0.3179
|
||||
ttdbs 0.2206
|
||||
tsias 0.5470
|
||||
tseas 0.5470
|
||||
tdftrambypas 0.4530
|
||||
tdftrambypbs 0.4530
|
||||
tsibs 0.2167
|
||||
tsebs 0.6238
|
||||
tcolldisnas 1.1524
|
||||
tcolldisnbs 1.7928
|
||||
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
|
||||
tcenah 0.0852
|
||||
tcenaf_ret1nfh 1.7736
|
||||
tcenaf_ret1nrh 0.8902
|
||||
taah 0.1420
|
||||
tcenbh 0.0853
|
||||
tcenbf_ret1nfh 1.7736
|
||||
tcenbf_ret1nrh 0.8902
|
||||
tabh 0.1299
|
||||
tdbh 0.1864
|
||||
temaah 1.8086
|
||||
temasah 1.8086
|
||||
temabh 2.2901
|
||||
ttenah 0.1562
|
||||
ttcenah 0.0868
|
||||
ttcenaf_ret1nfh 1.7736
|
||||
ttcenaf_ret1nrh 0.8902
|
||||
ttaah 0.1420
|
||||
ttenbh 0.2050
|
||||
ttcenbh 0.0866
|
||||
ttcenbf_ret1nfh 1.7736
|
||||
ttcenbf_ret1nrh 0.8902
|
||||
ttabh 0.1299
|
||||
ttdbh 0.1864
|
||||
tret1nf_dftrambypfh 0.0657
|
||||
tret1nr_dftrambypfh 1.7736
|
||||
tret1nf_cenbrh 0.0646
|
||||
tret1nf_cenarh 0.0657
|
||||
tret1nf_tcenarh 0.0657
|
||||
tret1nf_tcenbrh 0.0646
|
||||
tret1nr_tcenbrh 1.7736
|
||||
tret1nr_tcenarh 1.1332
|
||||
tret1nr_cenbrh 1.7736
|
||||
tret1nr_cenarh 1.1332
|
||||
tsiah 0.1247
|
||||
tseah 1.8086
|
||||
tdftrambypah 1.8086
|
||||
tdftrambypbh 1.7736
|
||||
tdftrambypr_ret1nfh 1.7736
|
||||
tdftrambypr_ret1nrh 0.8902
|
||||
tsibh 0.1864
|
||||
tsebh 0.2050
|
||||
tcolldisnah 1.8086
|
||||
tcolldisnbh 2.2901
|
||||
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
|
||||
icap_clka 0.0087
|
||||
icap_cena 0.0014
|
||||
icap_aa 0.0017
|
||||
icap_clkb 0.0088
|
||||
icap_cenb 0.0011
|
||||
icap_ab 0.0015
|
||||
icap_db 0.0018
|
||||
icap_emaa 0.0056
|
||||
icap_emasa 0.0021
|
||||
icap_emab 0.0054
|
||||
icap_tena 0.0008
|
||||
icap_tcena 0.0012
|
||||
icap_taa 0.0016
|
||||
icap_tenb 0.0009
|
||||
icap_tcenb 0.0012
|
||||
icap_tab 0.0014
|
||||
icap_tdb 0.0015
|
||||
icap_sia 0.0011
|
||||
icap_sea 0.0016
|
||||
icap_dftrambyp 0.0016
|
||||
icap_sib 0.0054
|
||||
icap_seb 0.0017
|
||||
icap_colldisn 0.0021
|
||||
icap_ret1n 0.0032
|
||||
# High Density Two Port Register File SVT MVT Compiler : current specific information.
|
||||
icc_standby_c_chipdisable 3.408e-04
|
||||
icc_standby_p_chipdisable 1.896e-04
|
||||
icc_standby_c_ret1 3.353e-04
|
||||
icc_standby_p_ret1 1.218e-06
|
||||
icc_standby_c_selective_precharge 3.335e-04
|
||||
icc_standby_p_selective_precharge 9.349e-05
|
||||
icc_c_rd0_a 4.237e-05
|
||||
icc_c_rd1_a 4.238e-05
|
||||
icc_c_rd2_a 4.238e-05
|
||||
icc_c_rd3_a 4.238e-05
|
||||
icc_c_rd4_a 4.238e-05
|
||||
icc_c_rd5_a 4.244e-05
|
||||
icc_c_rd6_a 4.251e-05
|
||||
icc_c_rd7_a 4.255e-05
|
||||
icc_p_rd0_a 7.708e-04
|
||||
icc_p_rd1_a 7.766e-04
|
||||
icc_p_rd2_a 7.796e-04
|
||||
icc_p_rd3_a 7.818e-04
|
||||
icc_p_rd4_a 8.241e-04
|
||||
icc_p_rd5_a 8.608e-04
|
||||
icc_p_rd6_a 8.853e-04
|
||||
icc_p_rd7_a 8.955e-04
|
||||
icc_c_wr0_b 4.984e-05
|
||||
icc_c_wr1_b 4.985e-05
|
||||
icc_c_wr2_b 4.985e-05
|
||||
icc_c_wr3_b 4.985e-05
|
||||
icc_c_wr4_b 4.985e-05
|
||||
icc_c_wr5_b 4.991e-05
|
||||
icc_c_wr6_b 4.998e-05
|
||||
icc_c_wr7_b 5.002e-05
|
||||
icc_p_wr0_b 9.232e-04
|
||||
icc_p_wr1_b 9.291e-04
|
||||
icc_p_wr2_b 9.320e-04
|
||||
icc_p_wr3_b 9.343e-04
|
||||
icc_p_wr4_b 9.766e-04
|
||||
icc_p_wr5_b 1.013e-03
|
||||
icc_p_wr6_b 1.038e-03
|
||||
icc_p_wr7_b 1.048e-03
|
||||
icc_c_desela 0.000e+00
|
||||
icc_p_desela 7.685e-05
|
||||
icc_c_deselb 0.000e+00
|
||||
icc_p_deselb 1.306e-04
|
||||
icc_c_peak 1.450981
|
||||
icc_p_peak 9.090659
|
||||
icc_c_inrush 1.381887
|
||||
icc_p_inrush 8.65777
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,162 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:42:22 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_256x19_wm0
|
||||
# Number of Words: 256
|
||||
# Number of Bits: 19
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: off
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: avm
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# avm_memcomp Version: 2.1.1-EAC
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
rf2_256x19_wm0 {
|
||||
MEMORY_TYPE RegFile
|
||||
EQUIV_GATE_COUNT 5350
|
||||
VDD_PIN VDDCE VDDPE
|
||||
GND_PIN VSSE
|
||||
#This file is for PROCESS TT, CORNER TT_0P90V_0P90V_25C
|
||||
#However, RedHawk needs the process to be specified as 'PROCESS XX'
|
||||
PROCESS XX
|
||||
Cload 3.5e-05nF
|
||||
VDD 0.9 0.9
|
||||
|
||||
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
|
||||
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
|
||||
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
|
||||
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
|
||||
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
|
||||
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
|
||||
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
|
||||
|
||||
Cpd avm_into_lowpwr {
|
||||
VDDCE VSSE 1.58295e-04nF
|
||||
VDDPE VSSE 8.96839e-05nF
|
||||
}
|
||||
PEAK_I avm_into_lowpwr {
|
||||
VDDCE VSSE 2.51762mA
|
||||
VDDPE VSSE 1.86034mA
|
||||
}
|
||||
Cpd avm_outof_lowpwr {
|
||||
VDDCE VSSE 1.74125e-04nF
|
||||
VDDPE VSSE 3.09166e-03nF
|
||||
}
|
||||
PEAK_I avm_outof_lowpwr {
|
||||
VDDCE VSSE 2.76938mA
|
||||
VDDPE VSSE 16.33388mA
|
||||
}
|
||||
Cpd avm_read_write {
|
||||
VDDCE VSSE 1.16619e-04nF
|
||||
VDDPE VSSE 2.19870e-03nF
|
||||
}
|
||||
PEAK_I avm_read_write {
|
||||
VDDCE VSSE 2.63262mA
|
||||
VDDPE VSSE 17.15057mA
|
||||
}
|
||||
Cpd avm_read_desel {
|
||||
VDDCE VSSE 5.31663e-05nF
|
||||
VDDPE VSSE 9.99581e-04nF
|
||||
}
|
||||
PEAK_I avm_read_desel {
|
||||
VDDCE VSSE 0.96190mA
|
||||
VDDPE VSSE 7.91806mA
|
||||
}
|
||||
Cpd avm_desel_write {
|
||||
VDDCE VSSE 6.34529e-05nF
|
||||
VDDPE VSSE 1.19912e-03nF
|
||||
}
|
||||
PEAK_I avm_desel_write {
|
||||
VDDCE VSSE 1.01244mA
|
||||
VDDPE VSSE 9.74696mA
|
||||
}
|
||||
Cpd avm_scan_capture {
|
||||
VDDCE VSSE 8.40553e-06nF
|
||||
VDDPE VSSE 2.14259e-03nF
|
||||
}
|
||||
PEAK_I avm_scan_capture {
|
||||
VDDCE VSSE 0.27129mA
|
||||
VDDPE VSSE 6.93612mA
|
||||
}
|
||||
Cpd avm_scan_shift {
|
||||
VDDCE VSSE 8.40553e-06nF
|
||||
VDDPE VSSE 2.14259e-03nF
|
||||
}
|
||||
PEAK_I avm_scan_shift {
|
||||
VDDCE VSSE 0.27129mA
|
||||
VDDPE VSSE 6.93612mA
|
||||
}
|
||||
Cpd standby_trig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.77000e-05nF
|
||||
}
|
||||
Cpd standby_ntrig {
|
||||
VDDCE VSSE 0.00000e+00nF
|
||||
VDDPE VSSE 1.96666e-05nF
|
||||
}
|
||||
LEAKAGE_I {
|
||||
VDDCE VSSE 2.50900e-03mA
|
||||
VDDPE VSSE 4.15700e-03mA
|
||||
}
|
||||
tsu 0.146718ns
|
||||
ck2q_delay 0.398883ns
|
||||
tr_q 0.0188104ns
|
||||
tf_q 0.0219533ns
|
||||
CHARACTERIZATION_MODE accurate
|
||||
}
|
||||
@@ -0,0 +1,322 @@
|
||||
#
|
||||
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
|
||||
#
|
||||
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
|
||||
#
|
||||
# Use of this Software is subject to the terms and conditions of the
|
||||
# applicable license agreement with ARM Physical IP, Inc.
|
||||
# In addition, this Software is protected by patents, copyright law
|
||||
# and international treaties.
|
||||
#
|
||||
# The copyright notice(s) in this Software does not indicate actual or
|
||||
# intended publication of this Software.
|
||||
#
|
||||
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
|
||||
#
|
||||
# Creation Date: Sun Oct 20 14:42:42 2019
|
||||
#
|
||||
# Instance Options:
|
||||
# Instance Name: rf2_256x19_wm0
|
||||
# Number of Words: 256
|
||||
# Number of Bits: 19
|
||||
# Multiplexer Width: 2
|
||||
# Multi-Vt selection: BASE
|
||||
# Frequency <MHz>: 1
|
||||
# Activity Factor <%>: 50
|
||||
# Pipeline: off
|
||||
# Word-Write Mask: off
|
||||
# Word Partition Size: 1
|
||||
# Write through: off
|
||||
# Top Metal Layer: m5-m10
|
||||
# Power Type: otc
|
||||
# Redundancy: off
|
||||
# Redundant Columns: 2
|
||||
# Redundant Rows: 0
|
||||
# BIST MUXes: on
|
||||
# Soft Error Repair (SER): none
|
||||
# Power Gating: off
|
||||
# Back Biasing: off
|
||||
# Retention: on
|
||||
# Extra Margin Adjustment: on
|
||||
# Advanced Test Features: off
|
||||
# Customer Comment: This is a memory instance
|
||||
# Bus-notation: on
|
||||
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
|
||||
# Name Case: upper
|
||||
# Check Instance Name: off
|
||||
# Diodes: on
|
||||
# Drive Strength: 6
|
||||
# Site Definitions: off
|
||||
# Library Name: USERLIB
|
||||
# Liberty setting: nldm
|
||||
#
|
||||
# Compiler Versions:
|
||||
# Memory Version: r4p0
|
||||
# Lang compiler Version: 4.1.6-EAC2
|
||||
# View Name: datatable
|
||||
# AMCI Version: 1.4.3-EAC
|
||||
# datatable_memcomp Version: 1.3.0-amci
|
||||
#
|
||||
# Modeling Assumptions: N/A
|
||||
#
|
||||
# Modeling Limitations: N/A
|
||||
#
|
||||
# Known Bugs: N/A
|
||||
#
|
||||
# Known Work Arounds: N/A
|
||||
#
|
||||
# Units used in Datatable :
|
||||
# geomx: micron
|
||||
# geomy: micron
|
||||
# Voltage: volts
|
||||
# Temprature: Degree Celsius
|
||||
# Current: mA
|
||||
# Time: ns
|
||||
#
|
||||
name tt_0p90v_0p90v_25c
|
||||
S N
|
||||
geomx 51.4050
|
||||
geomy 100.9400
|
||||
volt 0.9000
|
||||
temp 25.0000
|
||||
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
|
||||
tcenacenya 0.1187
|
||||
ttcenacenya 0.1176
|
||||
ttenacenyapu 0.1613
|
||||
ttenacenyanu 0.1884
|
||||
tdftrambypcenya 0.1213
|
||||
taaaya 0.1038
|
||||
ttaaaya 0.1082
|
||||
ttenaayapu 0.1878
|
||||
ttenaayanu 0.1834
|
||||
tdftrambypaya 0.1113
|
||||
tcenbcenyb 0.1195
|
||||
ttcenbcenyb 0.1185
|
||||
ttenbcenybpu 0.1658
|
||||
ttenbcenybnu 0.2026
|
||||
tdftrambypcenyb 0.1187
|
||||
tabayb 0.1040
|
||||
ttabayb 0.1062
|
||||
ttenbaybpu 0.2038
|
||||
ttenbaybnu 0.1937
|
||||
tdftrambypayb 0.1118
|
||||
taccqa_rd0 0.3815
|
||||
taccqa_rd1 0.3920
|
||||
taccqa_rd2 0.3950
|
||||
taccqa_rd3 0.3989
|
||||
taccqa_rd4 0.4570
|
||||
taccqa_rd5 0.5089
|
||||
taccqa_rd6 0.5665
|
||||
taccqa_rd7 0.6182
|
||||
taccqa_scan0 0.3815
|
||||
taccqa_scan1 0.3920
|
||||
taccqa_scan2 0.3950
|
||||
taccqa_scan3 0.3989
|
||||
taccqa_scan4 0.4570
|
||||
taccqa_scan5 0.5089
|
||||
taccqa_scan6 0.5665
|
||||
taccqa_scan7 0.6182
|
||||
tclkasoa_rd0 0.4152
|
||||
tclkasoa_rd1 0.4258
|
||||
tclkasoa_rd2 0.4288
|
||||
tclkasoa_rd3 0.4327
|
||||
tclkasoa_rd4 0.4908
|
||||
tclkasoa_rd5 0.5427
|
||||
tclkasoa_rd6 0.6003
|
||||
tclkasoa_rd7 0.6520
|
||||
tclkasoa_scan0 0.4152
|
||||
tclkasoa_scan1 0.4258
|
||||
tclkasoa_scan2 0.4288
|
||||
tclkasoa_scan3 0.4327
|
||||
tclkasoa_scan4 0.4908
|
||||
tclkasoa_scan5 0.5427
|
||||
tclkasoa_scan6 0.6003
|
||||
tclkasoa_scan7 0.6520
|
||||
tclkbsob 0.2178
|
||||
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
|
||||
kload_cenya 2.0800
|
||||
kload_aya 1.6620
|
||||
kload_cenyb 1.9640
|
||||
kload_ayb 1.6740
|
||||
kload_qa 0.6365
|
||||
kload_soa 1.7020
|
||||
kload_sob 1.8420
|
||||
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
|
||||
tcyca_ema0 0.5302
|
||||
tcyca_ema1 0.5410
|
||||
tcyca_ema2 0.5440
|
||||
tcyca_ema3 0.5479
|
||||
tcyca_ema4 0.6069
|
||||
tcyca_ema5 0.6596
|
||||
tcyca_ema6 0.7181
|
||||
tcyca_ema7 0.7706
|
||||
tcycb_ema0 0.6364
|
||||
tcycb_ema1 0.7006
|
||||
tcycb_ema2 0.7253
|
||||
tcycb_ema3 0.7724
|
||||
tcycb_ema4 0.8420
|
||||
tcycb_ema5 0.8934
|
||||
tcycb_ema6 0.9619
|
||||
tcycb_ema7 1.0133
|
||||
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
|
||||
tcracwb_rd0 0.2690
|
||||
tcracwb_rd1 0.2796
|
||||
tcracwb_rd2 0.2825
|
||||
tcracwb_rd3 0.2864
|
||||
tcracwb_rd4 0.3445
|
||||
tcracwb_rd5 0.3965
|
||||
tcracwb_rd6 0.4541
|
||||
tcracwb_rd7 0.5058
|
||||
tcwbcra_wr0 0.3946
|
||||
tcwbcra_wr1 0.4578
|
||||
tcwbcra_wr2 0.4822
|
||||
tcwbcra_wr3 0.5285
|
||||
tcwbcra_wr4 0.5971
|
||||
tcwbcra_wr5 0.6478
|
||||
tcwbcra_wr6 0.7153
|
||||
tcwbcra_wr7 0.7659
|
||||
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
|
||||
tckah 0.1135
|
||||
tckal 0.1133
|
||||
tckbh 0.1159
|
||||
tckbl 0.1130
|
||||
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
|
||||
tcenas 0.1417
|
||||
taas 0.1467
|
||||
tcenbs 0.1422
|
||||
tabs 0.1545
|
||||
tdbs 0.0714
|
||||
temaas 0.5877
|
||||
temasas 0.5877
|
||||
temabs 0.8121
|
||||
ttenas 0.2541
|
||||
ttcenas 0.1417
|
||||
ttaas 0.1512
|
||||
ttenbs 0.3297
|
||||
ttcenbs 0.1434
|
||||
ttabs 0.1580
|
||||
ttdbs 0.0737
|
||||
tsias 0.2795
|
||||
tseas 0.2795
|
||||
tdftrambypas 0.2304
|
||||
tdftrambypbs 0.2304
|
||||
tsibs 0.0714
|
||||
tsebs 0.3297
|
||||
tcolldisnas 0.5877
|
||||
tcolldisnbs 0.8121
|
||||
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
|
||||
tcenah 0.0495
|
||||
tcenaf_ret1nfh 0.8155
|
||||
tcenaf_ret1nrh 0.5017
|
||||
taah 0.0840
|
||||
tcenbh 0.0496
|
||||
tcenbf_ret1nfh 0.8155
|
||||
tcenbf_ret1nrh 0.5017
|
||||
tabh 0.0788
|
||||
tdbh 0.1126
|
||||
temaah 0.8964
|
||||
temasah 0.8964
|
||||
temabh 1.0565
|
||||
ttenah 0.0924
|
||||
ttcenah 0.0524
|
||||
ttcenaf_ret1nfh 0.8155
|
||||
ttcenaf_ret1nrh 0.5017
|
||||
ttaah 0.0840
|
||||
ttenbh 0.1239
|
||||
ttcenbh 0.0510
|
||||
ttcenbf_ret1nfh 0.8155
|
||||
ttcenbf_ret1nrh 0.5017
|
||||
ttabh 0.0788
|
||||
ttdbh 0.1126
|
||||
tret1nf_dftrambypfh 0.0358
|
||||
tret1nr_dftrambypfh 0.8155
|
||||
tret1nf_cenbrh 0.0358
|
||||
tret1nf_cenarh 0.0354
|
||||
tret1nf_tcenarh 0.0354
|
||||
tret1nf_tcenbrh 0.0358
|
||||
tret1nr_tcenbrh 0.8155
|
||||
tret1nr_tcenarh 0.5911
|
||||
tret1nr_cenbrh 0.8155
|
||||
tret1nr_cenarh 0.5911
|
||||
tsiah 0.0817
|
||||
tseah 0.8964
|
||||
tdftrambypah 0.8964
|
||||
tdftrambypbh 0.8155
|
||||
tdftrambypr_ret1nfh 0.8155
|
||||
tdftrambypr_ret1nrh 0.5017
|
||||
tsibh 0.1126
|
||||
tsebh 0.1239
|
||||
tcolldisnah 0.8964
|
||||
tcolldisnbh 1.0565
|
||||
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
|
||||
icap_clka 0.0091
|
||||
icap_cena 0.0013
|
||||
icap_aa 0.0016
|
||||
icap_clkb 0.0097
|
||||
icap_cenb 0.0013
|
||||
icap_ab 0.0016
|
||||
icap_db 0.0019
|
||||
icap_emaa 0.0058
|
||||
icap_emasa 0.0025
|
||||
icap_emab 0.0056
|
||||
icap_tena 0.0009
|
||||
icap_tcena 0.0014
|
||||
icap_taa 0.0015
|
||||
icap_tenb 0.0010
|
||||
icap_tcenb 0.0014
|
||||
icap_tab 0.0016
|
||||
icap_tdb 0.0016
|
||||
icap_sia 0.0012
|
||||
icap_sea 0.0016
|
||||
icap_dftrambyp 0.0021
|
||||
icap_sib 0.0058
|
||||
icap_seb 0.0019
|
||||
icap_colldisn 0.0021
|
||||
icap_ret1n 0.0034
|
||||
# High Density Two Port Register File SVT MVT Compiler : current specific information.
|
||||
icc_standby_c_chipdisable 2.509e-03
|
||||
icc_standby_p_chipdisable 4.157e-03
|
||||
icc_standby_c_ret1 2.485e-03
|
||||
icc_standby_p_ret1 2.581e-04
|
||||
icc_standby_c_selective_precharge 2.359e-03
|
||||
icc_standby_p_selective_precharge 3.484e-03
|
||||
icc_c_rd0_a 4.765e-05
|
||||
icc_c_rd1_a 4.772e-05
|
||||
icc_c_rd2_a 4.774e-05
|
||||
icc_c_rd3_a 4.785e-05
|
||||
icc_c_rd4_a 4.785e-05
|
||||
icc_c_rd5_a 4.785e-05
|
||||
icc_c_rd6_a 4.815e-05
|
||||
icc_c_rd7_a 4.815e-05
|
||||
icc_p_rd0_a 8.911e-04
|
||||
icc_p_rd1_a 8.963e-04
|
||||
icc_p_rd2_a 8.981e-04
|
||||
icc_p_rd3_a 8.996e-04
|
||||
icc_p_rd4_a 9.379e-04
|
||||
icc_p_rd5_a 9.702e-04
|
||||
icc_p_rd6_a 1.001e-03
|
||||
icc_p_rd7_a 1.021e-03
|
||||
icc_c_wr0_b 5.690e-05
|
||||
icc_c_wr1_b 5.698e-05
|
||||
icc_c_wr2_b 5.700e-05
|
||||
icc_c_wr3_b 5.711e-05
|
||||
icc_c_wr4_b 5.711e-05
|
||||
icc_c_wr5_b 5.711e-05
|
||||
icc_c_wr6_b 5.740e-05
|
||||
icc_c_wr7_b 5.740e-05
|
||||
icc_p_wr0_b 1.071e-03
|
||||
icc_p_wr1_b 1.076e-03
|
||||
icc_p_wr2_b 1.078e-03
|
||||
icc_p_wr3_b 1.079e-03
|
||||
icc_p_wr4_b 1.117e-03
|
||||
icc_p_wr5_b 1.150e-03
|
||||
icc_p_wr6_b 1.181e-03
|
||||
icc_p_wr7_b 1.201e-03
|
||||
icc_c_desela 0.000e+00
|
||||
icc_p_desela 8.948e-05
|
||||
icc_c_deselb 0.000e+00
|
||||
icc_p_deselb 1.510e-04
|
||||
icc_c_peak 2.632617
|
||||
icc_p_peak 17.150574
|
||||
icc_c_inrush 2.507255
|
||||
icc_p_inrush 16.33388
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user