wgulian3
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f2c0453702
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Add multi-cycle compat module and use it in ALU
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2020-02-21 22:08:09 -05:00 |
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wgulian3
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83d1f54fcf
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fix shared mem ram inference
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2020-02-20 15:59:23 -05:00 |
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wgulian3
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55d722364d
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Merge branch 'fpga_synthesis' into fix_cache_m10k
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2020-02-20 02:36:39 -05:00 |
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codetector
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e82e29c855
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remove async reset for FPGA synthesis
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2020-02-19 23:19:05 -05:00 |
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wgulian3
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de85cfd296
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fix clean build with makefile
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2020-02-19 17:33:51 -05:00 |
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Codetector
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072c89c433
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Merge branch 'fpga_synthesis' into fix_cache_m10k
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2020-02-19 16:03:23 -05:00 |
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wgulian3
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5dadeffac8
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fix project.tcl
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2020-02-19 14:20:58 -05:00 |
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wgulian3
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3b60c10460
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Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis
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2020-02-19 01:04:55 -05:00 |
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wgulian3
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3423e3189f
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Fix e2e building issues and increase division pipeline length
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2020-02-19 01:04:48 -05:00 |
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wgulian3
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3e68c8bcf5
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verilator does not support delayed assignment in a loop
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2020-02-18 13:38:17 -05:00 |
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wgulian3
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e76d05f7ce
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Fix issues quartus synthesis issues
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2020-02-18 13:24:18 -05:00 |
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wgulian3
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d71f8fcc73
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Fix divide edge case in verilator and move divide modules out of SYN_FUNC block within alu.
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2020-02-18 13:02:46 -05:00 |
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wgulian3
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a32d654263
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Merge branch 'master' into fpga_synthesis
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2020-02-18 03:35:12 -05:00 |
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wgulian3
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61803741f8
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Merge branch 'master' into fpga_synthesis
# Conflicts:
# rtl/VX_back_end.v
# rtl/VX_gpr_stage.v
# rtl/VX_writeback.v
# rtl/simulate/test_bench.cpp
# rtl/simulate/test_bench.h
# runtime/mains/dev/Makefile
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2020-02-18 03:34:38 -05:00 |
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felsabbagh3
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28ce40eebf
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fixed make w + vx_gpr_stage csr schedule
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2020-02-18 00:26:44 -08:00 |
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felsabbagh3
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be66e51613
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Added CSRs, some Load unit tests are failing
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2020-02-17 22:22:27 -08:00 |
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felsabbagh3
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a0f3f67426
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Fixed double printing in ::io_handler
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2020-02-17 19:47:55 -08:00 |
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felsabbagh3
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3a45375596
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Fixed Verilator
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2020-02-17 19:36:00 -08:00 |
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wgulian3
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4184980188
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verilator: run all riscv tests
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2020-02-13 13:50:57 -05:00 |
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wgulian3
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e662ef4134
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Fix verilator
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2020-02-13 13:42:43 -05:00 |
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wgulian3
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86bfa4d1e4
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Fix verilator
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2020-02-13 13:18:06 -05:00 |
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wgulian3
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8318aff69f
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Support exec multi-cycle for div/mul
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2020-02-13 13:17:46 -05:00 |
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codetector
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ded06bcd12
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ram m10k fix
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2020-02-11 09:57:32 -05:00 |
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wgulian3
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c1bd731d7f
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Add ram async clear port fix for fpga RAM inference
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2020-02-06 13:07:50 -05:00 |
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wgulian3
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9c7a9d88cf
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Replace div/rem expressions with divider modules in preparation for pipelining
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2020-02-04 11:54:06 -05:00 |
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wgulian3
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0211ca4add
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Add compat divide module and tb
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2020-02-04 10:59:05 -05:00 |
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wgulian3
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8d20b52ea2
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Cleanup imports of VX_define
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2020-02-04 10:57:32 -05:00 |
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wgulian3
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d727404f3b
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timing analysis tcl
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2020-01-28 04:09:00 -05:00 |
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wgulian3
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4158b29f29
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Fancier SDC file
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2020-01-28 02:20:13 -05:00 |
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wgulian3
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a6e74f589e
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Update files
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2020-01-27 20:35:45 -05:00 |
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wgulian3
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12a4136464
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quartus makefile: Support custom Quartus root location
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2020-01-24 18:42:03 -05:00 |
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wgulian3
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e9cdc6e5af
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SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
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2020-01-24 06:10:24 -05:00 |
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Lyons, Ethan Tyler
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b583e206a2
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Fixed GPR Stage to be Generic when ASIC is defined
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2019-11-22 09:20:20 -05:00 |
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fares
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9e58bf8fb5
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Started synthesis script
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2019-11-22 00:32:19 -05:00 |
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fares
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d4f6a7e3b2
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reverted to 4 thread configuration
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2019-11-22 00:13:55 -05:00 |
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fares
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8acc32372b
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8Warp 32Threads for GTCAD synthesis
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2019-11-21 23:51:11 -05:00 |
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fares
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c4d315dfed
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VCD for power
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2019-11-21 23:25:51 -05:00 |
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Lyons, Ethan Tyler
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c8abd48458
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Synthesis Compatible
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2019-11-21 21:42:34 -05:00 |
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Lyons, Ethan Tyler
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b748a7665d
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Synthesis Compatible
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2019-11-21 21:41:41 -05:00 |
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Lyons, Ethan Tyler
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e56e42c8c3
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Synthesis Compatible
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2019-11-21 21:41:11 -05:00 |
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Lyons, Ethan Tyler
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52e881243e
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Warps/Threads Parameterization
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2019-11-21 01:15:54 -05:00 |
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Lyons, Ethan Tyler
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9f58584207
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Warps/Threads Parameterization
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2019-11-21 01:15:21 -05:00 |
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Lyons, Ethan Tyler
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509850192c
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Warps/Threads Parameterization
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2019-11-21 01:14:50 -05:00 |
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fares
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c09a15069b
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Improving critical path
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2019-11-18 13:11:05 -05:00 |
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fares
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c6d56f11c3
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Added EXEC to Warp Scheduler buffer
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2019-11-18 11:34:51 -05:00 |
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fares
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53c78b905a
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Switched to g++
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2019-11-16 12:23:59 -05:00 |
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fares
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19dba43849
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vecadd bug fixing + ebreak for termination
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2019-11-15 14:18:45 -05:00 |
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fares
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3d5120640b
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clCreateProgramWithBuiltInKernels OpenCL Error
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2019-11-15 01:14:31 -05:00 |
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felsabbagh3
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70651f0340
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Added a pipeline stage + fixed SM param errors
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2019-11-13 12:25:28 -05:00 |
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Lyons, Ethan Tyler
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7f7d17d176
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Shared Memory Implemented
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2019-11-13 10:06:36 -05:00 |
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