Switched to g++
This commit is contained in:
8
rtl/cache/VX_cache_data.v
vendored
8
rtl/cache/VX_cache_data.v
vendored
@@ -139,11 +139,11 @@ module VX_cache_data
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.EMAB(3'b011),
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.TENA(1'b1),
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.TCENA(1'b0),
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.TAA(8'b0),
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.TAA(5'b0),
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.TENB(1'b1),
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.TCENB(1'b0),
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.TWENB(128'b0),
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.TAB(8'b0),
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.TAB(5'b0),
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.TDB(128'b0),
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.RET1N(1'b1),
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.SIA(2'b0),
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@@ -211,11 +211,11 @@ module VX_cache_data
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.EMAB(3'b011),
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.TENA(1'b1),
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.TCENA(1'b0),
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.TAA(8'b0),
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.TAA(5'b0),
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.TENB(1'b1),
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.TCENB(1'b0),
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// .TWENB(128'b0),
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.TAB(8'b0),
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.TAB(5'b0),
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.TDB(19'b0),
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.RET1N(1'b1),
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.SIA(2'b0),
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@@ -57,13 +57,13 @@ module VX_shared_memory_block
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wire cena = 0;
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wire cenb = !shm_write;
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//wire[3:0][31:0] write_bit_mask;
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wire[3:0][31:0] write_bit_mask;
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//assign write_bit_mask[0] = (we == 2'b00) ? {32{1'b1}} : {32{1'b0}};
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//assign write_bit_mask[1] = (we == 2'b01) ? {32{1'b1}} : {32{1'b0}};
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//assign write_bit_mask[2] = (we == 2'b10) ? {32{1'b1}} : {32{1'b0}};
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//assign write_bit_mask[3] = (we == 2'b11) ? {32{1'b1}} : {32{1'b0}};
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integer curr_word;
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genvar curr_word;
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for (curr_word = 0; curr_word < SMB_WORDS_PER_READ; curr_word = curr_word + 1)
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begin
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assign write_bit_mask[curr_word] = (we == curr_word) ? 1 : {32{1'b0}};
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