Blaise Tine
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7d01be367c
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reset network refactoring
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2021-07-15 11:34:55 -07:00 |
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22cf698e69
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minor update
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2021-07-13 05:25:44 -07:00 |
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10e9ee124b
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using onehot multiplexer to reduce critical path
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2021-07-08 00:26:59 -07:00 |
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dc34c5c5bd
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minor update
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2021-07-03 04:47:19 -07:00 |
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93fee18d59
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minor update
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2021-07-01 02:59:44 -07:00 |
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1ea738ed26
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lkg build
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2021-06-25 16:28:10 -07:00 |
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a3a7239b4d
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critical path optimizations
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2021-06-23 01:51:23 -07:00 |
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b8fd2308e1
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arbiter specialization
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2021-06-22 21:02:37 -07:00 |
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57143f5889
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synthesis optimizations
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2021-06-17 16:43:43 -07:00 |
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47c3234659
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minor update
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2021-06-13 10:58:48 -07:00 |
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adf033b0aa
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non-cacheable memory address critical paths optimizations
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2021-06-10 12:47:18 -07:00 |
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aff5903a22
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minor ibuffer critical path optimization.
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2021-04-19 20:53:13 -07:00 |
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16bef8937b
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adding empty to index_buffer
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2021-03-30 10:15:42 -07:00 |
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b33a994f49
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minor update
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2021-03-29 23:51:05 -07:00 |
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bd40e7db70
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minor update - mux reordering to reduce critical path on input data
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2021-03-21 11:43:57 -07:00 |
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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3f5fd6d394
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using shiftreg-based skid buffers
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2021-02-28 02:20:09 -08:00 |
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Blaise Tine
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ebee332e9d
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minor update
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2021-02-27 02:31:05 -08:00 |
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Blaise Tine
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20d704b4d3
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skid buffer optimization
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2021-02-27 02:29:48 -08:00 |
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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143319d557
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minor optimization
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2021-02-18 16:03:16 -08:00 |
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Blaise Tine
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073964fdf7
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minor update
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2021-02-12 08:52:06 -08:00 |
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Blaise Tine
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72b6713a72
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updating fdiv/fsqrt bram hex files, reset_delay updaet
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2021-02-04 09:02:18 -08:00 |
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5419859281
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fcvt fix
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2021-01-25 02:22:00 -08:00 |
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Blaise Tine
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8775f63ec4
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lkg build rollout with 16cores optimization on arria10
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2021-01-24 16:49:22 -08:00 |
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Blaise Tine
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a046bd7a73
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cache pipeline optimization
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2021-01-17 17:19:52 -08:00 |
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Blaise Tine
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ed216ab39d
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minor updates
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2021-01-17 13:58:43 -08:00 |
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Blaise Tine
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d4e7b28be8
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cache refactoring
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2021-01-17 00:18:56 -08:00 |
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ad6e0b4e77
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sp_ram byteen fix
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2021-01-15 16:28:03 -08:00 |
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fe64c47f60
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ccip write fix
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2021-01-14 22:49:06 -08:00 |
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Blaise Tine
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b4b5d6f0ab
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minor updates
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2021-01-12 15:19:38 -08:00 |
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Blaise Tine
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ceae724207
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minor updates
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2021-01-12 11:24:36 -08:00 |
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Blaise Tine
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7e93d253f2
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minor update
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2021-01-10 22:03:23 -08:00 |
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Blaise Tine
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e770824d47
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fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance
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2021-01-10 20:26:15 -08:00 |
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Blaise Tine
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06945533cf
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fixed l2/l3 caches related bugs
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2021-01-09 16:32:55 -08:00 |
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Blaise Tine
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5c83c594c1
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minor update
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2021-01-07 17:25:59 -08:00 |
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Blaise Tine
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146c285aa0
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minor update
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2021-01-06 19:59:04 -08:00 |
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Blaise Tine
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2b8435471a
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speeding up simulation using dedicated full dpi-based FPU core
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2021-01-06 18:44:06 -08:00 |
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Blaise Tine
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39bff921be
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cache bug fixes
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2021-01-05 05:04:49 -08:00 |
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Blaise Tine
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4815ab099c
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using single-port block ram for cache tags, restoring core reset signal
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2021-01-02 19:53:41 -08:00 |
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Blaise Tine
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da9649c2a3
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fixed pipe register reset issue in synthesis
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2021-01-01 14:54:18 -08:00 |
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Blaise Tine
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36602cfa6a
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buffering core reset signal
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2021-01-01 11:46:30 -08:00 |
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Blaise Tine
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d44144f72f
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FPU float<->int conversion optimization
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2020-12-29 15:37:45 -08:00 |
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Blaise Tine
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b2b8f190dd
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minor update
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2020-12-26 14:47:41 -08:00 |
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Blaise Tine
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33c431ed44
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multiplier unit optimization - using fifo for metadata, shift register optimization
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2020-12-26 11:23:21 -08:00 |
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Blaise Tine
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b459192dec
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critical path optimization - fpga fmax @4c = ~212 mhz
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2020-12-26 03:28:32 -08:00 |
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Blaise Tine
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4b7d871d62
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allowing partial cache request submissions, io bus support broken
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2020-12-21 03:53:13 -08:00 |
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Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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3e9abb978b
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fixed typo
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2020-12-09 13:03:22 -08:00 |
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Blaise Tine
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e0905f8352
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minor update
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2020-12-09 05:34:27 -08:00 |
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