fixed typo

hw/rtl/VX_instr_demux.v

@@ -36,7 +36,7 @@ module VX_instr_demux (
 
     VX_skid_buffer #(
         .DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BR_BITS + 1 + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)),
-        .REGISTER (1) // ALU has no back pressure, use a simple register
+        .NOBACKPRESSURE (1) // ALU has no back pressure
     ) alu_buffer (
         .clk       (clk),
         .reset     (reset),

hw/rtl/libs/VX_skid_buffer.v

@@ -1,9 +1,9 @@
 `include "VX_platform.vh"
 
 module VX_skid_buffer #(
-    parameter DATAW    = 1,
-    parameter PASSTHRU = 0,
-    parameter REGISTER = 0
+    parameter DATAW          = 1,
+    parameter PASSTHRU       = 0,
+    parameter NOBACKPRESSURE = 0
 ) ( 
     input  wire             clk,
     input  wire             reset,
@@ -26,7 +26,11 @@ module VX_skid_buffer #(
         assign data_out  = data_in;
         assign ready_in  = ready_out;
 
-    end if (REGISTER) begin
+    end else if (NOBACKPRESSURE) begin
+
+        always @(posedge clk) begin
+            assert(ready_out) else $error("ready_out should always be asserted");
+        end
 
         wire stall = valid_out && ~ready_out;