fixed pipe register reset issue in synthesis

hw/rtl/VX_cluster.v

@@ -67,20 +67,14 @@ module VX_cluster #(
     wire [`NUM_CORES-1:0]                        per_core_busy;
     wire [`NUM_CORES-1:0]                        per_core_ebreak;
 
-    for (genvar i = 0; i < `NUM_CORES; i++) begin    
-    
-        reg core_reset;
-        always @(posedge clk) begin
-            core_reset <= reset;
-        end
-
+    for (genvar i = 0; i < `NUM_CORES; i++) begin
         VX_core #(
             .CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
         ) core (
             `SCOPE_BIND_VX_cluster_core(i)
 
             .clk            (clk),
-            .reset          (core_reset),
+            .reset          (reset),
 
             .dram_req_valid (per_core_dram_req_valid[i]),
             .dram_req_rw    (per_core_dram_req_rw   [i]),                

hw/rtl/libs/VX_pipe_register.v

@@ -17,7 +17,7 @@ module VX_pipe_register #(
         `UNUSED_VAR (reset)
         `UNUSED_VAR (enable)
         assign data_out = data_in;  
-    end else if (DEPTH == 1) begin   
+    end else if (DEPTH == 1) begin        
         if (RESETW == 0) begin
             `UNUSED_VAR (reset)
             reg [DATAW-1:0] value;
@@ -39,7 +39,7 @@ module VX_pipe_register #(
                 end
             end
             assign data_out = value;
-        end else begin            
+        end else begin
             reg [DATAW-RESETW-1:0] value_d;
             reg [RESETW-1:0]       value_r;
 
@@ -49,6 +49,9 @@ module VX_pipe_register #(
                 end else if (enable) begin
                     value_r <= data_in[DATAW-1:DATAW-RESETW];
                 end
+            end
+
+            always @(posedge clk) begin
                 if (enable) begin
                     value_d <= data_in[DATAW-RESETW-1:0];
                 end