felsabbagh3
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ad45758a35
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Before Fetch->FE
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2019-09-08 18:09:11 -04:00 |
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felsabbagh3
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c310e7381f
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Icache interface
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2019-09-08 17:36:09 -04:00 |
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felsabbagh3
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fe09aafbb4
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Interface Checkpoint 2 - Remove Lints
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2019-09-05 19:32:37 -04:00 |
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felsabbagh3
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2d0e41db63
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checkpoint: Added icache struct
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2019-09-03 16:19:06 -04:00 |
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felsabbagh3
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b216da5a6a
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ram stdint + Quartus Files
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2019-06-11 21:13:30 -07:00 |
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felsabbagh3
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d7afef04a9
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Sim Work miss
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2019-05-18 23:42:55 +04:00 |
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felsabbagh3
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48468ed26a
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Proper SIMT with fine-grain scheduler implemented
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2019-05-10 00:49:54 -07:00 |
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felsabbagh3
|
96dac5e1ce
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Warp + Context Aware Design - Global Stalling
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2019-05-08 16:32:49 -07:00 |
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felsabbagh3
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a6c13bc38c
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Inefficient context aware desgin
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2019-05-08 15:55:06 -07:00 |
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felsabbagh3
|
79356c7ab1
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Changed hierarchy + Identified private + public modules
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2019-05-07 23:45:05 -07:00 |
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felsabbagh3
|
191ed73415
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Less expensive but slower fetch logic
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2019-05-05 22:55:47 -04:00 |
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felsabbagh3
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8c2ae97510
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1 WARP 8 THREADS TESTED + FULLY WORKING
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2019-03-31 05:21:00 -04:00 |
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felsabbagh3
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c83ef94d02
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1 WARP 2 THREADS WORKING
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2019-03-31 05:02:55 -04:00 |
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felsabbagh3
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4aac33b298
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Using verilog For-loops + Passing all tests
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2019-03-30 22:55:13 -04:00 |
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felsabbagh3
|
52a839f84d
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Using verilog For-loops + Passing all tests
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2019-03-30 22:14:44 -04:00 |
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felsabbagh3
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99a0792a0c
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Passing all tests with 2 threads
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2019-03-30 03:54:20 -04:00 |
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felsabbagh3
|
d02c3d25b7
|
sync
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2019-03-27 13:52:13 -04:00 |
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felsabbagh3
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68f3ba84e5
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Added HW threads - Infinite loop + fixed valid
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2019-03-27 03:53:59 -04:00 |
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felsabbagh3
|
9b42e79dcf
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Added HW threads - Infinite loop
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2019-03-27 03:44:14 -04:00 |
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felsabbagh3
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01d142c6e6
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rtl passing all tests
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2019-03-22 02:44:53 -04:00 |
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felsabbagh3
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d08d389177
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Started on rtl (Finished till decode)
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2019-03-21 02:23:10 -04:00 |
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