Interface Checkpoint 2 - Remove Lints
This commit is contained in:
felsabbagh3
@@ -1,11 +1,9 @@
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all: RUNFILE
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VERILATOR:
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verilator -Wall -cc Vortex.v --exe test_bench.cpp -CFLAGS -std=c++11
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verilator --compiler gcc -Wall -cc Vortex.v -Iinterfaces/ --exe test_bench.cpp -CFLAGS -std=c++11
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RUNFILE: VERILATOR
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(cd obj_dir && make -j -f VVortex.mk)
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@@ -7,24 +7,24 @@ module VX_context (
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input wire in_warp,
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/* verilator lint_on UNUSED */
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input wire in_wb_warp,
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input wire in_valid[`NT_M1:0],
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input wire[`NT_M1:0] in_valid,
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input wire in_write_register,
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input wire[4:0] in_rd,
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input wire[31:0] in_write_data[`NT_M1:0],
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input wire[`NT_M1:0][31:0] in_write_data,
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input wire[4:0] in_src1,
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input wire[4:0] in_src2,
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input wire[31:0] in_curr_PC,
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input wire in_is_clone,
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input wire in_is_jal,
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input wire in_src1_fwd,
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input wire[31:0] in_src1_fwd_data[`NT_M1:0],
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input wire[`NT_M1:0][31:0] in_src1_fwd_data,
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input wire in_src2_fwd,
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input wire[31:0] in_src2_fwd_data[`NT_M1:0],
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input wire[`NT_M1:0][31:0] in_src2_fwd_data,
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output reg[31:0] out_a_reg_data[`NT_M1:0],
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output reg[31:0] out_b_reg_data[`NT_M1:0],
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output reg[`NT_M1:0][31:0] out_a_reg_data,
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output reg[`NT_M1:0][31:0] out_b_reg_data,
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output wire out_clone_stall,
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output wire[31:0] w0_t0_registers[31:0]
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output wire[31:0][31:0] w0_t0_registers
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);
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reg[5:0] state_stall;
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@@ -32,10 +32,10 @@ module VX_context (
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state_stall = 0;
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end
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wire[31:0] rd1_register[`NT_M1:0];
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wire[31:0] rd2_register[`NT_M1:0];
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wire[`NT_M1:0][31:0] rd1_register;
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wire[`NT_M1:0][31:0] rd2_register;
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/* verilator lint_off UNUSED */
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wire[31:0] clone_regsiters[31:0];
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wire[31:0][31:0] clone_regsiters;
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/* verilator lint_on UNUSED */
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assign w0_t0_registers = clone_regsiters;
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@@ -7,31 +7,31 @@ module VX_context_slave (
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input wire in_warp,
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/* verilator lint_on UNUSED */
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input wire in_wb_warp,
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input wire in_valid[`NT_M1:0],
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input wire[`NT_M1:0] in_valid,
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input wire in_write_register,
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input wire[4:0] in_rd,
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input wire[31:0] in_write_data[`NT_M1:0],
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input wire[`NT_M1:0][31:0] in_write_data,
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input wire[4:0] in_src1,
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input wire[4:0] in_src2,
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input wire[31:0] in_curr_PC,
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input wire in_is_clone,
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input wire in_is_jal,
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input wire in_src1_fwd,
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input wire[31:0] in_src1_fwd_data[`NT_M1:0],
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input wire[`NT_M1:0][31:0] in_src1_fwd_data,
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input wire in_src2_fwd,
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input wire[31:0] in_src2_fwd_data[`NT_M1:0],
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input wire[31:0] in_wspawn_regs[31:0],
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input wire[`NT_M1:0][31:0] in_src2_fwd_data,
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input wire[31:0][31:0] in_wspawn_regs,
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input wire in_wspawn,
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output reg[31:0] out_a_reg_data[`NT_M1:0],
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output reg[31:0] out_b_reg_data[`NT_M1:0],
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output reg[`NT_M1:0][31:0] out_a_reg_data,
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output reg[`NT_M1:0][31:0] out_b_reg_data,
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output wire out_clone_stall
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);
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wire[31:0] rd1_register[`NT_M1:0];
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wire[31:0] rd2_register[`NT_M1:0];
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wire[`NT_M1:0][31:0] rd1_register;
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wire[`NT_M1:0][31:0] rd2_register;
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/* verilator lint_off UNUSED */
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wire[31:0] clone_regsiters[31:0];
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wire[31:0][31:0] clone_regsiters;
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/* verilator lint_on UNUSED */
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311
rtl/VX_d_e_reg.v
311
rtl/VX_d_e_reg.v
@@ -3,171 +3,164 @@
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`include "VX_define.v"
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module VX_d_e_reg (
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input wire clk,
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input wire[4:0] in_rd,
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input wire[4:0] in_rs1,
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input wire[4:0] in_rs2,
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input wire[31:0] in_a_reg_data[`NT_M1:0],
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input wire[31:0] in_b_reg_data[`NT_M1:0],
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input wire[4:0] in_alu_op,
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input wire[1:0] in_wb,
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input wire in_rs2_src, // NEW
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input wire[31:0] in_itype_immed, // new
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input wire[2:0] in_mem_read, // NEW
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input wire[2:0] in_mem_write,
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input wire[31:0] in_PC_next,
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input wire[2:0] in_branch_type,
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input wire in_fwd_stall,
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input wire in_branch_stall,
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input wire[19:0] in_upper_immed,
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input wire[11:0] in_csr_address, // done
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input wire in_is_csr, // done
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input wire[31:0] in_csr_mask, // done
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input wire[31:0] in_curr_PC,
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input wire in_jal,
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input wire[31:0] in_jal_offset,
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input wire in_freeze,
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input wire in_clone_stall,
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input wire in_valid[`NT_M1:0],
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input wire[`NW_M1:0] in_warp_num,
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input wire clk,
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input wire reset,
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input wire in_fwd_stall,
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input wire in_branch_stall,
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input wire in_freeze,
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input wire in_clone_stall,
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VX_frE_to_bckE_req_inter VX_frE_to_bckE_req,
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output wire[11:0] out_csr_address, // done
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output wire out_is_csr, // done
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output wire[31:0] out_csr_mask, // done
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output wire[4:0] out_rd,
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output wire[4:0] out_rs1,
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output wire[4:0] out_rs2,
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output wire[31:0] out_a_reg_data[`NT_M1:0],
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output wire[31:0] out_b_reg_data[`NT_M1:0],
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output wire[4:0] out_alu_op,
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output wire[1:0] out_wb,
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output wire out_rs2_src, // NEW
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output wire[31:0] out_itype_immed, // new
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output wire[2:0] out_mem_read,
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output wire[2:0] out_mem_write,
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output wire[2:0] out_branch_type,
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output wire[19:0] out_upper_immed,
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output wire[31:0] out_curr_PC,
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output wire out_jal,
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output wire[31:0] out_jal_offset,
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output wire[31:0] out_PC_next,
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output wire out_valid[`NT_M1:0],
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output wire[`NW_M1:0] out_warp_num
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VX_frE_to_bckE_req_inter VX_bckE_req
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);
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reg[4:0] rd;
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reg[4:0] rs1;
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reg[4:0] rs2;
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reg[31:0] a_reg_data[`NT_M1:0];
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reg[31:0] b_reg_data[`NT_M1:0];
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reg[4:0] alu_op;
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reg[1:0] wb;
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reg[31:0] PC_next_out;
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reg rs2_src;
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reg[31:0] itype_immed;
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reg[2:0] mem_read;
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reg[2:0] mem_write;
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reg[2:0] branch_type;
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reg[19:0] upper_immed;
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reg[11:0] csr_address;
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reg is_csr;
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reg[31:0] csr_mask;
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reg[31:0] curr_PC;
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reg jal;
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reg[31:0] jal_offset;
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reg valid[`NT_M1:0];
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reg[31:0] reg_data_z[`NT_M1:0];
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reg valid_z[`NT_M1:0];
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reg[`NW_M1:0] warp_num;
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integer ini_reg;
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initial begin
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rd = 0;
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rs1 = 0;
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for (ini_reg = 0; ini_reg < `NT; ini_reg = ini_reg + 1)
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begin
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a_reg_data[ini_reg] = 0;
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b_reg_data[ini_reg] = 0;
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reg_data_z[ini_reg] = 0;
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valid[ini_reg] = 0;
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valid_z[ini_reg] = 0;
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end
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rs2 = 0;
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alu_op = 0;
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wb = `NO_WB;
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PC_next_out = 0;
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rs2_src = 0;
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itype_immed = 0;
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mem_read = `NO_MEM_READ;
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mem_write = `NO_MEM_WRITE;
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branch_type = `NO_BRANCH;
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upper_immed = 0;
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csr_address = 0;
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is_csr = 0;
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csr_mask = 0;
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curr_PC = 0;
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jal = `NO_JUMP;
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jal_offset = 0;
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warp_num = 0;
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end
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wire stalling;
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assign stalling = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL) || (in_clone_stall == `STALL);
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assign out_rd = rd;
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assign out_rs1 = rs1;
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assign out_rs2 = rs2;
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assign out_a_reg_data = a_reg_data;
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assign out_b_reg_data = b_reg_data;
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assign out_alu_op = alu_op;
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assign out_wb = wb;
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assign out_PC_next = PC_next_out;
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assign out_rs2_src = rs2_src;
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assign out_itype_immed = itype_immed;
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assign out_mem_read = mem_read;
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assign out_mem_write = mem_write;
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assign out_branch_type = branch_type;
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assign out_upper_immed = upper_immed;
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assign out_csr_address = csr_address;
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assign out_is_csr = is_csr;
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assign out_csr_mask = csr_mask;
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assign out_jal = jal;
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assign out_jal_offset = jal_offset;
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assign out_curr_PC = curr_PC;
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assign out_valid = valid;
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assign out_warp_num = warp_num;
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wire stall = in_freeze;
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wire flush = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL) || (in_clone_stall == `STALL);
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always @(posedge clk) begin
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if (in_freeze == 1'h0) begin
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rd <= stalling ? 5'h0 : in_rd;
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rs1 <= stalling ? 5'h0 : in_rs1;
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rs2 <= stalling ? 5'h0 : in_rs2;
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a_reg_data <= stalling ? reg_data_z : in_a_reg_data;
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b_reg_data <= stalling ? reg_data_z : in_b_reg_data;
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alu_op <= stalling ? `NO_ALU : in_alu_op;
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wb <= stalling ? `NO_WB : in_wb;
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PC_next_out <= stalling ? 32'h0 : in_PC_next;
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rs2_src <= stalling ? `RS2_REG : in_rs2_src;
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itype_immed <= stalling ? 32'hdeadbeef : in_itype_immed;
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mem_read <= stalling ? `NO_MEM_READ : in_mem_read;
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mem_write <= stalling ? `NO_MEM_WRITE: in_mem_write;
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branch_type <= stalling ? `NO_BRANCH : in_branch_type;
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upper_immed <= stalling ? 20'h0 : in_upper_immed;
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csr_address <= stalling ? 12'h0 : in_csr_address;
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is_csr <= stalling ? 1'h0 : in_is_csr;
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csr_mask <= stalling ? 32'h0 : in_csr_mask;
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jal <= stalling ? `NO_JUMP : in_jal;
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jal_offset <= stalling ? 32'h0 : in_jal_offset;
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curr_PC <= stalling ? 32'h0 : in_curr_PC;
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valid <= stalling ? valid_z : in_valid;
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warp_num <= stalling ? 0 : in_warp_num;
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end
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end
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VX_generic_register #(.N(490)) d_e_reg
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(
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.clk (clk),
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.reset(reset),
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.stall(stall),
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.flush(flush),
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.in ({VX_frE_to_bckE_req.csr_address, VX_frE_to_bckE_req.is_csr, VX_frE_to_bckE_req.csr_mask, VX_frE_to_bckE_req.rd, VX_frE_to_bckE_req.rs1, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.a_reg_data, VX_frE_to_bckE_req.b_reg_data, VX_frE_to_bckE_req.alu_op, VX_frE_to_bckE_req.wb, VX_frE_to_bckE_req.rs2_src, VX_frE_to_bckE_req.itype_immed, VX_frE_to_bckE_req.mem_read, VX_frE_to_bckE_req.mem_write, VX_frE_to_bckE_req.branch_type, VX_frE_to_bckE_req.upper_immed, VX_frE_to_bckE_req.curr_PC, VX_frE_to_bckE_req.jal, VX_frE_to_bckE_req.jal_offset, VX_frE_to_bckE_req.PC_next, VX_frE_to_bckE_req.valid, VX_frE_to_bckE_req.warp_num}),
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.out ({VX_bckE_req.csr_address , VX_bckE_req.is_csr , VX_bckE_req.csr_mask , VX_bckE_req.rd , VX_bckE_req.rs1 , VX_bckE_req.rs2 , VX_bckE_req.a_reg_data , VX_bckE_req.b_reg_data , VX_bckE_req.alu_op , VX_bckE_req.wb , VX_bckE_req.rs2_src , VX_bckE_req.itype_immed , VX_bckE_req.mem_read , VX_bckE_req.mem_write , VX_bckE_req.branch_type , VX_bckE_req.upper_immed , VX_bckE_req.curr_PC , VX_bckE_req.jal , VX_bckE_req.jal_offset , VX_bckE_req.PC_next , VX_bckE_req.valid , VX_bckE_req.warp_num})
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);
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// wire[`NT_M1:0][31:0] temp_out_a_reg_data;
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// wire[`NT_M1:0][31:0] temp_out_b_reg_data;
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// wire[`NT_M1:0] temp_out_valid;
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// genvar index;
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// for (index = 0; index <= `NT_M1; index = index + 1) begin
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// assign out_valid[index] = temp_out_valid[index];
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// assign out_a_reg_data[index] = temp_out_a_reg_data[index];
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// assign out_b_reg_data[index] = temp_out_b_reg_data[index];
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// end
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// reg[4:0] rd;
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// reg[4:0] rs1;
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// reg[4:0] rs2;
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// reg[31:0] a_reg_data[`NT_M1:0];
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// reg[31:0] b_reg_data[`NT_M1:0];
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// reg[4:0] alu_op;
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// reg[1:0] wb;
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// reg[31:0] PC_next_out;
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// reg rs2_src;
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// reg[31:0] itype_immed;
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// reg[2:0] mem_read;
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// reg[2:0] mem_write;
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// reg[2:0] branch_type;
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// reg[19:0] upper_immed;
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// reg[11:0] csr_address;
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// reg is_csr;
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// reg[31:0] csr_mask;
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// reg[31:0] curr_PC;
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// reg jal;
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// reg[31:0] jal_offset;
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// reg valid[`NT_M1:0];
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// reg[31:0] reg_data_z[`NT_M1:0];
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// reg valid_z[`NT_M1:0];
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// reg[`NW_M1:0] warp_num;
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// integer ini_reg;
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// initial begin
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// rd = 0;
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// rs1 = 0;
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// for (ini_reg = 0; ini_reg < `NT; ini_reg = ini_reg + 1)
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// begin
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// a_reg_data[ini_reg] = 0;
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// b_reg_data[ini_reg] = 0;
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// reg_data_z[ini_reg] = 0;
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// valid[ini_reg] = 0;
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// valid_z[ini_reg] = 0;
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// end
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// rs2 = 0;
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// alu_op = 0;
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// wb = `NO_WB;
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// PC_next_out = 0;
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// rs2_src = 0;
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// itype_immed = 0;
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// mem_read = `NO_MEM_READ;
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// mem_write = `NO_MEM_WRITE;
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// branch_type = `NO_BRANCH;
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// upper_immed = 0;
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// csr_address = 0;
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// is_csr = 0;
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// csr_mask = 0;
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// curr_PC = 0;
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// jal = `NO_JUMP;
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// jal_offset = 0;
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// warp_num = 0;
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// end
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// wire stalling;
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|
||||
// assign stalling = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL) || (in_clone_stall == `STALL);
|
||||
|
||||
// Freeze stall
|
||||
// Stalling flush
|
||||
|
||||
// assign out_rd = rd;
|
||||
// assign out_rs1 = rs1;
|
||||
// assign out_rs2 = rs2;
|
||||
// assign out_a_reg_data = a_reg_data;
|
||||
// assign out_b_reg_data = b_reg_data;
|
||||
// assign out_alu_op = alu_op;
|
||||
// assign out_wb = wb;
|
||||
// assign out_PC_next = PC_next_out;
|
||||
// assign out_rs2_src = rs2_src;
|
||||
// assign out_itype_immed = itype_immed;
|
||||
// assign out_mem_read = mem_read;
|
||||
// assign out_mem_write = mem_write;
|
||||
// assign out_branch_type = branch_type;
|
||||
// assign out_upper_immed = upper_immed;
|
||||
// assign out_csr_address = csr_address;
|
||||
// assign out_is_csr = is_csr;
|
||||
// assign out_csr_mask = csr_mask;
|
||||
// assign out_jal = jal;
|
||||
// assign out_jal_offset = jal_offset;
|
||||
// assign out_curr_PC = curr_PC;
|
||||
// assign out_valid = valid;
|
||||
// assign out_warp_num = warp_num;
|
||||
|
||||
|
||||
// always @(posedge clk) begin
|
||||
// if (in_freeze == 1'h0) begin
|
||||
// rd <= stalling ? 5'h0 : in_rd;
|
||||
// rs1 <= stalling ? 5'h0 : in_rs1;
|
||||
// rs2 <= stalling ? 5'h0 : in_rs2;
|
||||
// a_reg_data <= stalling ? reg_data_z : in_a_reg_data;
|
||||
// b_reg_data <= stalling ? reg_data_z : in_b_reg_data;
|
||||
// alu_op <= stalling ? `NO_ALU : in_alu_op;
|
||||
// wb <= stalling ? `NO_WB : in_wb;
|
||||
// PC_next_out <= stalling ? 32'h0 : in_PC_next;
|
||||
// rs2_src <= stalling ? `RS2_REG : in_rs2_src;
|
||||
// itype_immed <= stalling ? 32'hdeadbeef : in_itype_immed;
|
||||
// mem_read <= stalling ? `NO_MEM_READ : in_mem_read;
|
||||
// mem_write <= stalling ? `NO_MEM_WRITE: in_mem_write;
|
||||
// branch_type <= stalling ? `NO_BRANCH : in_branch_type;
|
||||
// upper_immed <= stalling ? 20'h0 : in_upper_immed;
|
||||
// csr_address <= stalling ? 12'h0 : in_csr_address;
|
||||
// is_csr <= stalling ? 1'h0 : in_is_csr;
|
||||
// csr_mask <= stalling ? 32'h0 : in_csr_mask;
|
||||
// jal <= stalling ? `NO_JUMP : in_jal;
|
||||
// jal_offset <= stalling ? 32'h0 : in_jal_offset;
|
||||
// curr_PC <= stalling ? 32'h0 : in_curr_PC;
|
||||
// valid <= stalling ? valid_z : in_valid;
|
||||
// warp_num <= stalling ? 0 : in_warp_num;
|
||||
// end
|
||||
// end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
249
rtl/VX_decode.v
249
rtl/VX_decode.v
@@ -2,61 +2,52 @@
|
||||
`include "VX_define.v"
|
||||
|
||||
module VX_decode(
|
||||
input wire clk,
|
||||
// Fetch Inputs
|
||||
input wire clk,
|
||||
input wire[31:0] in_instruction,
|
||||
input wire[31:0] in_curr_PC,
|
||||
input wire in_valid[`NT_M1:0],
|
||||
VX_inst_meta_inter fd_inst_meta_de,
|
||||
|
||||
// WriteBack inputs
|
||||
input wire[31:0] in_write_data[`NT_M1:0],
|
||||
input wire[4:0] in_rd,
|
||||
input wire[1:0] in_wb,
|
||||
input wire in_wb_valid[`NT_M1:0],
|
||||
input wire[`NW_M1:0] in_wb_warp_num,
|
||||
VX_wb_inter VX_writeback_inter,
|
||||
|
||||
// FORWARDING INPUTS
|
||||
input wire in_src1_fwd,
|
||||
input wire[31:0] in_src1_fwd_data[`NT_M1:0],
|
||||
input wire[`NT_M1:0][31:0] in_src1_fwd_data,
|
||||
input wire in_src2_fwd,
|
||||
input wire[31:0] in_src2_fwd_data[`NT_M1:0],
|
||||
/* verilator lint_off UNUSED */
|
||||
input wire[`NT_M1:0][31:0] in_src2_fwd_data,
|
||||
input wire[`NW_M1:0] in_which_wspawn,
|
||||
/* verilator lint_on UNUSED */
|
||||
|
||||
input wire[`NW_M1:0] in_warp_num,
|
||||
|
||||
output wire[11:0] out_csr_address,
|
||||
output wire out_is_csr,
|
||||
output wire[31:0] out_csr_mask,
|
||||
|
||||
// Outputs
|
||||
output wire[4:0] out_rd,
|
||||
output wire[4:0] out_rs1,
|
||||
output wire[4:0] out_rs2,
|
||||
output wire[31:0] out_a_reg_data[`NT_M1:0],
|
||||
output wire[31:0] out_b_reg_data[`NT_M1:0],
|
||||
output wire[1:0] out_wb,
|
||||
output wire[4:0] out_alu_op,
|
||||
output wire out_rs2_src,
|
||||
output reg[31:0] out_itype_immed,
|
||||
output wire[2:0] out_mem_read,
|
||||
output wire[2:0] out_mem_write,
|
||||
output reg[2:0] out_branch_type,
|
||||
output reg out_branch_stall,
|
||||
output reg out_jal,
|
||||
output reg[31:0] out_jal_offset,
|
||||
output reg[19:0] out_upper_immed,
|
||||
output wire[31:0] out_PC_next,
|
||||
output reg out_clone_stall,
|
||||
output wire out_change_mask,
|
||||
output wire out_thread_mask[`NT_M1:0],
|
||||
output wire out_valid[`NT_M1:0],
|
||||
output wire[`NW_M1:0] out_warp_num,
|
||||
output wire out_wspawn,
|
||||
output wire[31:0] out_wspawn_pc,
|
||||
output wire out_ebreak
|
||||
VX_frE_to_bckE_req_inter VX_frE_to_bckE_req,
|
||||
VX_warp_ctl_inter VX_warp_ctl,
|
||||
output reg out_clone_stall,
|
||||
output reg out_branch_stall
|
||||
|
||||
);
|
||||
|
||||
|
||||
wire[`NT_M1:0][31:0] in_write_data;
|
||||
wire[4:0] in_rd;
|
||||
wire[1:0] in_wb;
|
||||
wire[`NT_M1:0] in_wb_valid;
|
||||
wire[`NW_M1:0] in_wb_warp_num;
|
||||
|
||||
|
||||
assign in_write_data = VX_writeback_inter.write_data;
|
||||
assign in_rd = VX_writeback_inter.rd;
|
||||
assign in_wb = VX_writeback_inter.wb;
|
||||
assign in_wb_valid = VX_writeback_inter.wb_valid;
|
||||
assign in_wb_warp_num = VX_writeback_inter.wb_warp_num;
|
||||
|
||||
wire[31:0] in_instruction = fd_inst_meta_de.instruction;
|
||||
wire[31:0] in_curr_PC = fd_inst_meta_de.inst_pc;
|
||||
wire[`NW_M1:0] in_warp_num = fd_inst_meta_de.warp_num;
|
||||
|
||||
assign VX_frE_to_bckE_req.curr_PC = in_curr_PC;
|
||||
|
||||
wire in_valid[`NT_M1:0];
|
||||
genvar index;
|
||||
for (index = 0; index <= `NT_M1; index = index + 1) assign in_valid[index] = fd_inst_meta_de.valid[index];
|
||||
|
||||
wire[6:0] curr_opcode;
|
||||
|
||||
wire is_itype;
|
||||
@@ -115,7 +106,7 @@ module VX_decode(
|
||||
reg[4:0] mul_alu;
|
||||
|
||||
/* verilator lint_off UNUSED */
|
||||
wire[31:0] w0_t0_registers[31:0];
|
||||
wire[31:0][31:0] w0_t0_registers;
|
||||
/* verilator lint_on UNUSED */
|
||||
|
||||
|
||||
@@ -144,8 +135,8 @@ module VX_decode(
|
||||
.in_wb_warp (context_zero_valid),
|
||||
.in_valid (in_wb_valid),
|
||||
.in_rd (in_rd),
|
||||
.in_src1 (out_rs1),
|
||||
.in_src2 (out_rs2),
|
||||
.in_src1 (VX_frE_to_bckE_req.rs1),
|
||||
.in_src2 (VX_frE_to_bckE_req.rs2),
|
||||
.in_curr_PC (in_curr_PC),
|
||||
.in_is_clone (real_zero_isclone),
|
||||
.in_is_jal (is_jal),
|
||||
@@ -162,15 +153,15 @@ module VX_decode(
|
||||
);
|
||||
|
||||
|
||||
assign out_a_reg_data = glob_a_reg_data;
|
||||
assign out_b_reg_data = glob_b_reg_data;
|
||||
assign VX_frE_to_bckE_req.a_reg_data = glob_a_reg_data;
|
||||
assign VX_frE_to_bckE_req.b_reg_data = glob_b_reg_data;
|
||||
assign out_clone_stall = glob_clone_stall;
|
||||
|
||||
`else
|
||||
|
||||
wire[31:0] glob_a_reg_data[`NW-1:0][`NT_M1:0];
|
||||
wire[31:0] glob_b_reg_data[`NW-1:0][`NT_M1:0];
|
||||
reg glob_clone_stall[`NW-1:0];
|
||||
wire[`NW-1:0][`NT_M1:0][31:0] glob_a_reg_data;
|
||||
wire[`NW-1:0][`NT_M1:0][31:0] glob_b_reg_data;
|
||||
reg[`NW-1:0] glob_clone_stall;
|
||||
|
||||
wire curr_warp_zero = in_warp_num == 0;
|
||||
wire context_zero_valid = (in_wb_warp_num == 0);
|
||||
@@ -181,8 +172,8 @@ module VX_decode(
|
||||
.in_wb_warp (context_zero_valid),
|
||||
.in_valid (in_wb_valid),
|
||||
.in_rd (in_rd),
|
||||
.in_src1 (out_rs1),
|
||||
.in_src2 (out_rs2),
|
||||
.in_src1 (VX_frE_to_bckE_req.rs1),
|
||||
.in_src2 (VX_frE_to_bckE_req.rs2),
|
||||
.in_curr_PC (in_curr_PC),
|
||||
.in_is_clone (real_zero_isclone),
|
||||
.in_is_jal (is_jal),
|
||||
@@ -211,8 +202,8 @@ module VX_decode(
|
||||
.in_wb_warp (context_glob_valid),
|
||||
.in_valid (in_wb_valid),
|
||||
.in_rd (in_rd),
|
||||
.in_src1 (out_rs1),
|
||||
.in_src2 (out_rs2),
|
||||
.in_src1 (VX_frE_to_bckE_req.rs1),
|
||||
.in_src2 (VX_frE_to_bckE_req.rs2),
|
||||
.in_curr_PC (in_curr_PC),
|
||||
.in_is_clone (real_isclone),
|
||||
.in_is_jal (is_jal),
|
||||
@@ -238,8 +229,8 @@ module VX_decode(
|
||||
// end
|
||||
// end
|
||||
|
||||
reg[31:0] temp_out_a_reg_data[`NT_M1:0];
|
||||
reg[31:0] temp_out_b_reg_data[`NT_M1:0];
|
||||
reg[`NT_M1:0][31:0] temp_out_a_reg_data;
|
||||
reg[`NT_M1:0][31:0] temp_out_b_reg_data;
|
||||
/* verilator lint_off UNOPTFLAT */
|
||||
reg temp_out_clone_stall;
|
||||
/* verilator lint_on UNOPTFLAT */
|
||||
@@ -247,8 +238,8 @@ module VX_decode(
|
||||
always @(*) begin
|
||||
|
||||
if (`NW == 1) begin
|
||||
temp_out_a_reg_data = glob_a_reg_data;
|
||||
temp_out_b_reg_data = glob_b_reg_data;
|
||||
temp_out_a_reg_data = glob_a_reg_data[0];
|
||||
temp_out_b_reg_data = glob_b_reg_data[0];
|
||||
end else begin
|
||||
integer g;
|
||||
// temp_out_clone_stall = 0;
|
||||
@@ -264,8 +255,12 @@ module VX_decode(
|
||||
end
|
||||
end
|
||||
|
||||
assign out_a_reg_data = temp_out_a_reg_data;
|
||||
assign out_b_reg_data = temp_out_b_reg_data;
|
||||
genvar sml_index;
|
||||
for (sml_index = 0; sml_index <= `NT_M1; sml_index = sml_index + 1) begin
|
||||
assign VX_frE_to_bckE_req.a_reg_data[sml_index] = temp_out_a_reg_data[sml_index];
|
||||
assign VX_frE_to_bckE_req.b_reg_data[sml_index] = temp_out_b_reg_data[sml_index];
|
||||
end
|
||||
|
||||
// assign out_clone_stall = temp_out_clone_stall;
|
||||
|
||||
// assign out_a_reg_data = curr_warp_zero ? glob_a_reg_data[0] : glob_a_reg_data[1];
|
||||
@@ -296,8 +291,11 @@ module VX_decode(
|
||||
// end
|
||||
// end
|
||||
|
||||
assign out_warp_num = in_warp_num;
|
||||
assign out_valid = in_valid;
|
||||
|
||||
assign VX_frE_to_bckE_req.valid = fd_inst_meta_de.valid;
|
||||
|
||||
assign VX_frE_to_bckE_req.warp_num = in_warp_num;
|
||||
assign VX_warp_ctl.warp_num = in_warp_num;
|
||||
|
||||
assign write_register = (in_wb != 2'h0) ? (1'b1) : (1'b0);
|
||||
|
||||
@@ -305,15 +303,15 @@ module VX_decode(
|
||||
assign curr_opcode = in_instruction[6:0];
|
||||
|
||||
|
||||
assign out_rd = in_instruction[11:7];
|
||||
assign out_rs1 = in_instruction[19:15];
|
||||
assign out_rs2 = in_instruction[24:20];
|
||||
assign VX_frE_to_bckE_req.rd = in_instruction[11:7];
|
||||
assign VX_frE_to_bckE_req.rs1 = in_instruction[19:15];
|
||||
assign VX_frE_to_bckE_req.rs2 = in_instruction[24:20];
|
||||
assign func3 = in_instruction[14:12];
|
||||
assign func7 = in_instruction[31:25];
|
||||
assign u_12 = in_instruction[31:20];
|
||||
|
||||
|
||||
assign out_PC_next = in_curr_PC + 32'h4;
|
||||
assign VX_frE_to_bckE_req.PC_next = in_curr_PC + 32'h4;
|
||||
|
||||
|
||||
// Write Back sigal
|
||||
@@ -336,23 +334,21 @@ module VX_decode(
|
||||
assign is_jmprt = is_gpgpu && (func3 == 4);
|
||||
assign is_wspawn = is_gpgpu && (func3 == 0);
|
||||
|
||||
assign out_wspawn = is_wspawn;
|
||||
assign out_wspawn_pc = out_a_reg_data[0];
|
||||
|
||||
// always @(*) begin
|
||||
// if (is_jalrs && in_warp_num == 2) begin
|
||||
// $display("JALRS WOHOOO: rs2 - %h", out_b_reg_data[0]);
|
||||
// end
|
||||
// end
|
||||
assign VX_warp_ctl.wspawn = is_wspawn;
|
||||
assign VX_warp_ctl.wspawn_pc = VX_frE_to_bckE_req.a_reg_data[0];
|
||||
|
||||
|
||||
wire jalrs_thread_mask[`NT_M1:0];
|
||||
wire jmprt_thread_mask[`NT_M1:0];
|
||||
|
||||
|
||||
wire[`NT_M1:0] jalrs_thread_mask;
|
||||
wire[`NT_M1:0] jmprt_thread_mask;
|
||||
|
||||
genvar tm_i;
|
||||
generate
|
||||
for (tm_i = 0; tm_i < `NT; tm_i = tm_i + 1) begin
|
||||
assign jalrs_thread_mask[tm_i] = tm_i <= $signed(out_b_reg_data[0]);
|
||||
/* verilator lint_off UNSIGNED */
|
||||
assign jalrs_thread_mask[tm_i] = tm_i <= $signed(VX_frE_to_bckE_req.b_reg_data[0]);
|
||||
/* verilator lint_on UNSIGNED */
|
||||
end
|
||||
endgenerate
|
||||
|
||||
@@ -365,10 +361,10 @@ module VX_decode(
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign out_thread_mask = is_jalrs ? jalrs_thread_mask : jmprt_thread_mask;
|
||||
assign VX_warp_ctl.thread_mask = is_jalrs ? jalrs_thread_mask : jmprt_thread_mask;
|
||||
|
||||
|
||||
assign out_change_mask = is_jalrs || is_jmprt;
|
||||
assign VX_warp_ctl.change_mask = is_jalrs || is_jmprt;
|
||||
|
||||
|
||||
|
||||
@@ -398,32 +394,32 @@ module VX_decode(
|
||||
|
||||
// always @(negedge clk) begin
|
||||
// if (in_curr_PC == 32'h800001f0) begin
|
||||
// $display("IN DECODE: Going to write to: %d with val: %h [%h, %h, %h]", out_rd, internal_rd1, in_curr_PC, in_src1_fwd_data, rd1_register);
|
||||
// $display("IN DECODE: Going to write to: %d with val: %h [%h, %h, %h]", VX_frE_to_bckE_req.rd, internal_rd1, in_curr_PC, in_src1_fwd_data, rd1_register);
|
||||
// end
|
||||
// end
|
||||
|
||||
assign out_is_csr = is_csr;
|
||||
assign out_csr_mask = (is_csr_immed == 1'b1) ? {27'h0, out_rs1} : out_a_reg_data[0];
|
||||
assign VX_frE_to_bckE_req.is_csr = is_csr;
|
||||
assign VX_frE_to_bckE_req.csr_mask = (is_csr_immed == 1'b1) ? {27'h0, VX_frE_to_bckE_req.rs1} : VX_frE_to_bckE_req.a_reg_data[0];
|
||||
|
||||
|
||||
assign out_wb = (is_jal || is_jalr || is_jalrs || is_e_inst) ? `WB_JAL :
|
||||
is_linst ? `WB_MEM :
|
||||
(is_itype || is_rtype || is_lui || is_auipc || is_csr) ? `WB_ALU :
|
||||
`NO_WB;
|
||||
assign VX_frE_to_bckE_req.wb = (is_jal || is_jalr || is_jalrs || is_e_inst) ? `WB_JAL :
|
||||
is_linst ? `WB_MEM :
|
||||
(is_itype || is_rtype || is_lui || is_auipc || is_csr) ? `WB_ALU :
|
||||
`NO_WB;
|
||||
|
||||
|
||||
assign out_rs2_src = (is_itype || is_stype) ? `RS2_IMMED : `RS2_REG;
|
||||
assign VX_frE_to_bckE_req.rs2_src = (is_itype || is_stype) ? `RS2_IMMED : `RS2_REG;
|
||||
|
||||
// MEM signals
|
||||
assign out_mem_read = (is_linst) ? func3 : `NO_MEM_READ;
|
||||
assign out_mem_write = (is_stype) ? func3 : `NO_MEM_WRITE;
|
||||
assign VX_frE_to_bckE_req.mem_read = (is_linst) ? func3 : `NO_MEM_READ;
|
||||
assign VX_frE_to_bckE_req.mem_write = (is_stype) ? func3 : `NO_MEM_WRITE;
|
||||
|
||||
// UPPER IMMEDIATE
|
||||
always @(*) begin
|
||||
case(curr_opcode)
|
||||
`LUI_INST: out_upper_immed = {func7, out_rs2, out_rs1, func3};
|
||||
`AUIPC_INST: out_upper_immed = {func7, out_rs2, out_rs1, func3};
|
||||
default: out_upper_immed = 20'h0;
|
||||
`LUI_INST: VX_frE_to_bckE_req.upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3};
|
||||
`AUIPC_INST: VX_frE_to_bckE_req.upper_immed = {func7, VX_frE_to_bckE_req.rs2, VX_frE_to_bckE_req.rs1, func3};
|
||||
default: VX_frE_to_bckE_req.upper_immed = 20'h0;
|
||||
endcase // curr_opcode
|
||||
end
|
||||
|
||||
@@ -437,7 +433,7 @@ module VX_decode(
|
||||
assign jal_1_offset = {{11{jal_b_20}}, jal_unsigned_offset};
|
||||
|
||||
|
||||
assign jalr_immed = {func7, out_rs2};
|
||||
assign jalr_immed = {func7, VX_frE_to_bckE_req.rs2};
|
||||
assign jal_2_offset = {{20{jalr_immed[11]}}, jalr_immed};
|
||||
|
||||
|
||||
@@ -452,33 +448,32 @@ module VX_decode(
|
||||
case(curr_opcode)
|
||||
`JAL_INST:
|
||||
begin
|
||||
out_jal = 1'b1 && in_valid[0];
|
||||
out_jal_offset = jal_1_offset;
|
||||
VX_frE_to_bckE_req.jal = 1'b1 && in_valid[0];
|
||||
VX_frE_to_bckE_req.jal_offset = jal_1_offset;
|
||||
end
|
||||
`JALR_INST:
|
||||
begin
|
||||
out_jal = 1'b1 && in_valid[0];
|
||||
out_jal_offset = jal_2_offset;
|
||||
VX_frE_to_bckE_req.jal = 1'b1 && in_valid[0];
|
||||
VX_frE_to_bckE_req.jal_offset = jal_2_offset;
|
||||
end
|
||||
`GPGPU_INST:
|
||||
begin
|
||||
if (is_jalrs || is_jmprt)
|
||||
begin
|
||||
// $display("OUT JAL DEST: %h", out_a_reg_data[0]);
|
||||
out_jal = 1'b1 && in_valid[0];
|
||||
out_jal_offset = 32'h0;
|
||||
VX_frE_to_bckE_req.jal = 1'b1 && in_valid[0];
|
||||
VX_frE_to_bckE_req.jal_offset = 32'h0;
|
||||
end
|
||||
end
|
||||
`SYS_INST:
|
||||
begin
|
||||
// $display("SYS EBREAK %h", (jal_sys_jal && in_valid[0]) );
|
||||
out_jal = jal_sys_jal && in_valid[0];
|
||||
out_jal_offset = jal_sys_off;
|
||||
VX_frE_to_bckE_req.jal = jal_sys_jal && in_valid[0];
|
||||
VX_frE_to_bckE_req.jal_offset = jal_sys_off;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
out_jal = 1'b0 && in_valid[0];
|
||||
out_jal_offset = 32'hdeadbeef;
|
||||
VX_frE_to_bckE_req.jal = 1'b0 && in_valid[0];
|
||||
VX_frE_to_bckE_req.jal_offset = 32'hdeadbeef;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
@@ -489,29 +484,29 @@ module VX_decode(
|
||||
assign is_ebreak = (curr_opcode == `SYS_INST) && (jal_sys_jal && in_valid[0]);
|
||||
|
||||
|
||||
assign out_ebreak = is_ebreak;
|
||||
assign VX_warp_ctl.ebreak = is_ebreak;
|
||||
|
||||
// CSR
|
||||
|
||||
assign csr_cond1 = func3 != 3'h0;
|
||||
assign csr_cond2 = u_12 >= 12'h2;
|
||||
|
||||
assign out_csr_address = (csr_cond1 && csr_cond2) ? u_12 : 12'h55;
|
||||
assign VX_frE_to_bckE_req.csr_address = (csr_cond1 && csr_cond2) ? u_12 : 12'h55;
|
||||
|
||||
|
||||
// ITYPE IMEED
|
||||
assign alu_shift_i = (func3 == 3'h1) || (func3 == 3'h5);
|
||||
assign alu_shift_i_immed = {{7{1'b0}}, out_rs2};
|
||||
assign alu_shift_i_immed = {{7{1'b0}}, VX_frE_to_bckE_req.rs2};
|
||||
assign alu_tempp = alu_shift_i ? alu_shift_i_immed : u_12;
|
||||
|
||||
|
||||
always @(*) begin
|
||||
case(curr_opcode)
|
||||
`ALU_INST: out_itype_immed = {{20{alu_tempp[11]}}, alu_tempp};
|
||||
`S_INST: out_itype_immed = {{20{func7[6]}}, func7, out_rd};
|
||||
`L_INST: out_itype_immed = {{20{u_12[11]}}, u_12};
|
||||
`B_INST: out_itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]};
|
||||
default: out_itype_immed = 32'hdeadbeef;
|
||||
`ALU_INST: VX_frE_to_bckE_req.itype_immed = {{20{alu_tempp[11]}}, alu_tempp};
|
||||
`S_INST: VX_frE_to_bckE_req.itype_immed = {{20{func7[6]}}, func7, VX_frE_to_bckE_req.rd};
|
||||
`L_INST: VX_frE_to_bckE_req.itype_immed = {{20{u_12[11]}}, u_12};
|
||||
`B_INST: VX_frE_to_bckE_req.itype_immed = {{20{in_instruction[31]}}, in_instruction[31], in_instruction[7], in_instruction[30:25], in_instruction[11:8]};
|
||||
default: VX_frE_to_bckE_req.itype_immed = 32'hdeadbeef;
|
||||
endcase
|
||||
end
|
||||
|
||||
@@ -522,37 +517,37 @@ module VX_decode(
|
||||
begin
|
||||
out_branch_stall = 1'b1 && in_valid[0];
|
||||
case(func3)
|
||||
3'h0: out_branch_type = `BEQ;
|
||||
3'h1: out_branch_type = `BNE;
|
||||
3'h4: out_branch_type = `BLT;
|
||||
3'h5: out_branch_type = `BGT;
|
||||
3'h6: out_branch_type = `BLTU;
|
||||
3'h7: out_branch_type = `BGTU;
|
||||
default: out_branch_type = `NO_BRANCH;
|
||||
3'h0: VX_frE_to_bckE_req.branch_type = `BEQ;
|
||||
3'h1: VX_frE_to_bckE_req.branch_type = `BNE;
|
||||
3'h4: VX_frE_to_bckE_req.branch_type = `BLT;
|
||||
3'h5: VX_frE_to_bckE_req.branch_type = `BGT;
|
||||
3'h6: VX_frE_to_bckE_req.branch_type = `BLTU;
|
||||
3'h7: VX_frE_to_bckE_req.branch_type = `BGTU;
|
||||
default: VX_frE_to_bckE_req.branch_type = `NO_BRANCH;
|
||||
endcase
|
||||
end
|
||||
|
||||
`JAL_INST:
|
||||
begin
|
||||
out_branch_type = `NO_BRANCH;
|
||||
VX_frE_to_bckE_req.branch_type = `NO_BRANCH;
|
||||
out_branch_stall = 1'b1 && in_valid[0];
|
||||
end
|
||||
`JALR_INST:
|
||||
begin
|
||||
out_branch_type = `NO_BRANCH;
|
||||
VX_frE_to_bckE_req.branch_type = `NO_BRANCH;
|
||||
out_branch_stall = 1'b1 && in_valid[0];
|
||||
end
|
||||
`GPGPU_INST:
|
||||
begin
|
||||
if (is_jalrs || is_jmprt)
|
||||
begin
|
||||
out_branch_type = `NO_BRANCH;
|
||||
VX_frE_to_bckE_req.branch_type = `NO_BRANCH;
|
||||
out_branch_stall = 1'b1 && in_valid[0];
|
||||
end
|
||||
end
|
||||
default:
|
||||
begin
|
||||
out_branch_type = `NO_BRANCH;
|
||||
VX_frE_to_bckE_req.branch_type = `NO_BRANCH;
|
||||
out_branch_stall = 1'b0 && in_valid[0];
|
||||
end
|
||||
endcase
|
||||
@@ -602,14 +597,14 @@ module VX_decode(
|
||||
|
||||
wire[4:0] temp_final_alu;
|
||||
|
||||
assign temp_final_alu = is_btype ? ((out_branch_type < `BLTU) ? `SUB : `SUBU) :
|
||||
assign temp_final_alu = is_btype ? ((VX_frE_to_bckE_req.branch_type < `BLTU) ? `SUB : `SUBU) :
|
||||
is_lui ? `LUI_ALU :
|
||||
is_auipc ? `AUIPC_ALU :
|
||||
is_csr ? csr_alu :
|
||||
(is_stype || is_linst) ? `ADD :
|
||||
alu_op;
|
||||
|
||||
assign out_alu_op = ((func7[0] == 1'b1) && is_rtype) ? mul_alu : temp_final_alu;
|
||||
assign VX_frE_to_bckE_req.alu_op = ((func7[0] == 1'b1) && is_rtype) ? mul_alu : temp_final_alu;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
151
rtl/VX_e_m_reg.v
151
rtl/VX_e_m_reg.v
@@ -5,150 +5,41 @@
|
||||
|
||||
module VX_e_m_reg (
|
||||
input wire clk,
|
||||
input wire[31:0] in_alu_result[`NT_M1:0],
|
||||
input wire[4:0] in_rd,
|
||||
input wire[1:0] in_wb,
|
||||
input wire[4:0] in_rs1,
|
||||
input wire[4:0] in_rs2,
|
||||
input wire[31:0] in_a_reg_data[`NT_M1:0],
|
||||
input wire[31:0] in_b_reg_data[`NT_M1:0],
|
||||
input wire[2:0] in_mem_read, // NEW
|
||||
input wire[2:0] in_mem_write, // NEW
|
||||
input wire[31:0] in_PC_next,
|
||||
input wire reset,
|
||||
input wire in_freeze,
|
||||
input wire[11:0] in_csr_address,
|
||||
input wire in_is_csr,
|
||||
input wire[31:0] in_csr_result,
|
||||
input wire[31:0] in_curr_PC,
|
||||
input wire[31:0] in_branch_offset,
|
||||
input wire[2:0] in_branch_type,
|
||||
input wire in_jal,
|
||||
input wire[31:0] in_jal_dest,
|
||||
input wire in_freeze,
|
||||
input wire in_valid[`NT_M1:0],
|
||||
input wire[`NW_M1:0] in_warp_num,
|
||||
input wire[`NT_M1:0][31:0] in_a_reg_data,
|
||||
input wire[`NT_M1:0][31:0] in_b_reg_data,
|
||||
VX_mem_req_inter VX_exe_mem_req,
|
||||
|
||||
|
||||
VX_mem_req_inter VX_mem_req,
|
||||
output wire[11:0] out_csr_address,
|
||||
output wire out_is_csr,
|
||||
output wire[31:0] out_csr_result,
|
||||
output wire[31:0] out_alu_result[`NT_M1:0],
|
||||
output wire[4:0] out_rd,
|
||||
output wire[1:0] out_wb,
|
||||
output wire[4:0] out_rs1,
|
||||
output wire[4:0] out_rs2,
|
||||
output wire[31:0] out_a_reg_data[`NT_M1:0],
|
||||
output wire[31:0] out_b_reg_data[`NT_M1:0],
|
||||
output wire[2:0] out_mem_read,
|
||||
output wire[2:0] out_mem_write,
|
||||
output wire[31:0] out_curr_PC,
|
||||
output wire[31:0] out_branch_offset,
|
||||
output wire[2:0] out_branch_type,
|
||||
output wire[`NT_M1:0][31:0] out_a_reg_data,
|
||||
output wire[`NT_M1:0][31:0] out_b_reg_data,
|
||||
output wire out_jal,
|
||||
output wire[31:0] out_jal_dest,
|
||||
output wire[31:0] out_PC_next,
|
||||
output wire out_valid[`NT_M1:0],
|
||||
output wire[`NW_M1:0] out_warp_num
|
||||
output wire[31:0] out_jal_dest
|
||||
);
|
||||
|
||||
|
||||
reg[31:0] alu_result[`NT_M1:0];
|
||||
reg[4:0] rd;
|
||||
reg[4:0] rs1;
|
||||
reg[4:0] rs2;
|
||||
reg[31:0] a_reg_data[`NT_M1:0];
|
||||
reg[31:0] b_reg_data[`NT_M1:0];
|
||||
reg[1:0] wb;
|
||||
reg[31:0] PC_next;
|
||||
reg[2:0] mem_read;
|
||||
reg[2:0] mem_write;
|
||||
reg[11:0] csr_address;
|
||||
reg is_csr;
|
||||
reg[31:0] csr_result;
|
||||
reg[31:0] curr_PC;
|
||||
reg[31:0] branch_offset;
|
||||
reg[2:0] branch_type;
|
||||
reg jal;
|
||||
reg[31:0] jal_dest;
|
||||
reg valid[`NT_M1:0];
|
||||
reg[`NW_M1:0] warp_num;
|
||||
// reg[31:0] reg_data_z[`NT_T2_M1:0];
|
||||
// reg[`NT_M1:0] valid_z;
|
||||
// reg[31:0] alu_result_z[`NT_M1:0];
|
||||
wire flush = 0;
|
||||
wire stall = in_freeze;
|
||||
|
||||
integer ini_reg;
|
||||
|
||||
initial begin
|
||||
rd = 0;
|
||||
rs1 = 0;
|
||||
rs2 = 0;
|
||||
wb = 0;
|
||||
PC_next = 0;
|
||||
mem_read = `NO_MEM_READ;
|
||||
mem_write = `NO_MEM_WRITE;
|
||||
csr_address = 0;
|
||||
is_csr = 0;
|
||||
csr_result = 0;
|
||||
curr_PC = 0;
|
||||
branch_offset = 0;
|
||||
branch_type = 0;
|
||||
jal = `NO_JUMP;
|
||||
jal_dest = 0;
|
||||
warp_num = 0;
|
||||
for (ini_reg = 0; ini_reg < `NT; ini_reg = ini_reg + 1)
|
||||
begin
|
||||
a_reg_data[ini_reg] = 0;
|
||||
b_reg_data[ini_reg] = 0;
|
||||
valid[ini_reg] = 0;
|
||||
alu_result[ini_reg] = 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
assign out_alu_result = alu_result;
|
||||
assign out_rd = rd;
|
||||
assign out_rs1 = rs1;
|
||||
assign out_rs2 = rs2;
|
||||
assign out_wb = wb;
|
||||
assign out_PC_next = PC_next;
|
||||
assign out_mem_read = mem_read;
|
||||
assign out_mem_write = mem_write;
|
||||
assign out_a_reg_data = a_reg_data;
|
||||
assign out_b_reg_data = b_reg_data;
|
||||
assign out_csr_address = csr_address;
|
||||
assign out_is_csr = is_csr;
|
||||
assign out_csr_result = csr_result;
|
||||
assign out_curr_PC = curr_PC;
|
||||
assign out_branch_offset = branch_offset;
|
||||
assign out_branch_type = branch_type;
|
||||
assign out_jal = jal;
|
||||
assign out_jal_dest = jal_dest;
|
||||
assign out_valid = valid;
|
||||
assign out_warp_num = warp_num;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(in_freeze == 1'b0) begin
|
||||
alu_result <= in_alu_result;
|
||||
rd <= in_rd;
|
||||
rs1 <= in_rs1;
|
||||
rs2 <= in_rs2;
|
||||
wb <= in_wb;
|
||||
PC_next <= in_PC_next;
|
||||
mem_read <= in_mem_read;
|
||||
mem_write <= in_mem_write;
|
||||
a_reg_data <= in_a_reg_data;
|
||||
b_reg_data <= in_b_reg_data;
|
||||
csr_address <= in_csr_address;
|
||||
is_csr <= in_is_csr;
|
||||
csr_result <= in_csr_result;
|
||||
curr_PC <= in_curr_PC;
|
||||
branch_offset <= in_branch_offset;
|
||||
branch_type <= in_branch_type;
|
||||
jal <= in_jal;
|
||||
jal_dest <= in_jal_dest;
|
||||
valid <= in_valid;
|
||||
warp_num <= in_warp_num;
|
||||
end
|
||||
end
|
||||
VX_generic_register #(.N(720)) f_d_reg
|
||||
(
|
||||
.clk (clk),
|
||||
.reset(reset),
|
||||
.stall(stall),
|
||||
.flush(flush),
|
||||
.in ({in_csr_address , in_is_csr , in_csr_result , in_jal , in_jal_dest , in_a_reg_data , in_b_reg_data , VX_exe_mem_req.alu_result, VX_exe_mem_req.mem_read, VX_exe_mem_req.mem_write, VX_exe_mem_req.rd, VX_exe_mem_req.wb, VX_exe_mem_req.rs1, VX_exe_mem_req.rs2, VX_exe_mem_req.rd2, VX_exe_mem_req.PC_next, VX_exe_mem_req.curr_PC, VX_exe_mem_req.branch_offset, VX_exe_mem_req.branch_type, VX_exe_mem_req.valid, VX_exe_mem_req.warp_num}),
|
||||
.out ({out_csr_address, out_is_csr, out_csr_result, out_jal, out_jal_dest, out_a_reg_data, out_b_reg_data, VX_mem_req.alu_result , VX_mem_req.mem_read , VX_mem_req.mem_write , VX_mem_req.rd , VX_mem_req.wb , VX_mem_req.rs1 , VX_mem_req.rs2 , VX_mem_req.rd2 , VX_mem_req.PC_next , VX_mem_req.curr_PC , VX_mem_req.branch_offset , VX_mem_req.branch_type , VX_mem_req.valid , VX_mem_req.warp_num})
|
||||
);
|
||||
|
||||
endmodule // VX_e_m_reg
|
||||
|
||||
|
||||
123
rtl/VX_execute.v
123
rtl/VX_execute.v
@@ -2,52 +2,44 @@
|
||||
`include "VX_define.v"
|
||||
|
||||
module VX_execute (
|
||||
input wire[4:0] in_rd,
|
||||
input wire[4:0] in_rs1,
|
||||
input wire[4:0] in_rs2,
|
||||
input wire[31:0] in_a_reg_data[`NT_M1:0],
|
||||
input wire[31:0] in_b_reg_data[`NT_M1:0],
|
||||
input wire[4:0] in_alu_op,
|
||||
input wire[1:0] in_wb,
|
||||
input wire in_rs2_src, // NEW
|
||||
input wire[31:0] in_itype_immed, // new
|
||||
input wire[2:0] in_mem_read, // NEW
|
||||
input wire[2:0] in_mem_write, // NEW
|
||||
input wire[31:0] in_PC_next,
|
||||
input wire[2:0] in_branch_type,
|
||||
input wire[19:0] in_upper_immed,
|
||||
input wire[11:0] in_csr_address, // done
|
||||
input wire in_is_csr, // done
|
||||
input wire[31:0] in_csr_data, // done
|
||||
input wire[31:0] in_csr_mask, // done
|
||||
input wire in_jal,
|
||||
input wire[31:0] in_jal_offset,
|
||||
input wire[31:0] in_curr_PC,
|
||||
input wire in_valid[`NT_M1:0],
|
||||
input [`NW_M1:0] in_warp_num,
|
||||
VX_frE_to_bckE_req_inter VX_bckE_req,
|
||||
input wire[31:0] in_csr_data,
|
||||
|
||||
output wire[11:0] out_csr_address,
|
||||
output wire out_is_csr,
|
||||
output reg[31:0] out_csr_result,
|
||||
output reg[31:0] out_alu_result[`NT_M1:0],
|
||||
output wire[4:0] out_rd,
|
||||
output wire[1:0] out_wb,
|
||||
output wire[4:0] out_rs1,
|
||||
output wire[4:0] out_rs2,
|
||||
output wire[31:0] out_a_reg_data[`NT_M1:0],
|
||||
output wire[31:0] out_b_reg_data[`NT_M1:0],
|
||||
output wire[2:0] out_mem_read,
|
||||
output wire[2:0] out_mem_write,
|
||||
output wire out_jal,
|
||||
output wire[31:0] out_jal_dest,
|
||||
output wire[31:0] out_branch_offset,
|
||||
output wire out_branch_stall,
|
||||
output wire[31:0] out_PC_next,
|
||||
output wire out_valid[`NT_M1:0],
|
||||
output wire[`NW_M1:0] out_warp_num
|
||||
VX_mem_req_inter VX_exe_mem_req,
|
||||
output wire[11:0] out_csr_address,
|
||||
output wire out_is_csr,
|
||||
output reg[31:0] out_csr_result,
|
||||
output wire[`NT_M1:0][31:0] out_a_reg_data,
|
||||
output wire[`NT_M1:0][31:0] out_b_reg_data,
|
||||
output wire out_jal,
|
||||
output wire[31:0] out_jal_dest,
|
||||
output wire out_branch_stall
|
||||
);
|
||||
|
||||
|
||||
wire[`NT_M1:0][31:0] in_a_reg_data;
|
||||
wire[`NT_M1:0][31:0] in_b_reg_data;
|
||||
wire[4:0] in_alu_op;
|
||||
wire in_rs2_src;
|
||||
wire[31:0] in_itype_immed;
|
||||
wire[2:0] in_branch_type;
|
||||
wire[19:0] in_upper_immed;
|
||||
wire[31:0] in_csr_mask;
|
||||
wire in_jal;
|
||||
wire[31:0] in_jal_offset;
|
||||
wire[31:0] in_curr_PC;
|
||||
|
||||
assign in_a_reg_data = VX_bckE_req.a_reg_data;
|
||||
assign in_b_reg_data = VX_bckE_req.b_reg_data;
|
||||
assign in_alu_op = VX_bckE_req.alu_op;
|
||||
assign in_rs2_src = VX_bckE_req.rs2_src;
|
||||
assign in_itype_immed = VX_bckE_req.itype_immed;
|
||||
assign in_branch_type = VX_bckE_req.branch_type;
|
||||
assign in_upper_immed = VX_bckE_req.upper_immed;
|
||||
assign in_csr_mask = VX_bckE_req.csr_mask;
|
||||
assign in_jal = VX_bckE_req.jal;
|
||||
assign in_jal_offset = VX_bckE_req.jal_offset;
|
||||
assign in_curr_PC = VX_bckE_req.curr_PC;
|
||||
|
||||
genvar index_out_reg;
|
||||
generate
|
||||
@@ -63,18 +55,11 @@ module VX_execute (
|
||||
.in_alu_op (in_alu_op),
|
||||
.in_csr_data (in_csr_data),
|
||||
.in_curr_PC (in_curr_PC),
|
||||
.out_alu_result(out_alu_result[index_out_reg])
|
||||
.out_alu_result(VX_exe_mem_req.alu_result[index_out_reg])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// always @(*) begin
|
||||
// if ((in_alu_op == `MUL) && (in_warp_num == 1)) begin
|
||||
// $display("@PC: %h ---> %d * %d = %d\t%d * %d = %d", in_curr_PC, in_a_reg_data[0], in_b_reg_data[0], out_alu_result[0], in_a_reg_data[1], in_b_reg_data[1], out_alu_result[1]);
|
||||
// end
|
||||
|
||||
// end
|
||||
|
||||
|
||||
assign out_jal_dest = $signed(in_a_reg_data[0]) + $signed(in_jal_offset);
|
||||
assign out_jal = in_jal;
|
||||
@@ -97,20 +82,30 @@ module VX_execute (
|
||||
|
||||
|
||||
|
||||
assign out_rd = in_rd;
|
||||
assign out_wb = in_wb;
|
||||
assign out_mem_read = in_mem_read;
|
||||
assign out_mem_write = in_mem_write;
|
||||
assign out_rs1 = in_rs1;
|
||||
assign out_a_reg_data = in_a_reg_data;
|
||||
assign out_b_reg_data = in_b_reg_data;
|
||||
assign out_rs2 = in_rs2;
|
||||
assign out_PC_next = in_PC_next;
|
||||
assign out_is_csr = in_is_csr;
|
||||
assign out_csr_address = in_csr_address;
|
||||
assign out_branch_offset = in_itype_immed;
|
||||
assign out_valid = in_valid;
|
||||
assign out_warp_num = in_warp_num;
|
||||
genvar ind;
|
||||
for (ind = 0; ind <= `NT_M1; ind = ind + 1) begin
|
||||
assign out_a_reg_data[ind] = in_a_reg_data[ind];
|
||||
assign out_b_reg_data[ind] = in_b_reg_data[ind];
|
||||
end
|
||||
|
||||
assign VX_exe_mem_req.mem_read = VX_bckE_req.mem_read;
|
||||
assign VX_exe_mem_req.mem_write = VX_bckE_req.mem_write;
|
||||
assign VX_exe_mem_req.wb = VX_bckE_req.wb;
|
||||
assign VX_exe_mem_req.rs1 = VX_bckE_req.rs1;
|
||||
assign VX_exe_mem_req.rs2 = VX_bckE_req.rs2;
|
||||
assign VX_exe_mem_req.rd = VX_bckE_req.rd;
|
||||
assign VX_exe_mem_req.rd2 = VX_bckE_req.b_reg_data;
|
||||
assign VX_exe_mem_req.wb = VX_bckE_req.wb;
|
||||
assign VX_exe_mem_req.PC_next = VX_bckE_req.PC_next;
|
||||
assign VX_exe_mem_req.curr_PC = VX_bckE_req.curr_PC;
|
||||
assign VX_exe_mem_req.branch_offset = VX_bckE_req.itype_immed;
|
||||
assign VX_exe_mem_req.branch_type = VX_bckE_req.branch_type;
|
||||
assign VX_exe_mem_req.valid = VX_bckE_req.valid;
|
||||
assign VX_exe_mem_req.warp_num = VX_bckE_req.warp_num;
|
||||
|
||||
|
||||
assign out_is_csr = VX_bckE_req.is_csr;
|
||||
assign out_csr_address = VX_bckE_req.csr_address;
|
||||
|
||||
|
||||
endmodule // VX_execute
|
||||
|
||||
@@ -3,84 +3,31 @@
|
||||
`include "VX_define.v"
|
||||
|
||||
module VX_f_d_reg (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire in_valid[`NT_M1:0],
|
||||
input wire in_fwd_stall,
|
||||
input wire in_freeze,
|
||||
input wire in_clone_stall,
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire in_fwd_stall,
|
||||
input wire in_freeze,
|
||||
input wire in_clone_stall,
|
||||
|
||||
VX_inst_meta_inter fe_inst_meta_fd,
|
||||
VX_inst_meta_inter fd_inst_meta_de
|
||||
|
||||
output wire[31:0] out_instruction,
|
||||
output wire[31:0] out_curr_PC,
|
||||
output wire out_valid[`NT_M1:0],
|
||||
output wire[`NW_M1:0] out_warp_num,
|
||||
/* verilator lint_off UNUSED */
|
||||
input wire[31:0] in_instruction,
|
||||
input wire[31:0] in_curr_PC,
|
||||
input wire[`NW_M1:0] in_warp_num,
|
||||
input fe_inst_meta_de_t fe_inst_meta_fd
|
||||
/* verilator lint_on UNUSED */
|
||||
);
|
||||
|
||||
// genvar index;
|
||||
// always @(posedge clk) begin
|
||||
// // $display("in_instruction: %x\tfe_inst_meta_fd.instruction: %x",in_instruction, fe_inst_meta_fd.instruction);
|
||||
// $error("finally");
|
||||
// assert (in_instruction == fe_inst_meta_fd.instruction);
|
||||
// assert (in_curr_PC == fe_inst_meta_fd.inst_pc);
|
||||
// assert (in_warp_num == fe_inst_meta_fd.warp_num);
|
||||
// for (index = 0; index <= `NT_M1; index = index + 1) assert (in_valid[index] == fe_inst_meta_fd.valid[index]);
|
||||
// end
|
||||
|
||||
// var match;
|
||||
// always @(*) begin
|
||||
// match = ;
|
||||
// if (!match)
|
||||
// $display("in_instruction: %x, fe_inst_meta_fd.instruction: %x",in_instruction ,fe_inst_meta_fd.instruction);
|
||||
// end
|
||||
|
||||
reg[31:0] instruction;
|
||||
reg[31:0] curr_PC;
|
||||
reg valid[`NT_M1:0];
|
||||
reg[`NW_M1:0] warp_num;
|
||||
|
||||
integer reset_cur_thread = 0;
|
||||
wire flush = 1'b0;
|
||||
wire stall = in_fwd_stall == 1'b1 || in_freeze == 1'b1 || in_clone_stall;
|
||||
|
||||
|
||||
always @(posedge clk or posedge reset) begin
|
||||
if(reset) begin
|
||||
instruction <= 32'h0;
|
||||
curr_PC <= 32'h0;
|
||||
warp_num <= 0;
|
||||
for (reset_cur_thread = 0; reset_cur_thread < `NT; reset_cur_thread = reset_cur_thread + 1)
|
||||
valid[reset_cur_thread] <= 1'b0;
|
||||
|
||||
end else if (in_fwd_stall == 1'b1 || in_freeze == 1'b1 || in_clone_stall) begin
|
||||
// if (in_clone_stall) begin
|
||||
// $display("STALL BECAUSE OF CLONE");
|
||||
// end
|
||||
end else begin
|
||||
instruction <= in_instruction;
|
||||
valid <= in_valid;
|
||||
curr_PC <= in_curr_PC;
|
||||
warp_num <= in_warp_num;
|
||||
|
||||
// instruction <= fe_inst_meta_fd.instruction;
|
||||
// valid <= fe_inst_meta_fd.valid;
|
||||
// curr_PC <= fe_inst_meta_fd.inst_pc;
|
||||
// warp_num <= fe_inst_meta_fd.warp_num;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
// $display("PC in VX_f_d_reg: %h", curr_PC);
|
||||
end
|
||||
|
||||
assign out_instruction = instruction;
|
||||
assign out_curr_PC = curr_PC;
|
||||
assign out_valid = valid;
|
||||
assign out_warp_num = warp_num;
|
||||
|
||||
VX_generic_register #(.N(72)) f_d_reg
|
||||
(
|
||||
.clk (clk),
|
||||
.reset(reset),
|
||||
.stall(stall),
|
||||
.flush(flush),
|
||||
.in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.inst_pc, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}),
|
||||
.out ({fd_inst_meta_de.instruction, fd_inst_meta_de.inst_pc, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid})
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -15,26 +15,31 @@ module VX_fetch (
|
||||
input wire[31:0] in_jal_dest,
|
||||
input wire in_interrupt,
|
||||
input wire in_debug,
|
||||
input wire in_thread_mask[`NT_M1:0],
|
||||
input wire in_change_mask,
|
||||
input wire[`NW_M1:0] in_decode_warp_num,
|
||||
input wire[`NW_M1:0] in_memory_warp_num,
|
||||
input wire in_wspawn,
|
||||
input wire[31:0] in_wspawn_pc,
|
||||
input wire in_ebreak,
|
||||
input icache_response_t icache_response,
|
||||
|
||||
output icache_request_t icache_request,
|
||||
output wire[31:0] out_instruction,
|
||||
output wire out_delay,
|
||||
output wire[`NW_M1:0] out_warp_num,
|
||||
output wire[31:0] out_curr_PC,
|
||||
output wire out_valid[`NT_M1:0],
|
||||
output wire out_ebreak,
|
||||
output wire[`NW_M1:0] out_which_wspawn,
|
||||
output fe_inst_meta_de_t fe_inst_meta_fd
|
||||
VX_inst_meta_inter fe_inst_meta_fd,
|
||||
VX_warp_ctl_inter VX_warp_ctl
|
||||
);
|
||||
|
||||
wire in_change_mask = VX_warp_ctl.change_mask;
|
||||
wire in_wspawn = VX_warp_ctl.wspawn;
|
||||
wire[31:0] in_wspawn_pc = VX_warp_ctl.wspawn_pc;
|
||||
wire in_ebreak = VX_warp_ctl.ebreak;
|
||||
wire[`NW_M1:0] in_decode_warp_num = VX_warp_ctl.warp_num;
|
||||
|
||||
|
||||
wire in_thread_mask[`NT_M1:0];
|
||||
|
||||
genvar ind;
|
||||
for (ind = 0; ind <= `NT_M1; ind = ind + 1) assign in_thread_mask[ind] = VX_warp_ctl.thread_mask[ind];
|
||||
|
||||
|
||||
|
||||
reg stall;
|
||||
reg[31:0] out_PC;
|
||||
|
||||
@@ -184,25 +189,16 @@ module VX_fetch (
|
||||
end
|
||||
|
||||
assign out_PC = out_PC_var;
|
||||
assign out_valid = out_valid_var;
|
||||
|
||||
// always @(*) begin
|
||||
// if (out_valid[0]) begin
|
||||
// $display("[%d] %h #%b#",out_warp_num, out_PC, out_valid);
|
||||
// end
|
||||
// end
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
|
||||
|
||||
assign icache_request.pc_address = out_PC;
|
||||
|
||||
assign out_curr_PC = out_PC;
|
||||
assign out_warp_num = warp_num;
|
||||
assign out_delay = 0;
|
||||
|
||||
assign out_instruction = (stall) ? 32'b0 : icache_response.instruction;
|
||||
|
||||
assign fe_inst_meta_fd.warp_num = warp_num;
|
||||
|
||||
genvar index;
|
||||
@@ -211,6 +207,8 @@ module VX_fetch (
|
||||
assign fe_inst_meta_fd.instruction = (stall) ? 32'b0 : icache_response.instruction;;
|
||||
assign fe_inst_meta_fd.inst_pc = out_PC;
|
||||
|
||||
|
||||
// always @(*) begin
|
||||
// $display("fetch: icache_request: %x", out_PC);
|
||||
// end
|
||||
|
||||
endmodule
|
||||
@@ -11,7 +11,7 @@ module VX_forwarding (
|
||||
// INFO FROM EXE
|
||||
input wire[4:0] in_execute_dest,
|
||||
input wire[1:0] in_execute_wb,
|
||||
input wire[31:0] in_execute_alu_result[`NT_M1:0],
|
||||
input wire[`NT_M1:0][31:0] in_execute_alu_result,
|
||||
input wire[31:0] in_execute_PC_next,
|
||||
input wire in_execute_is_csr,
|
||||
input wire[11:0] in_execute_csr_address,
|
||||
@@ -20,8 +20,8 @@ module VX_forwarding (
|
||||
// INFO FROM MEM
|
||||
input wire[4:0] in_memory_dest,
|
||||
input wire[1:0] in_memory_wb,
|
||||
input wire[31:0] in_memory_alu_result[`NT_M1:0],
|
||||
input wire[31:0] in_memory_mem_data[`NT_M1:0],
|
||||
input wire[`NT_M1:0][31:0] in_memory_alu_result,
|
||||
input wire[`NT_M1:0][31:0] in_memory_mem_data,
|
||||
input wire[31:0] in_memory_PC_next,
|
||||
input wire in_memory_is_csr,
|
||||
input wire[11:0] in_memory_csr_address,
|
||||
@@ -31,8 +31,8 @@ module VX_forwarding (
|
||||
// INFO FROM WB
|
||||
input wire[4:0] in_writeback_dest,
|
||||
input wire[1:0] in_writeback_wb,
|
||||
input wire[31:0] in_writeback_alu_result[`NT_M1:0],
|
||||
input wire[31:0] in_writeback_mem_data[`NT_M1:0],
|
||||
input wire[`NT_M1:0][31:0] in_writeback_alu_result,
|
||||
input wire[`NT_M1:0][31:0] in_writeback_mem_data,
|
||||
input wire[31:0] in_writeback_PC_next,
|
||||
input wire[`NW_M1:0] in_writeback_warp_num,
|
||||
|
||||
@@ -41,8 +41,8 @@ module VX_forwarding (
|
||||
output wire out_src1_fwd,
|
||||
output wire out_src2_fwd,
|
||||
output wire out_csr_fwd,
|
||||
output wire[31:0] out_src1_fwd_data[`NT_M1:0],
|
||||
output wire[31:0] out_src2_fwd_data[`NT_M1:0],
|
||||
output wire[`NT_M1:0][31:0] out_src1_fwd_data,
|
||||
output wire[`NT_M1:0][31:0] out_src2_fwd_data,
|
||||
output wire[31:0] out_csr_fwd_data,
|
||||
output wire out_fwd_stall
|
||||
);
|
||||
@@ -66,9 +66,9 @@ module VX_forwarding (
|
||||
wire csr_exe_fwd;
|
||||
wire csr_mem_fwd;
|
||||
|
||||
wire[31:0] use_execute_PC_next[`NT_M1:0];
|
||||
wire[31:0] use_memory_PC_next[`NT_M1:0];
|
||||
wire[31:0] use_writeback_PC_next[`NT_M1:0];
|
||||
wire[`NT_M1:0][31:0] use_execute_PC_next;
|
||||
wire[`NT_M1:0][31:0] use_memory_PC_next;
|
||||
wire[`NT_M1:0][31:0] use_writeback_PC_next;
|
||||
|
||||
|
||||
genvar index;
|
||||
@@ -169,10 +169,11 @@ module VX_forwarding (
|
||||
(src2_mem_fwd) ? ((mem_jal) ? use_memory_PC_next : (mem_mem_read ? in_memory_mem_data : in_memory_alu_result)) :
|
||||
( src2_wb_fwd ) ? (wb_jal ? use_writeback_PC_next : (wb_mem_read ? in_writeback_mem_data : in_writeback_alu_result)) :
|
||||
in_execute_alu_result; // last one should be deadbeef
|
||||
|
||||
|
||||
assign out_csr_fwd_data = csr_exe_fwd ? in_execute_alu_result :
|
||||
csr_mem_fwd ? in_memory_csr_result :
|
||||
in_execute_alu_result; // last one should be deadbeef
|
||||
assign out_csr_fwd_data = csr_exe_fwd ? in_execute_alu_result[0][31:0] :
|
||||
csr_mem_fwd ? in_memory_csr_result[31:0] :
|
||||
in_execute_alu_result[0][31:0]; // last one should be deadbeef
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -3,76 +3,36 @@
|
||||
`include "VX_define.v"
|
||||
|
||||
module VX_m_w_reg (
|
||||
input wire clk,
|
||||
input wire[31:0] in_alu_result[`NT_M1:0],
|
||||
input wire[31:0] in_mem_result[`NT_M1:0], // NEW
|
||||
input wire[4:0] in_rd,
|
||||
input wire[1:0] in_wb,
|
||||
input wire[4:0] in_rs1,
|
||||
input wire[4:0] in_rs2,
|
||||
input wire[31:0] in_PC_next,
|
||||
input wire in_freeze,
|
||||
input wire in_valid[`NT_M1:0],
|
||||
input wire[`NW_M1:0] in_warp_num,
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
VX_inst_mem_wb_inter VX_mem_wb,
|
||||
|
||||
output wire[31:0] out_alu_result[`NT_M1:0],
|
||||
output wire[31:0] out_mem_result[`NT_M1:0], // NEW
|
||||
input wire in_freeze,
|
||||
|
||||
output wire[`NT_M1:0][31:0] out_alu_result,
|
||||
output wire[`NT_M1:0][31:0] out_mem_result, // NEW
|
||||
output wire[4:0] out_rd,
|
||||
output wire[1:0] out_wb,
|
||||
output wire[4:0] out_rs1,
|
||||
output wire[4:0] out_rs2,
|
||||
output wire[31:0] out_PC_next,
|
||||
output wire out_valid[`NT_M1:0],
|
||||
output wire[`NT_M1:0] out_valid,
|
||||
output wire[`NW_M1:0] out_warp_num
|
||||
);
|
||||
|
||||
wire flush = 0;
|
||||
wire stall = in_freeze;
|
||||
|
||||
|
||||
reg[31:0] alu_result[`NT_M1:0];
|
||||
reg[31:0] mem_result[`NT_M1:0];
|
||||
reg[4:0] rd;
|
||||
reg[4:0] rs1;
|
||||
reg[4:0] rs2;
|
||||
reg[1:0] wb;
|
||||
reg[31:0] PC_next;
|
||||
reg valid[`NT_M1:0];
|
||||
reg[`NW_M1:0] warp_num;
|
||||
|
||||
initial begin
|
||||
// alu_result = 0;
|
||||
// mem_result = 0;
|
||||
rd = 0;
|
||||
rs1 = 0;
|
||||
rs2 = 0;
|
||||
wb = 0;
|
||||
PC_next = 0;
|
||||
warp_num = 0;
|
||||
// valid = 0;
|
||||
end
|
||||
|
||||
assign out_alu_result = alu_result;
|
||||
assign out_mem_result = mem_result;
|
||||
assign out_rd = rd;
|
||||
assign out_rs1 = rs1;
|
||||
assign out_rs2 = rs2;
|
||||
assign out_wb = wb;
|
||||
assign out_PC_next = PC_next;
|
||||
assign out_valid = valid;
|
||||
assign out_warp_num = warp_num;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(in_freeze == 1'b0) begin
|
||||
alu_result <= in_alu_result;
|
||||
mem_result <= in_mem_result;
|
||||
rd <= in_rd;
|
||||
rs1 <= in_rs1;
|
||||
rs2 <= in_rs2;
|
||||
wb <= in_wb;
|
||||
PC_next <= in_PC_next;
|
||||
valid <= in_valid;
|
||||
warp_num <= in_warp_num;
|
||||
end
|
||||
end
|
||||
VX_generic_register #(.N(313)) m_w_reg
|
||||
(
|
||||
.clk (clk),
|
||||
.reset(reset),
|
||||
.stall(stall),
|
||||
.flush(flush),
|
||||
.in ({VX_mem_wb.alu_result, VX_mem_wb.mem_result, VX_mem_wb.rd, VX_mem_wb.wb, VX_mem_wb.rs1, VX_mem_wb.rs2, VX_mem_wb.PC_next, VX_mem_wb.valid, VX_mem_wb.warp_num}),
|
||||
.out ({out_alu_result , out_mem_result , out_rd , out_wb , out_rs1 , out_rs2 , out_PC_next , out_valid , out_warp_num })
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
146
rtl/VX_memory.v
146
rtl/VX_memory.v
@@ -3,136 +3,70 @@
|
||||
|
||||
|
||||
module VX_memory (
|
||||
/* verilator lint_off UNUSED */
|
||||
input wire clk,
|
||||
/* verilator lint_on UNUSED */
|
||||
input wire[31:0] in_alu_result[`NT_M1:0],
|
||||
input wire[2:0] in_mem_read,
|
||||
input wire[2:0] in_mem_write,
|
||||
input wire[4:0] in_rd,
|
||||
input wire[1:0] in_wb,
|
||||
input wire[4:0] in_rs1,
|
||||
input wire[4:0] in_rs2,
|
||||
input wire[31:0] in_rd2[`NT_M1:0],
|
||||
input wire[31:0] in_PC_next,
|
||||
input wire[31:0] in_curr_PC,
|
||||
input wire[31:0] in_branch_offset,
|
||||
input wire[2:0] in_branch_type,
|
||||
input wire in_valid[`NT_M1:0],
|
||||
input wire[31:0] in_cache_driver_out_data[`NT_M1:0],
|
||||
input wire[`NW_M1:0] in_warp_num,
|
||||
VX_mem_req_inter VX_mem_req,
|
||||
VX_inst_mem_wb_inter VX_mem_wb,
|
||||
|
||||
output wire[31:0] out_alu_result[`NT_M1:0],
|
||||
output wire[31:0] out_mem_result[`NT_M1:0],
|
||||
output wire[4:0] out_rd,
|
||||
output wire[1:0] out_wb,
|
||||
output wire[4:0] out_rs1,
|
||||
output wire[4:0] out_rs2,
|
||||
output reg out_branch_dir,
|
||||
output wire[31:0] out_branch_dest,
|
||||
output wire out_delay,
|
||||
output wire[31:0] out_PC_next,
|
||||
output wire out_valid[`NT_M1:0],
|
||||
|
||||
output wire out_delay,
|
||||
|
||||
output wire out_branch_dir,
|
||||
output wire[31:0] out_branch_dest,
|
||||
|
||||
|
||||
input wire[31:0] in_cache_driver_out_data[`NT_M1:0],
|
||||
output wire[31:0] out_cache_driver_in_address[`NT_M1:0],
|
||||
output wire[2:0] out_cache_driver_in_mem_read,
|
||||
output wire[2:0] out_cache_driver_in_mem_write,
|
||||
output wire out_cache_driver_in_valid[`NT_M1:0],
|
||||
output wire[31:0] out_cache_driver_in_data[`NT_M1:0],
|
||||
output wire[`NW_M1:0] out_warp_num
|
||||
output wire[31:0] out_cache_driver_in_data[`NT_M1:0]
|
||||
);
|
||||
|
||||
// always @(in_mem_read, in_cache_driver_out_data) begin
|
||||
// if (in_mem_read == `LW_MEM_READ) begin
|
||||
// $display("PC: %h ----> Received: %h for addr: ", in_curr_PC, in_cache_driver_out_data[0], in_alu_result[0]);
|
||||
// end
|
||||
// end
|
||||
|
||||
// wire[15:0] addr_0 = in_alu_result[0][31:16];
|
||||
genvar index;
|
||||
for (index = 0; index <= `NT_M1; index = index + 1) begin
|
||||
assign out_cache_driver_in_address[index] = VX_mem_req.alu_result[index];
|
||||
assign out_cache_driver_in_data[index] = VX_mem_req.rd2[index];
|
||||
assign out_cache_driver_in_valid[index] = VX_mem_req.valid[index];
|
||||
|
||||
// wire sm_valid[`NT_M1:0];
|
||||
assign VX_mem_wb.mem_result[index] = in_cache_driver_out_data[index];
|
||||
|
||||
// assign sm_valid = (addr_0 != 16'hFFFF) ? in_valid : in_valid;
|
||||
|
||||
|
||||
// wire z_valid[`NT_M1:0];
|
||||
// assign z_valid = 0;
|
||||
end
|
||||
|
||||
assign out_delay = 1'b0;
|
||||
|
||||
assign out_cache_driver_in_address = in_alu_result;
|
||||
assign out_cache_driver_in_mem_read = in_mem_read;
|
||||
assign out_cache_driver_in_mem_write = in_mem_write;
|
||||
assign out_cache_driver_in_data = in_rd2;
|
||||
assign out_cache_driver_in_valid = in_valid;
|
||||
|
||||
// always @(*) begin
|
||||
// if (in_valid[0] && (in_mem_write == `SW_MEM_WRITE) && (in_alu_result[0] >= 32'h810049a0)) begin
|
||||
// $display("SW$ PC: %h - Warp: %h -> [%h]%h = %h || [%h]%h = %h",in_curr_PC, in_warp_num, in_valid[0], in_alu_result[0], in_rd2[0], in_valid[1], in_alu_result[1], in_rd2[1]);
|
||||
// end
|
||||
// end
|
||||
assign out_cache_driver_in_mem_read = VX_mem_req.mem_read;
|
||||
assign out_cache_driver_in_mem_write = VX_mem_req.mem_write;
|
||||
|
||||
|
||||
|
||||
// wire[31:0] sm_out_data[`NT_M1:0];
|
||||
assign VX_mem_wb.alu_result = VX_mem_req.alu_result;
|
||||
assign VX_mem_wb.rd = VX_mem_req.rd;
|
||||
assign VX_mem_wb.wb = VX_mem_req.wb;
|
||||
assign VX_mem_wb.rs1 = VX_mem_req.rs1;
|
||||
assign VX_mem_wb.rs2 = VX_mem_req.rs2;
|
||||
assign VX_mem_wb.PC_next = VX_mem_req.PC_next;
|
||||
assign VX_mem_wb.valid = VX_mem_req.valid;
|
||||
assign VX_mem_wb.warp_num = VX_mem_req.warp_num;
|
||||
|
||||
|
||||
// VX_shared_memory vx_shared_memory(
|
||||
// .clk (clk),
|
||||
// .in_address (in_alu_result),
|
||||
// .in_mem_read (in_mem_read),
|
||||
// .in_mem_write(in_mem_write),
|
||||
// .in_valid (sm_valid),
|
||||
// .in_data (in_rd2),
|
||||
// .out_data (sm_out_data)
|
||||
// );
|
||||
reg temp_branch_dir;
|
||||
|
||||
|
||||
// assign out_mem_result = sm_valid ? sm_out_data : in_cache_driver_out_data;
|
||||
assign out_mem_result = in_cache_driver_out_data;
|
||||
assign out_alu_result = in_alu_result;
|
||||
assign out_rd = in_rd;
|
||||
assign out_wb = in_wb;
|
||||
assign out_rs1 = in_rs1;
|
||||
assign out_rs2 = in_rs2;
|
||||
assign out_PC_next = in_PC_next;
|
||||
assign out_valid = in_valid;
|
||||
assign out_warp_num = in_warp_num;
|
||||
|
||||
// always @(*) begin
|
||||
|
||||
// if (in_cache_driver_out_data[0] != 32'hbabebabe)
|
||||
// begin
|
||||
// $display("MEM: data read from cache_driver: %h", in_cache_driver_out_data[0]);
|
||||
// end
|
||||
|
||||
// end
|
||||
|
||||
|
||||
assign out_branch_dest = $signed(in_curr_PC) + ($signed(in_branch_offset) << 1);
|
||||
assign out_branch_dest = $signed(VX_mem_req.curr_PC) + ($signed(VX_mem_req.branch_offset) << 1);
|
||||
|
||||
always @(*) begin
|
||||
case(in_branch_type)
|
||||
`BEQ: out_branch_dir = (in_alu_result[0] == 0) ? `TAKEN : `NOT_TAKEN;
|
||||
`BNE:
|
||||
begin
|
||||
out_branch_dir = (in_alu_result[0] == 0) ? `NOT_TAKEN : `TAKEN;
|
||||
end
|
||||
`BLT: out_branch_dir = (in_alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
|
||||
`BGT: out_branch_dir = (in_alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN;
|
||||
`BLTU:
|
||||
begin
|
||||
out_branch_dir = (in_alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
|
||||
if (in_warp_num == 1) begin
|
||||
// $display("BLTU PC:%h : %d < %d = %d", in_curr_PC, in_rs1, in_rs2, (in_alu_result[0][31] == 0));
|
||||
end
|
||||
end
|
||||
`BGTU: out_branch_dir = (in_alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN;
|
||||
`NO_BRANCH: out_branch_dir = `NOT_TAKEN;
|
||||
default: out_branch_dir = `NOT_TAKEN;
|
||||
case(VX_mem_req.branch_type)
|
||||
`BEQ: temp_branch_dir = (VX_mem_req.alu_result[0] == 0) ? `TAKEN : `NOT_TAKEN;
|
||||
`BNE: temp_branch_dir = (VX_mem_req.alu_result[0] == 0) ? `NOT_TAKEN : `TAKEN;
|
||||
`BLT: temp_branch_dir = (VX_mem_req.alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
|
||||
`BGT: temp_branch_dir = (VX_mem_req.alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN;
|
||||
`BLTU: temp_branch_dir = (VX_mem_req.alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
|
||||
`BGTU: temp_branch_dir = (VX_mem_req.alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN;
|
||||
`NO_BRANCH: temp_branch_dir = `NOT_TAKEN;
|
||||
default: temp_branch_dir = `NOT_TAKEN;
|
||||
endcase // in_branch_type
|
||||
end
|
||||
|
||||
|
||||
assign out_branch_dir = temp_branch_dir;
|
||||
|
||||
endmodule // Memory
|
||||
|
||||
|
||||
@@ -10,12 +10,12 @@ module VX_register_file (
|
||||
input wire[4:0] in_src1,
|
||||
input wire[4:0] in_src2,
|
||||
|
||||
output wire[31:0] out_regs[31:0],
|
||||
output wire[31:0][31:0] out_regs,
|
||||
output reg[31:0] out_src1_data,
|
||||
output reg[31:0] out_src2_data
|
||||
);
|
||||
|
||||
reg[31:0] registers[31:0];
|
||||
reg[31:0][31:0] registers;
|
||||
|
||||
wire[31:0] write_data;
|
||||
|
||||
|
||||
@@ -10,14 +10,14 @@ module VX_register_file_master_slave (
|
||||
input wire[4:0] in_src2,
|
||||
input wire in_wspawn,
|
||||
input wire in_to_wspawn,
|
||||
input wire[31:0] in_wspawn_regs[31:0],
|
||||
input wire[31:0][31:0] in_wspawn_regs,
|
||||
|
||||
output reg[31:0] out_src1_data,
|
||||
output reg[31:0] out_src2_data,
|
||||
output wire[31:0] out_regs[31:0]
|
||||
output wire[31:0][31:0] out_regs
|
||||
);
|
||||
|
||||
reg[31:0] registers[31:0];
|
||||
reg[31:0][31:0] registers;
|
||||
|
||||
wire[31:0] write_data;
|
||||
|
||||
|
||||
@@ -15,13 +15,13 @@ module VX_register_file_slave (
|
||||
input wire[4:0] in_src2,
|
||||
input wire in_clone,
|
||||
input wire in_to_clone,
|
||||
input wire[31:0] in_regs[31:0],
|
||||
input wire[31:0][31:0] in_regs,
|
||||
|
||||
output reg[31:0] out_src1_data,
|
||||
output reg[31:0] out_src2_data
|
||||
);
|
||||
|
||||
reg[31:0] registers[31:0];
|
||||
reg[31:0][31:0] registers;
|
||||
|
||||
wire[31:0] write_data;
|
||||
|
||||
|
||||
@@ -6,26 +6,24 @@ module VX_writeback (
|
||||
/* verilator lint_off UNUSED */
|
||||
input wire clk,
|
||||
/* verilator lint_off UNUSED */
|
||||
input wire[31:0] in_alu_result[`NT_M1:0],
|
||||
input wire[31:0] in_mem_result[`NT_M1:0],
|
||||
input wire[`NT_M1:0][31:0] in_alu_result,
|
||||
input wire[`NT_M1:0][31:0] in_mem_result,
|
||||
input wire[4:0] in_rd,
|
||||
input wire[1:0] in_wb,
|
||||
input wire[31:0] in_PC_next,
|
||||
/* verilator lint_off UNUSED */
|
||||
input wire in_valid[`NT_M1:0],
|
||||
input wire[`NT_M1:0] in_valid,
|
||||
/* verilator lint_on UNUSED */
|
||||
input wire [`NW_M1:0] in_warp_num,
|
||||
|
||||
output wire[31:0] out_write_data[`NT_M1:0],
|
||||
output wire[4:0] out_rd,
|
||||
output wire[1:0] out_wb,
|
||||
output wire[`NW_M1:0] out_warp_num
|
||||
|
||||
VX_wb_inter VX_writeback_inter
|
||||
);
|
||||
|
||||
wire is_jal;
|
||||
wire uses_alu;
|
||||
|
||||
wire[31:0] out_pc_data[`NT_M1:0];
|
||||
wire[`NT_M1:0][31:0] out_pc_data;
|
||||
|
||||
|
||||
// genvar index;
|
||||
@@ -49,20 +47,14 @@ module VX_writeback (
|
||||
assign is_jal = in_wb == `WB_JAL;
|
||||
assign uses_alu = in_wb == `WB_ALU;
|
||||
|
||||
assign out_write_data = is_jal ? out_pc_data :
|
||||
assign VX_writeback_inter.write_data = is_jal ? out_pc_data :
|
||||
uses_alu ? in_alu_result :
|
||||
in_mem_result;
|
||||
|
||||
|
||||
// always @(negedge clk) begin
|
||||
// if (in_wb != 0) begin
|
||||
// $display("[%h] WB Data: %h {%h}, to register: %d [%d %d]",in_PC_next - 4, out_write_data[0], in_mem_result[0], in_rd, in_valid[0], in_valid[1]);
|
||||
// end
|
||||
// end
|
||||
|
||||
assign out_rd = in_rd;
|
||||
assign out_wb = in_wb;
|
||||
assign out_warp_num = in_warp_num;
|
||||
assign VX_writeback_inter.wb_valid = in_valid;
|
||||
assign VX_writeback_inter.rd = in_rd;
|
||||
assign VX_writeback_inter.wb = in_wb;
|
||||
assign VX_writeback_inter.wb_warp_num = in_warp_num;
|
||||
|
||||
|
||||
endmodule // VX_writeback
|
||||
412
rtl/Vortex.v
412
rtl/Vortex.v
@@ -6,10 +6,7 @@ module Vortex(
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
input wire[31:0] icache_response_instruction,
|
||||
output wire[31:0] icache_request_pc_address,
|
||||
// input wire[31:0] icache_instruction,
|
||||
// output wire icache_request_valid,
|
||||
// output wire[31:0] icache_PC,
|
||||
output wire[31:0] icache_request_pc_address,
|
||||
input wire[31:0] in_cache_driver_out_data[`NT_M1:0],
|
||||
output wire[31:0] out_cache_driver_in_address[`NT_M1:0],
|
||||
output wire[2:0] out_cache_driver_in_mem_read,
|
||||
@@ -26,73 +23,14 @@ module Vortex(
|
||||
|
||||
|
||||
// From fetch
|
||||
wire[31:0] fetch_instruction;
|
||||
wire fetch_delay;
|
||||
wire[31:0] fetch_curr_PC;
|
||||
wire fetch_valid[`NT_M1:0];
|
||||
wire[`NW_M1:0] fetch_warp_num;
|
||||
wire fetch_ebreak;
|
||||
wire[`NW_M1:0] fetch_which_warp;
|
||||
|
||||
// From f_d_register
|
||||
wire[31:0] f_d_instruction;
|
||||
wire[31:0] f_d_curr_PC;
|
||||
wire f_d_valid[`NT_M1:0];
|
||||
wire[`NW_M1:0] f_d_warp_num;
|
||||
|
||||
// From decode
|
||||
wire decode_branch_stall;
|
||||
wire[11:0] decode_csr_address;
|
||||
wire decode_is_csr;
|
||||
wire[31:0] decode_csr_mask;
|
||||
wire[4:0] decode_rd;
|
||||
wire[4:0] decode_rs1;
|
||||
wire[4:0] decode_rs2;
|
||||
wire[31:0] decode_a_reg_data[`NT_M1:0];
|
||||
wire[31:0] decode_b_reg_data[`NT_M1:0];
|
||||
wire[1:0] decode_wb;
|
||||
wire[4:0] decode_alu_op;
|
||||
wire decode_rs2_src;
|
||||
reg[31:0] decode_itype_immed;
|
||||
wire[2:0] decode_mem_read;
|
||||
wire[2:0] decode_mem_write;
|
||||
reg[2:0] decode_branch_type;
|
||||
reg decode_jal;
|
||||
reg[31:0] decode_jal_offset;
|
||||
reg[19:0] decode_upper_immed;
|
||||
wire[31:0] decode_PC_next;
|
||||
wire decode_valid[`NT_M1:0];
|
||||
wire decode_clone_stall;
|
||||
wire decode_change_mask;
|
||||
wire decode_thread_mask[`NT_M1:0];
|
||||
wire[`NW_M1:0] decode_warp_num;
|
||||
wire decode_wspawn;
|
||||
wire[31:0] decode_wspawn_pc;
|
||||
wire decode_ebreak;
|
||||
|
||||
// From d_e_register
|
||||
wire[11:0] d_e_csr_address;
|
||||
wire d_e_is_csr;
|
||||
wire[31:0] d_e_csr_mask;
|
||||
wire[4:0] d_e_rd;
|
||||
wire[4:0] d_e_rs1;
|
||||
wire[4:0] d_e_rs2;
|
||||
wire[31:0] d_e_a_reg_data[`NT_M1:0];
|
||||
wire[31:0] d_e_b_reg_data[`NT_M1:0];
|
||||
wire[4:0] d_e_alu_op;
|
||||
wire[1:0] d_e_wb;
|
||||
wire d_e_rs2_src;
|
||||
wire[31:0] d_e_itype_immed;
|
||||
wire[2:0] d_e_mem_read;
|
||||
wire[2:0] d_e_mem_write;
|
||||
wire[2:0] d_e_branch_type;
|
||||
wire[19:0] d_e_upper_immed;
|
||||
wire[31:0] d_e_curr_PC;
|
||||
wire d_e_jal;
|
||||
wire[31:0] d_e_jal_offset;
|
||||
wire[31:0] d_e_PC_next;
|
||||
wire d_e_valid[`NT_M1:0];
|
||||
wire[`NW_M1:0] d_e_warp_num;
|
||||
|
||||
|
||||
// From execute
|
||||
@@ -100,21 +38,10 @@ wire execute_branch_stall;
|
||||
wire[11:0] execute_csr_address;
|
||||
wire execute_is_csr;
|
||||
reg[31:0] execute_csr_result;
|
||||
reg[31:0] execute_alu_result[`NT_M1:0];
|
||||
wire[4:0] execute_rd;
|
||||
wire[1:0] execute_wb;
|
||||
wire[4:0] execute_rs1;
|
||||
wire[4:0] execute_rs2;
|
||||
wire[31:0] execute_a_reg_data[`NT_M1:0];
|
||||
wire[31:0] execute_b_reg_data[`NT_M1:0];
|
||||
wire[2:0] execute_mem_read;
|
||||
wire[2:0] execute_mem_write;
|
||||
wire[`NT_M1:0][31:0] execute_a_reg_data;
|
||||
wire[`NT_M1:0][31:0] execute_b_reg_data;
|
||||
wire execute_jal;
|
||||
wire[31:0] execute_jal_dest;
|
||||
wire[31:0] execute_branch_offset;
|
||||
wire[31:0] execute_PC_next;
|
||||
wire execute_valid[`NT_M1:0];
|
||||
wire[`NW_M1:0] execute_warp_num;
|
||||
|
||||
|
||||
// From e_m_register
|
||||
@@ -123,42 +50,20 @@ wire[31:0] e_m_jal_dest;
|
||||
wire[11:0] e_m_csr_address;
|
||||
wire e_m_is_csr;
|
||||
wire[31:0] e_m_csr_result;
|
||||
wire[31:0] e_m_alu_result[`NT_M1:0];
|
||||
wire[4:0] e_m_rd;
|
||||
wire[1:0] e_m_wb;
|
||||
wire[4:0] e_m_rs1;
|
||||
/* verilator lint_off UNUSED */
|
||||
wire[31:0] e_m_a_reg_data[`NT_M1:0];
|
||||
wire[`NT_M1:0][31:0] e_m_a_reg_data;
|
||||
wire[`NT_M1:0][31:0] e_m_b_reg_data;
|
||||
/* verilator lint_on UNUSED */
|
||||
wire[31:0] e_m_b_reg_data[`NT_M1:0];
|
||||
wire[4:0] e_m_rs2;
|
||||
wire[2:0] e_m_mem_read;
|
||||
wire[2:0] e_m_mem_write;
|
||||
wire[31:0] e_m_curr_PC;
|
||||
wire[31:0] e_m_branch_offset;
|
||||
wire[2:0] e_m_branch_type;
|
||||
wire[31:0] e_m_PC_next;
|
||||
wire e_m_valid[`NT_M1:0];
|
||||
wire[`NW_M1:0] e_m_warp_num;
|
||||
|
||||
|
||||
// From memory
|
||||
wire memory_delay;
|
||||
wire memory_branch_dir;
|
||||
wire[31:0] memory_branch_dest;
|
||||
wire[31:0] memory_alu_result[`NT_M1:0];
|
||||
wire[31:0] memory_mem_result[`NT_M1:0];
|
||||
wire[4:0] memory_rd;
|
||||
wire[1:0] memory_wb;
|
||||
wire[4:0] memory_rs1;
|
||||
wire[4:0] memory_rs2;
|
||||
wire[31:0] memory_PC_next;
|
||||
wire memory_valid[`NT_M1:0];
|
||||
wire[`NW_M1:0] memory_warp_num;
|
||||
|
||||
// From m_w_register
|
||||
wire[31:0] m_w_alu_result[`NT_M1:0];
|
||||
wire[31:0] m_w_mem_result[`NT_M1:0];
|
||||
wire[`NT_M1:0][31:0] m_w_alu_result;
|
||||
wire[`NT_M1:0][31:0] m_w_mem_result;
|
||||
wire[4:0] m_w_rd;
|
||||
wire[1:0] m_w_wb;
|
||||
/* verilator lint_off UNUSED */
|
||||
@@ -166,14 +71,8 @@ wire[4:0] m_w_rs1;
|
||||
wire[4:0] m_w_rs2;
|
||||
/* verilator lint_on UNUSED */
|
||||
wire[31:0] m_w_PC_next;
|
||||
wire m_w_valid[`NT_M1:0];
|
||||
wire[`NW_M1:0] m_w_warp_num;
|
||||
|
||||
// From writeback
|
||||
wire[31:0] writeback_write_data[`NT_M1:0];
|
||||
wire[4:0] writeback_rd;
|
||||
wire[1:0] writeback_wb;
|
||||
wire[`NW_M1:0] writeback_warp_num;
|
||||
wire[`NT_M1:0] m_w_valid;
|
||||
wire[`NW_M1:0] m_w_warp_num;
|
||||
|
||||
// From csr handler
|
||||
wire[31:0] csr_decode_csr_data;
|
||||
@@ -187,8 +86,8 @@ wire forwarding_src2_fwd;
|
||||
wire forwarding_csr_fwd;
|
||||
wire[31:0] forwarding_csr_fwd_data;
|
||||
/* verilator lint_on UNUSED */
|
||||
wire[31:0] forwarding_src1_fwd_data[`NT_M1:0];
|
||||
wire[31:0] forwarding_src2_fwd_data[`NT_M1:0];
|
||||
wire[`NT_M1:0][31:0] forwarding_src1_fwd_data;
|
||||
wire[`NT_M1:0][31:0] forwarding_src2_fwd_data;
|
||||
|
||||
|
||||
// Internal
|
||||
@@ -204,7 +103,21 @@ assign out_ebreak = fetch_ebreak;
|
||||
|
||||
icache_response_t icache_response_fe;
|
||||
icache_request_t icache_request_fe;
|
||||
fe_inst_meta_de_t fe_inst_meta_fd;
|
||||
|
||||
VX_inst_meta_inter fe_inst_meta_fd();
|
||||
VX_inst_meta_inter fd_inst_meta_de();
|
||||
|
||||
VX_frE_to_bckE_req_inter VX_frE_to_bckE_req();
|
||||
VX_frE_to_bckE_req_inter VX_bckE_req();
|
||||
|
||||
VX_mem_req_inter VX_exe_mem_req();
|
||||
VX_mem_req_inter VX_mem_req();
|
||||
|
||||
|
||||
VX_inst_mem_wb_inter VX_mem_wb();
|
||||
|
||||
VX_warp_ctl_inter VX_warp_ctl();
|
||||
VX_wb_inter VX_writeback_inter();
|
||||
|
||||
assign icache_response_fe.instruction = icache_response_instruction;
|
||||
assign icache_request_pc_address = icache_request_fe.pc_address;
|
||||
@@ -223,21 +136,12 @@ VX_fetch vx_fetch(
|
||||
.in_jal_dest (e_m_jal_dest),
|
||||
.in_interrupt (interrupt),
|
||||
.in_debug (debug),
|
||||
.in_thread_mask (decode_thread_mask),
|
||||
.in_change_mask (decode_change_mask),
|
||||
.in_decode_warp_num (decode_warp_num),
|
||||
.in_memory_warp_num (memory_warp_num),
|
||||
.in_wspawn (decode_wspawn),
|
||||
.in_wspawn_pc (decode_wspawn_pc),
|
||||
.in_ebreak (decode_ebreak),
|
||||
.in_memory_warp_num (VX_mem_wb.warp_num),
|
||||
.icache_response (icache_response_fe),
|
||||
.VX_warp_ctl (VX_warp_ctl),
|
||||
|
||||
.icache_request (icache_request_fe),
|
||||
.out_instruction (fetch_instruction),
|
||||
.out_delay (fetch_delay),
|
||||
.out_curr_PC (fetch_curr_PC),
|
||||
.out_warp_num (fetch_warp_num),
|
||||
.out_valid (fetch_valid),
|
||||
.out_ebreak (fetch_ebreak),
|
||||
.out_which_wspawn (fetch_which_warp),
|
||||
.fe_inst_meta_fd (fe_inst_meta_fd)
|
||||
@@ -247,212 +151,78 @@ VX_fetch vx_fetch(
|
||||
VX_f_d_reg vx_f_d_reg(
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.in_instruction (fetch_instruction),
|
||||
.in_valid (fetch_valid),
|
||||
.in_curr_PC (fetch_curr_PC),
|
||||
.in_fwd_stall (forwarding_fwd_stall),
|
||||
.in_freeze (total_freeze),
|
||||
.in_clone_stall (decode_clone_stall),
|
||||
.in_warp_num (fetch_warp_num),
|
||||
.out_instruction(f_d_instruction),
|
||||
.out_curr_PC (f_d_curr_PC),
|
||||
.out_valid (f_d_valid),
|
||||
.out_warp_num (f_d_warp_num),
|
||||
.fe_inst_meta_fd(fe_inst_meta_fd)
|
||||
.fe_inst_meta_fd(fe_inst_meta_fd),
|
||||
.fd_inst_meta_de(fd_inst_meta_de)
|
||||
);
|
||||
|
||||
|
||||
VX_decode vx_decode(
|
||||
.clk (clk),
|
||||
.in_instruction (f_d_instruction),
|
||||
.in_curr_PC (f_d_curr_PC),
|
||||
.in_valid (f_d_valid),
|
||||
.in_write_data (writeback_write_data),
|
||||
.in_rd (writeback_rd),
|
||||
.in_wb (writeback_wb),
|
||||
.in_wb_warp_num (writeback_warp_num),
|
||||
.in_wb_valid (m_w_valid),
|
||||
.fd_inst_meta_de (fd_inst_meta_de),
|
||||
.VX_writeback_inter(VX_writeback_inter),
|
||||
.in_src1_fwd (forwarding_src1_fwd),
|
||||
.in_src1_fwd_data(forwarding_src1_fwd_data),
|
||||
.in_src2_fwd (forwarding_src2_fwd),
|
||||
.in_src2_fwd_data(forwarding_src2_fwd_data),
|
||||
.in_warp_num (f_d_warp_num),
|
||||
.in_which_wspawn (fetch_which_warp),
|
||||
|
||||
.out_csr_address (decode_csr_address),
|
||||
.out_is_csr (decode_is_csr),
|
||||
.out_csr_mask (decode_csr_mask),
|
||||
.out_rd (decode_rd),
|
||||
.out_rs1 (decode_rs1),
|
||||
.out_rs2 (decode_rs2),
|
||||
.out_a_reg_data (decode_a_reg_data),
|
||||
.out_b_reg_data (decode_b_reg_data),
|
||||
.out_wb (decode_wb),
|
||||
.out_alu_op (decode_alu_op),
|
||||
.out_rs2_src (decode_rs2_src),
|
||||
.out_itype_immed (decode_itype_immed),
|
||||
.out_mem_read (decode_mem_read),
|
||||
.out_mem_write (decode_mem_write),
|
||||
.out_branch_type (decode_branch_type),
|
||||
.out_branch_stall(decode_branch_stall),
|
||||
.out_jal (decode_jal),
|
||||
.out_jal_offset (decode_jal_offset),
|
||||
.out_upper_immed (decode_upper_immed),
|
||||
.out_PC_next (decode_PC_next),
|
||||
.out_valid (decode_valid),
|
||||
.out_clone_stall (decode_clone_stall),
|
||||
.out_change_mask (decode_change_mask),
|
||||
.out_thread_mask (decode_thread_mask),
|
||||
.out_warp_num (decode_warp_num),
|
||||
.out_wspawn (decode_wspawn),
|
||||
.out_wspawn_pc (decode_wspawn_pc),
|
||||
.out_ebreak (decode_ebreak)
|
||||
.VX_frE_to_bckE_req(VX_frE_to_bckE_req),
|
||||
.VX_warp_ctl (VX_warp_ctl),
|
||||
.out_clone_stall (decode_clone_stall),
|
||||
.out_branch_stall (decode_branch_stall)
|
||||
);
|
||||
|
||||
|
||||
VX_d_e_reg vx_d_e_reg(
|
||||
.clk (clk),
|
||||
.in_rd (decode_rd),
|
||||
.in_rs1 (decode_rs1),
|
||||
.in_rs2 (decode_rs2),
|
||||
.in_a_reg_data (decode_a_reg_data),
|
||||
.in_b_reg_data (decode_b_reg_data),
|
||||
.in_alu_op (decode_alu_op),
|
||||
.in_wb (decode_wb),
|
||||
.in_rs2_src (decode_rs2_src),
|
||||
.in_itype_immed (decode_itype_immed),
|
||||
.in_mem_read (decode_mem_read),
|
||||
.in_mem_write (decode_mem_write),
|
||||
.in_PC_next (decode_PC_next),
|
||||
.in_branch_type (decode_branch_type),
|
||||
.reset (reset),
|
||||
.in_fwd_stall (forwarding_fwd_stall),
|
||||
.in_branch_stall(execute_branch_stall),
|
||||
.in_upper_immed (decode_upper_immed),
|
||||
.in_csr_address (decode_csr_address),
|
||||
.in_is_csr (decode_is_csr),
|
||||
.in_csr_mask (decode_csr_mask),
|
||||
.in_curr_PC (f_d_curr_PC),
|
||||
.in_jal (decode_jal),
|
||||
.in_jal_offset (decode_jal_offset),
|
||||
.in_freeze (total_freeze),
|
||||
.in_valid (decode_valid),
|
||||
.in_clone_stall (decode_clone_stall),
|
||||
.in_warp_num (decode_warp_num),
|
||||
|
||||
.out_csr_address(d_e_csr_address),
|
||||
.out_is_csr (d_e_is_csr),
|
||||
.out_csr_mask (d_e_csr_mask),
|
||||
.out_rd (d_e_rd),
|
||||
.out_rs1 (d_e_rs1),
|
||||
.out_rs2 (d_e_rs2),
|
||||
.out_a_reg_data (d_e_a_reg_data),
|
||||
.out_b_reg_data (d_e_b_reg_data),
|
||||
.out_alu_op (d_e_alu_op),
|
||||
.out_wb (d_e_wb),
|
||||
.out_rs2_src (d_e_rs2_src),
|
||||
.out_itype_immed(d_e_itype_immed),
|
||||
.out_mem_read (d_e_mem_read),
|
||||
.out_mem_write (d_e_mem_write),
|
||||
.out_branch_type(d_e_branch_type),
|
||||
.out_upper_immed(d_e_upper_immed),
|
||||
.out_curr_PC (d_e_curr_PC),
|
||||
.out_jal (d_e_jal),
|
||||
.out_jal_offset (d_e_jal_offset),
|
||||
.out_PC_next (d_e_PC_next),
|
||||
.out_valid (d_e_valid),
|
||||
.out_warp_num (d_e_warp_num)
|
||||
.VX_frE_to_bckE_req(VX_frE_to_bckE_req),
|
||||
.VX_bckE_req (VX_bckE_req)
|
||||
);
|
||||
|
||||
VX_execute vx_execute(
|
||||
.in_rd (d_e_rd),
|
||||
.in_rs1 (d_e_rs1),
|
||||
.in_rs2 (d_e_rs2),
|
||||
.in_a_reg_data (d_e_a_reg_data),
|
||||
.in_b_reg_data (d_e_b_reg_data),
|
||||
.in_alu_op (d_e_alu_op),
|
||||
.in_wb (d_e_wb),
|
||||
.in_rs2_src (d_e_rs2_src),
|
||||
.in_itype_immed (d_e_itype_immed),
|
||||
.in_mem_read (d_e_mem_read),
|
||||
.in_mem_write (d_e_mem_write),
|
||||
.in_PC_next (d_e_PC_next),
|
||||
.in_branch_type (d_e_branch_type),
|
||||
.in_upper_immed (d_e_upper_immed),
|
||||
.in_csr_address (d_e_csr_address),
|
||||
.in_is_csr (d_e_is_csr),
|
||||
.VX_bckE_req (VX_bckE_req),
|
||||
.in_csr_data (csr_decode_csr_data),
|
||||
.in_csr_mask (d_e_csr_mask),
|
||||
.in_jal (d_e_jal),
|
||||
.in_jal_offset (d_e_jal_offset),
|
||||
.in_curr_PC (d_e_curr_PC),
|
||||
.in_valid (d_e_valid),
|
||||
.in_warp_num (d_e_warp_num),
|
||||
|
||||
.VX_exe_mem_req (VX_exe_mem_req),
|
||||
.out_csr_address (execute_csr_address),
|
||||
.out_is_csr (execute_is_csr),
|
||||
.out_csr_result (execute_csr_result),
|
||||
.out_alu_result (execute_alu_result),
|
||||
.out_rd (execute_rd),
|
||||
.out_wb (execute_wb),
|
||||
.out_rs1 (execute_rs1),
|
||||
.out_rs2 (execute_rs2),
|
||||
.out_a_reg_data (execute_a_reg_data),
|
||||
.out_b_reg_data (execute_b_reg_data),
|
||||
.out_mem_read (execute_mem_read),
|
||||
.out_mem_write (execute_mem_write),
|
||||
.out_jal (execute_jal),
|
||||
.out_jal_dest (execute_jal_dest),
|
||||
.out_branch_offset(execute_branch_offset),
|
||||
.out_branch_stall (execute_branch_stall),
|
||||
.out_PC_next (execute_PC_next),
|
||||
.out_valid (execute_valid),
|
||||
.out_warp_num (execute_warp_num)
|
||||
.out_a_reg_data (execute_a_reg_data),
|
||||
.out_b_reg_data (execute_b_reg_data)
|
||||
);
|
||||
|
||||
VX_e_m_reg vx_e_m_reg(
|
||||
.clk (clk),
|
||||
.in_alu_result (execute_alu_result),
|
||||
.in_rd (execute_rd),
|
||||
.in_wb (execute_wb),
|
||||
.in_rs1 (execute_rs1),
|
||||
.in_rs2 (execute_rs2),
|
||||
.in_a_reg_data (execute_a_reg_data),
|
||||
.in_b_reg_data (execute_b_reg_data),
|
||||
.in_mem_read (execute_mem_read),
|
||||
.in_mem_write (execute_mem_write),
|
||||
.in_PC_next (execute_PC_next),
|
||||
.reset (reset),
|
||||
.in_csr_address (execute_csr_address),
|
||||
.in_is_csr (execute_is_csr),
|
||||
.in_csr_result (execute_csr_result),
|
||||
.in_curr_PC (d_e_curr_PC),
|
||||
.in_branch_offset (execute_branch_offset),
|
||||
.in_branch_type (d_e_branch_type),
|
||||
.in_jal (execute_jal),
|
||||
.in_jal_dest (execute_jal_dest),
|
||||
.in_freeze (total_freeze),
|
||||
.in_valid (execute_valid),
|
||||
.in_warp_num (execute_warp_num),
|
||||
.VX_exe_mem_req (VX_exe_mem_req),
|
||||
.in_a_reg_data (execute_a_reg_data),
|
||||
.in_b_reg_data (execute_b_reg_data),
|
||||
|
||||
.VX_mem_req (VX_mem_req),
|
||||
.out_csr_address (e_m_csr_address),
|
||||
.out_is_csr (e_m_is_csr),
|
||||
.out_csr_result (e_m_csr_result),
|
||||
.out_alu_result (e_m_alu_result),
|
||||
.out_rd (e_m_rd),
|
||||
.out_wb (e_m_wb),
|
||||
.out_rs1 (e_m_rs1),
|
||||
.out_rs2 (e_m_rs2),
|
||||
.out_a_reg_data (e_m_a_reg_data),
|
||||
.out_b_reg_data (e_m_b_reg_data),
|
||||
.out_mem_read (e_m_mem_read),
|
||||
.out_mem_write (e_m_mem_write),
|
||||
.out_curr_PC (e_m_curr_PC),
|
||||
.out_branch_offset(e_m_branch_offset),
|
||||
.out_branch_type (e_m_branch_type),
|
||||
.out_jal (e_m_jal),
|
||||
.out_jal_dest (e_m_jal_dest),
|
||||
.out_PC_next (e_m_PC_next),
|
||||
.out_valid (e_m_valid),
|
||||
.out_warp_num (e_m_warp_num)
|
||||
.out_jal_dest (e_m_jal_dest)
|
||||
);
|
||||
|
||||
// wire[31:0] use_rd2[`NT_M1:0];
|
||||
@@ -461,35 +231,15 @@ VX_e_m_reg vx_e_m_reg(
|
||||
// assign use_rd2[1] = e_m_reg_data[3];
|
||||
|
||||
VX_memory vx_memory(
|
||||
.clk (clk),
|
||||
.in_alu_result (e_m_alu_result),
|
||||
.in_mem_read (e_m_mem_read),
|
||||
.in_mem_write (e_m_mem_write),
|
||||
.in_rd (e_m_rd),
|
||||
.in_wb (e_m_wb),
|
||||
.in_rs1 (e_m_rs1),
|
||||
.in_rs2 (e_m_rs2),
|
||||
.in_rd2 (e_m_b_reg_data),
|
||||
.in_PC_next (e_m_PC_next),
|
||||
.in_curr_PC (e_m_curr_PC),
|
||||
.in_branch_offset (e_m_branch_offset),
|
||||
.in_branch_type (e_m_branch_type),
|
||||
.in_valid (e_m_valid),
|
||||
.in_cache_driver_out_data (in_cache_driver_out_data),
|
||||
.in_warp_num (e_m_warp_num),
|
||||
.VX_mem_req (VX_mem_req),
|
||||
.VX_mem_wb (VX_mem_wb),
|
||||
|
||||
.out_delay (memory_delay),
|
||||
|
||||
.out_alu_result (memory_alu_result),
|
||||
.out_mem_result (memory_mem_result),
|
||||
.out_rd (memory_rd),
|
||||
.out_wb (memory_wb),
|
||||
.out_rs1 (memory_rs1),
|
||||
.out_rs2 (memory_rs2),
|
||||
.out_branch_dir (memory_branch_dir),
|
||||
.out_branch_dest (memory_branch_dest),
|
||||
.out_delay (memory_delay),
|
||||
.out_PC_next (memory_PC_next),
|
||||
.out_valid (memory_valid),
|
||||
.out_warp_num (memory_warp_num),
|
||||
|
||||
.in_cache_driver_out_data (in_cache_driver_out_data),
|
||||
.out_cache_driver_in_address (out_cache_driver_in_address),
|
||||
.out_cache_driver_in_mem_read (out_cache_driver_in_mem_read),
|
||||
.out_cache_driver_in_mem_write(out_cache_driver_in_mem_write),
|
||||
@@ -499,16 +249,10 @@ VX_memory vx_memory(
|
||||
|
||||
VX_m_w_reg vx_m_w_reg(
|
||||
.clk (clk),
|
||||
.in_alu_result (memory_alu_result),
|
||||
.in_mem_result (memory_mem_result),
|
||||
.in_rd (memory_rd),
|
||||
.in_wb (memory_wb),
|
||||
.in_rs1 (memory_rs1),
|
||||
.in_rs2 (memory_rs2),
|
||||
.in_PC_next (memory_PC_next),
|
||||
.reset (reset),
|
||||
.VX_mem_wb (VX_mem_wb),
|
||||
.in_freeze (total_freeze),
|
||||
.in_valid (memory_valid),
|
||||
.in_warp_num (memory_warp_num),
|
||||
|
||||
|
||||
.out_alu_result(m_w_alu_result),
|
||||
.out_mem_result(m_w_mem_result),
|
||||
@@ -531,44 +275,40 @@ VX_writeback vx_writeback(
|
||||
.in_PC_next (m_w_PC_next),
|
||||
.in_valid (m_w_valid),
|
||||
.in_warp_num (m_w_warp_num),
|
||||
|
||||
.out_write_data(writeback_write_data),
|
||||
.out_rd (writeback_rd),
|
||||
.out_wb (writeback_wb),
|
||||
.out_warp_num (writeback_warp_num)
|
||||
.VX_writeback_inter(VX_writeback_inter)
|
||||
);
|
||||
|
||||
|
||||
VX_forwarding vx_forwarding(
|
||||
.in_decode_src1 (decode_rs1),
|
||||
.in_decode_src2 (decode_rs2),
|
||||
.in_decode_csr_address (decode_csr_address),
|
||||
.in_decode_warp_num (decode_warp_num),
|
||||
.in_decode_src1 (VX_frE_to_bckE_req.rs1),
|
||||
.in_decode_src2 (VX_frE_to_bckE_req.rs2),
|
||||
.in_decode_csr_address (VX_frE_to_bckE_req.csr_address),
|
||||
.in_decode_warp_num (VX_frE_to_bckE_req.warp_num),
|
||||
|
||||
.in_execute_dest (execute_rd),
|
||||
.in_execute_wb (execute_wb),
|
||||
.in_execute_alu_result (execute_alu_result),
|
||||
.in_execute_PC_next (execute_PC_next),
|
||||
.in_execute_dest (VX_exe_mem_req.rd),
|
||||
.in_execute_wb (VX_exe_mem_req.wb),
|
||||
.in_execute_alu_result (VX_exe_mem_req.alu_result),
|
||||
.in_execute_PC_next (VX_exe_mem_req.PC_next),
|
||||
.in_execute_is_csr (execute_is_csr),
|
||||
.in_execute_csr_address (execute_csr_address),
|
||||
.in_execute_warp_num (execute_warp_num),
|
||||
.in_execute_warp_num (VX_exe_mem_req.warp_num),
|
||||
|
||||
.in_memory_dest (memory_rd),
|
||||
.in_memory_wb (memory_wb),
|
||||
.in_memory_alu_result (memory_alu_result),
|
||||
.in_memory_mem_data (memory_mem_result),
|
||||
.in_memory_PC_next (memory_PC_next),
|
||||
.in_memory_dest (VX_mem_wb.rd),
|
||||
.in_memory_wb (VX_mem_wb.wb),
|
||||
.in_memory_alu_result (VX_mem_wb.alu_result),
|
||||
.in_memory_mem_data (VX_mem_wb.mem_result),
|
||||
.in_memory_PC_next (VX_mem_wb.PC_next),
|
||||
.in_memory_is_csr (e_m_is_csr),
|
||||
.in_memory_csr_address (e_m_csr_address),
|
||||
.in_memory_csr_result (e_m_csr_result),
|
||||
.in_memory_warp_num (memory_warp_num),
|
||||
.in_memory_warp_num (VX_mem_wb.warp_num),
|
||||
|
||||
.in_writeback_dest (m_w_rd),
|
||||
.in_writeback_wb (m_w_wb),
|
||||
.in_writeback_alu_result(m_w_alu_result),
|
||||
.in_writeback_mem_data (m_w_mem_result),
|
||||
.in_writeback_PC_next (m_w_PC_next),
|
||||
.in_writeback_warp_num (writeback_warp_num),
|
||||
.in_writeback_warp_num (VX_writeback_inter.wb_warp_num),
|
||||
|
||||
.out_src1_fwd (forwarding_src1_fwd),
|
||||
.out_src2_fwd (forwarding_src2_fwd),
|
||||
@@ -581,7 +321,7 @@ VX_forwarding vx_forwarding(
|
||||
|
||||
VX_csr_handler vx_csr_handler(
|
||||
.clk (clk),
|
||||
.in_decode_csr_address(decode_csr_address),
|
||||
.in_decode_csr_address(VX_frE_to_bckE_req.csr_address),
|
||||
.in_mem_csr_address (e_m_csr_address),
|
||||
.in_mem_is_csr (e_m_is_csr),
|
||||
.in_mem_csr_result (e_m_csr_result),
|
||||
|
||||
14
rtl/buses.vh
14
rtl/buses.vh
@@ -18,14 +18,14 @@ typedef struct packed
|
||||
logic[31:0] instruction;
|
||||
} icache_response_t;
|
||||
|
||||
typedef struct packed
|
||||
{
|
||||
logic[31:0] instruction;
|
||||
logic[31:0] inst_pc;
|
||||
logic[`NW_M1:0] warp_num;
|
||||
logic[`NT_M1:0] valid;
|
||||
// typedef struct packed
|
||||
// {
|
||||
// logic[31:0] instruction;
|
||||
// logic[31:0] inst_pc;
|
||||
// logic[`NW_M1:0] warp_num;
|
||||
// logic[`NT_M1:0] valid;
|
||||
|
||||
} fe_inst_meta_de_t;
|
||||
// } fe_inst_meta_de_t;
|
||||
|
||||
|
||||
`endif
|
||||
|
||||
BIN
rtl/interfaces/._VX_frE_to_bckE_req_inter.v
Normal file
BIN
rtl/interfaces/._VX_frE_to_bckE_req_inter.v
Normal file
Binary file not shown.
BIN
rtl/interfaces/._VX_inst_mem_wb_inter.v
Normal file
BIN
rtl/interfaces/._VX_inst_mem_wb_inter.v
Normal file
Binary file not shown.
BIN
rtl/interfaces/._VX_inst_meta_inter.v
Normal file
BIN
rtl/interfaces/._VX_inst_meta_inter.v
Normal file
Binary file not shown.
BIN
rtl/interfaces/._VX_mem_req_inter.v
Normal file
BIN
rtl/interfaces/._VX_mem_req_inter.v
Normal file
Binary file not shown.
BIN
rtl/interfaces/._VX_warp_ctl_inter.v
Normal file
BIN
rtl/interfaces/._VX_warp_ctl_inter.v
Normal file
Binary file not shown.
BIN
rtl/interfaces/._VX_wb_inter.v
Normal file
BIN
rtl/interfaces/._VX_wb_inter.v
Normal file
Binary file not shown.
90
rtl/interfaces/VX_frE_to_bckE_req_inter.v
Normal file
90
rtl/interfaces/VX_frE_to_bckE_req_inter.v
Normal file
@@ -0,0 +1,90 @@
|
||||
|
||||
`include "VX_define.v"
|
||||
|
||||
`ifndef VX_FrE_to_BE_INTER
|
||||
|
||||
`define VX_FrE_to_BE_INTER
|
||||
|
||||
interface VX_frE_to_bckE_req_inter ();
|
||||
|
||||
wire[11:0] csr_address;
|
||||
wire is_csr;
|
||||
wire[31:0] csr_mask;
|
||||
wire[4:0] rd;
|
||||
wire[4:0] rs1;
|
||||
wire[4:0] rs2;
|
||||
wire[`NT_M1:0][31:0] a_reg_data;
|
||||
wire[`NT_M1:0][31:0] b_reg_data;
|
||||
wire[4:0] alu_op;
|
||||
wire[1:0] wb;
|
||||
wire rs2_src;
|
||||
wire[31:0] itype_immed;
|
||||
wire[2:0] mem_read;
|
||||
wire[2:0] mem_write;
|
||||
wire[2:0] branch_type;
|
||||
wire[19:0] upper_immed;
|
||||
wire[31:0] curr_PC;
|
||||
wire jal;
|
||||
wire[31:0] jal_offset;
|
||||
wire[31:0] PC_next;
|
||||
wire[`NT_M1:0] valid;
|
||||
wire[`NW_M1:0] warp_num;
|
||||
|
||||
// source-side view
|
||||
modport snk (
|
||||
input csr_address,
|
||||
input is_csr,
|
||||
input csr_mask,
|
||||
input rd,
|
||||
input rs1,
|
||||
input rs2,
|
||||
input a_reg_data,
|
||||
input b_reg_data,
|
||||
input alu_op,
|
||||
input wb,
|
||||
input rs2_src,
|
||||
input itype_immed,
|
||||
input mem_read,
|
||||
input mem_write,
|
||||
input branch_type,
|
||||
input upper_immed,
|
||||
input curr_PC,
|
||||
input jal,
|
||||
input jal_offset,
|
||||
input PC_next,
|
||||
input valid,
|
||||
input warp_num
|
||||
);
|
||||
|
||||
|
||||
// source-side view
|
||||
modport src (
|
||||
output csr_address,
|
||||
output is_csr,
|
||||
output csr_mask,
|
||||
output rd,
|
||||
output rs1,
|
||||
output rs2,
|
||||
output a_reg_data,
|
||||
output b_reg_data,
|
||||
output alu_op,
|
||||
output wb,
|
||||
output rs2_src,
|
||||
output itype_immed,
|
||||
output mem_read,
|
||||
output mem_write,
|
||||
output branch_type,
|
||||
output upper_immed,
|
||||
output curr_PC,
|
||||
output jal,
|
||||
output jal_offset,
|
||||
output PC_next,
|
||||
output valid,
|
||||
output warp_num
|
||||
);
|
||||
|
||||
|
||||
endinterface
|
||||
|
||||
|
||||
`endif
|
||||
51
rtl/interfaces/VX_inst_mem_wb_inter.v
Normal file
51
rtl/interfaces/VX_inst_mem_wb_inter.v
Normal file
@@ -0,0 +1,51 @@
|
||||
|
||||
`include "VX_define.v"
|
||||
|
||||
`ifndef VX_MEM_WB_INST_INTER
|
||||
|
||||
`define VX_MEM_WB_INST_INTER
|
||||
|
||||
interface VX_inst_mem_wb_inter ();
|
||||
|
||||
wire[`NT_M1:0][31:0] alu_result;
|
||||
wire[`NT_M1:0][31:0] mem_result;
|
||||
wire[4:0] rd;
|
||||
wire[1:0] wb;
|
||||
wire[4:0] rs1;
|
||||
wire[4:0] rs2;
|
||||
wire[31:0] PC_next;
|
||||
wire[`NT_M1:0] valid;
|
||||
wire[`NW_M1:0] warp_num;
|
||||
|
||||
// source-side view
|
||||
modport snk (
|
||||
input alu_result,
|
||||
input mem_result,
|
||||
input rd,
|
||||
input wb,
|
||||
input rs1,
|
||||
input rs2,
|
||||
input PC_next,
|
||||
input valid,
|
||||
input warp_num
|
||||
);
|
||||
|
||||
|
||||
// source-side view
|
||||
modport src (
|
||||
output alu_result,
|
||||
output mem_result,
|
||||
output rd,
|
||||
output wb,
|
||||
output rs1,
|
||||
output rs2,
|
||||
output PC_next,
|
||||
output valid,
|
||||
output warp_num
|
||||
);
|
||||
|
||||
|
||||
endinterface
|
||||
|
||||
|
||||
`endif
|
||||
32
rtl/interfaces/VX_inst_meta_inter.v
Normal file
32
rtl/interfaces/VX_inst_meta_inter.v
Normal file
@@ -0,0 +1,32 @@
|
||||
`include "VX_define.v"
|
||||
|
||||
`ifndef VX_F_D_INTER
|
||||
|
||||
`define VX_F_D_INTER
|
||||
|
||||
interface VX_inst_meta_inter ();
|
||||
wire[31:0] instruction;
|
||||
wire[31:0] inst_pc;
|
||||
wire[`NW_M1:0] warp_num;
|
||||
wire[`NT_M1:0] valid;
|
||||
|
||||
// source-side view
|
||||
modport snk (
|
||||
input instruction,
|
||||
input inst_pc,
|
||||
input warp_num,
|
||||
input valid
|
||||
);
|
||||
|
||||
// sink-side view
|
||||
modport src (
|
||||
output instruction,
|
||||
output inst_pc,
|
||||
output warp_num,
|
||||
output valid
|
||||
);
|
||||
|
||||
endinterface
|
||||
|
||||
|
||||
`endif
|
||||
55
rtl/interfaces/VX_mem_req_inter.v
Normal file
55
rtl/interfaces/VX_mem_req_inter.v
Normal file
@@ -0,0 +1,55 @@
|
||||
interface VX_mem_req_inter ();
|
||||
|
||||
wire[`NT_M1:0][31:0] alu_result;
|
||||
wire[2:0] mem_read;
|
||||
wire[2:0] mem_write;
|
||||
wire[4:0] rd;
|
||||
wire[1:0] wb;
|
||||
wire[4:0] rs1;
|
||||
wire[4:0] rs2;
|
||||
wire[`NT_M1:0][31:0] rd2;
|
||||
wire[31:0] PC_next;
|
||||
wire[31:0] curr_PC;
|
||||
wire[31:0] branch_offset;
|
||||
wire[2:0] branch_type;
|
||||
wire[`NT_M1:0] valid;
|
||||
wire[`NW_M1:0] warp_num;
|
||||
|
||||
|
||||
modport snk (
|
||||
input alu_result,
|
||||
input mem_read,
|
||||
input mem_write,
|
||||
input rd,
|
||||
input wb,
|
||||
input rs1,
|
||||
input rs2,
|
||||
input rd2,
|
||||
input PC_next,
|
||||
input curr_PC,
|
||||
input branch_offset,
|
||||
input branch_type,
|
||||
input valid,
|
||||
input warp_num
|
||||
);
|
||||
|
||||
|
||||
modport src (
|
||||
output alu_result,
|
||||
output mem_read,
|
||||
output mem_write,
|
||||
output rd,
|
||||
output wb,
|
||||
output rs1,
|
||||
output rs2,
|
||||
output rd2,
|
||||
output PC_next,
|
||||
output curr_PC,
|
||||
output branch_offset,
|
||||
output branch_type,
|
||||
output valid,
|
||||
output warp_num
|
||||
);
|
||||
|
||||
|
||||
endinterface
|
||||
42
rtl/interfaces/VX_warp_ctl_inter.v
Normal file
42
rtl/interfaces/VX_warp_ctl_inter.v
Normal file
@@ -0,0 +1,42 @@
|
||||
|
||||
`include "VX_define.v"
|
||||
|
||||
`ifndef VX_WARP_CTL_INTER
|
||||
|
||||
`define VX_WARP_CTL_INTER
|
||||
|
||||
interface VX_warp_ctl_inter ();
|
||||
|
||||
wire[`NW_M1:0] warp_num;
|
||||
wire change_mask;
|
||||
wire[`NT_M1:0] thread_mask;
|
||||
wire wspawn;
|
||||
wire[31:0] wspawn_pc;
|
||||
wire ebreak;
|
||||
|
||||
// source-side view
|
||||
modport snk (
|
||||
input warp_num,
|
||||
input change_mask,
|
||||
input thread_mask,
|
||||
input wspawn,
|
||||
input wspawn_pc,
|
||||
input ebreak
|
||||
);
|
||||
|
||||
|
||||
// source-side view
|
||||
modport src (
|
||||
output warp_num,
|
||||
output change_mask,
|
||||
output thread_mask,
|
||||
output wspawn,
|
||||
output wspawn_pc,
|
||||
output ebreak
|
||||
);
|
||||
|
||||
|
||||
endinterface
|
||||
|
||||
|
||||
`endif
|
||||
38
rtl/interfaces/VX_wb_inter.v
Normal file
38
rtl/interfaces/VX_wb_inter.v
Normal file
@@ -0,0 +1,38 @@
|
||||
|
||||
`ifndef VX_WB_INTER
|
||||
|
||||
`define VX_WB_INTER
|
||||
|
||||
|
||||
interface VX_wb_inter ();
|
||||
|
||||
wire[`NT_M1:0][31:0] write_data;
|
||||
wire[4:0] rd;
|
||||
wire[1:0] wb;
|
||||
wire[`NT_M1:0] wb_valid;
|
||||
wire[`NW_M1:0] wb_warp_num;
|
||||
|
||||
|
||||
|
||||
modport snk (
|
||||
input write_data,
|
||||
input rd,
|
||||
input wb,
|
||||
input wb_valid,
|
||||
input wb_warp_num
|
||||
);
|
||||
|
||||
|
||||
modport src (
|
||||
output write_data,
|
||||
output rd,
|
||||
output wb,
|
||||
output wb_valid,
|
||||
output wb_warp_num
|
||||
);
|
||||
|
||||
endinterface
|
||||
|
||||
|
||||
|
||||
`endif
|
||||
Binary file not shown.
22302
rtl/obj_dir/VVortex.cpp
22302
rtl/obj_dir/VVortex.cpp
File diff suppressed because it is too large
Load Diff
@@ -11,6 +11,12 @@
|
||||
#include "verilated.h"
|
||||
|
||||
class VVortex__Syms;
|
||||
class VVortex_VX_inst_meta_inter;
|
||||
class VVortex_VX_frE_to_bckE_req_inter;
|
||||
class VVortex_VX_mem_req_inter;
|
||||
class VVortex_VX_inst_mem_wb_inter;
|
||||
class VVortex_VX_warp_ctl_inter;
|
||||
class VVortex_VX_wb_inter;
|
||||
class VVortex_VX_context_slave;
|
||||
|
||||
//----------
|
||||
@@ -20,13 +26,22 @@ VL_MODULE(VVortex) {
|
||||
// CELLS
|
||||
// Public to allow access to /*verilator_public*/ items;
|
||||
// otherwise the application code can consider these internals.
|
||||
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_inst_meta_inter* __PVT__Vortex__DOT__fe_inst_meta_fd;
|
||||
VVortex_VX_inst_meta_inter* __PVT__Vortex__DOT__fd_inst_meta_de;
|
||||
VVortex_VX_frE_to_bckE_req_inter* __PVT__Vortex__DOT__VX_frE_to_bckE_req;
|
||||
VVortex_VX_frE_to_bckE_req_inter* __PVT__Vortex__DOT__VX_bckE_req;
|
||||
VVortex_VX_mem_req_inter* __PVT__Vortex__DOT__VX_exe_mem_req;
|
||||
VVortex_VX_mem_req_inter* __PVT__Vortex__DOT__VX_mem_req;
|
||||
VVortex_VX_inst_mem_wb_inter* __PVT__Vortex__DOT__VX_mem_wb;
|
||||
VVortex_VX_warp_ctl_inter* __PVT__Vortex__DOT__VX_warp_ctl;
|
||||
VVortex_VX_wb_inter* __PVT__Vortex__DOT__VX_writeback_inter;
|
||||
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave* __PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one;
|
||||
|
||||
// PORTS
|
||||
// The application code writes and reads these signals to
|
||||
@@ -50,11 +65,7 @@ VL_MODULE(VVortex) {
|
||||
struct {
|
||||
// Begin mtask footprint all:
|
||||
VL_SIG8(Vortex__DOT__decode_branch_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__decode_branch_type,2,0);
|
||||
VL_SIG8(Vortex__DOT__decode_jal,0,0);
|
||||
VL_SIG8(Vortex__DOT__decode_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__memory_branch_dir,0,0);
|
||||
VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__forwarding_src1_fwd,0,0);
|
||||
VL_SIG8(Vortex__DOT__forwarding_src2_fwd,0,0);
|
||||
@@ -64,23 +75,22 @@ VL_MODULE(VVortex) {
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_count,3,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__add_warp,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__remove_warp,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__warp_num,3,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__0__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__0__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__1__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__1__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__2__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__2__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__3__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__3__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__5__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__5__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__6__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__6__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__warp_zero_change_mask,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__warp_zero_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_clone,0,0);
|
||||
@@ -89,346 +99,160 @@ VL_MODULE(VVortex) {
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__jal_sys_jal,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__glob_clone_stall,7,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__real_zero_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__temp_out_clone_stall,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__jalrs_thread_mask,3,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__jmprt_thread_mask,3,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_ebreak,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__temp_final_alu,4,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__real_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__real_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__real_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__real_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__real_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__real_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__real_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__real_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__real_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__real_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__real_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__real_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__real_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__real_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__real_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__real_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__real_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__real_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__real_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__real_wspawn,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__real_isclone,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall,5,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rd,4,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__alu_op,4,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__wb,1,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rs2_src,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__mem_read,2,0);
|
||||
};
|
||||
struct {
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__mem_write,2,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__branch_type,2,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__is_csr,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__jal,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__warp_num,3,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__stalling,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__rd,4,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__wb,1,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__mem_read,2,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__mem_write,2,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__is_csr,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__branch_type,2,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__jal,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__warp_num,3,0);
|
||||
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__rd,4,0);
|
||||
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__wb,1,0);
|
||||
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__warp_num,3,0);
|
||||
VL_SIG8(Vortex__DOT__vx_memory__DOT__temp_branch_dir,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd,0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd,0,0);
|
||||
VL_SIG16(Vortex__DOT__decode_csr_address,11,0);
|
||||
};
|
||||
struct {
|
||||
VL_SIG16(Vortex__DOT__vx_decode__DOT__alu_tempp,11,0);
|
||||
VL_SIG16(Vortex__DOT__vx_d_e_reg__DOT__csr_address,11,0);
|
||||
VL_SIG16(Vortex__DOT__vx_e_m_reg__DOT__csr_address,11,0);
|
||||
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__decode_csr_address,11,0);
|
||||
VL_SIG(Vortex__DOT__decode_itype_immed,31,0);
|
||||
VL_SIG(Vortex__DOT__decode_jal_offset,31,0);
|
||||
VL_SIG(Vortex__DOT__memory_branch_dest,31,0);
|
||||
VL_SIG(Vortex__DOT__csr_decode_csr_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__out_PC_var,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__0__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__0__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__1__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__1__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__2__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__2__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__3__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__3__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__5__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__5__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__6__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__6__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__VX_Warp__DOT__real_PC,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__VX_Warp__DOT__temp_PC,31,0);
|
||||
VL_SIGW(Vortex__DOT__vx_f_d_reg__DOT__f_d_reg__DOT__value,71,0,3);
|
||||
VL_SIGW(Vortex__DOT__vx_decode__DOT__glob_a_reg_data,1023,0,32);
|
||||
VL_SIGW(Vortex__DOT__vx_decode__DOT__glob_b_reg_data,1023,0,32);
|
||||
VL_SIGW(Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers,1023,0,32);
|
||||
VL_SIGW(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
|
||||
VL_SIGW(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
|
||||
VL_SIGW(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
|
||||
VL_SIGW(Vortex__DOT__vx_d_e_reg__DOT__d_e_reg__DOT__value,489,0,16);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__ALU_in2,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0);
|
||||
};
|
||||
struct {
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0);
|
||||
VL_SIGW(Vortex__DOT__vx_e_m_reg__DOT__f_d_reg__DOT__value,719,0,23);
|
||||
VL_SIGW(Vortex__DOT__vx_m_w_reg__DOT__m_w_reg__DOT__value,312,0,10);
|
||||
VL_SIGW(Vortex__DOT__vx_writeback__DOT__out_pc_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next,127,0,4);
|
||||
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__0__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
|
||||
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__1__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
|
||||
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__2__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
|
||||
VL_SIG64(Vortex__DOT__vx_execute__DOT__genblk1__BRA__3__KET____DOT__vx_alu__DOT__mult_signed_result,63,0);
|
||||
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
|
||||
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
|
||||
VL_SIG8(Vortex__DOT__fetch_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__f_d_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__decode_a_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__decode_b_reg_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__decode_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__decode_thread_mask[4],0,0);
|
||||
VL_SIG(Vortex__DOT__d_e_a_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__d_e_b_reg_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__d_e_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__execute_alu_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT__execute_b_reg_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__execute_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__e_m_alu_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT__e_m_b_reg_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__e_m_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__memory_alu_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT__memory_mem_result[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__memory_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__m_w_alu_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT__m_w_mem_result[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__m_w_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__writeback_write_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__in_thread_mask[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_fetch__DOT__warp_glob_pc[8],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_glob_valid[8][4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__out_valid_var[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk1__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__w0_t0_registers[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__glob_a_reg_data[8][4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__glob_b_reg_data[8][4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__glob_clone_stall[8],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__temp_out_a_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__temp_out_b_reg_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[32],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__0__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__0__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__1__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__1__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__2__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__2__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__3__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__3__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__4__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__5__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
};
|
||||
struct {
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__5__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__6__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__6__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__VX_Warp__DOT__valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT__genblk2__BRA__7__KET____DOT__VX_Warp__DOT__valid_zero[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT__in_valid[4],0,0);
|
||||
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[1025],11,0);
|
||||
};
|
||||
|
||||
// LOCAL VARIABLES
|
||||
// Internals; generally not touched by application code
|
||||
// Anonymous structures to workaround compiler member-count bugs
|
||||
struct {
|
||||
// Begin mtask footprint all:
|
||||
VL_SIG8(__Vtableidx1,2,0);
|
||||
VL_SIG8(__Vclklast__TOP__clk,0,0);
|
||||
VL_SIG8(__Vclklast__TOP__reset,0,0);
|
||||
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT____Vlvbound1,11,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_fetch__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[4],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[4],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[4],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[4],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[4],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[4],31,0);
|
||||
VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[4],31,0);
|
||||
};
|
||||
struct {
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__0__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__0__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__1__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_write_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__1__KET____DOT__VX_Context_one__in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__2__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_write_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__2__KET____DOT__VX_Context_one__in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__3__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_write_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__3__KET____DOT__VX_Context_one__in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__4__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_write_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__4__KET____DOT__VX_Context_one__in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__5__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_write_data[4],31,0);
|
||||
};
|
||||
struct {
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__5__KET____DOT__VX_Context_one__in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__6__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_write_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__6__KET____DOT__VX_Context_one__in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_b_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__genblk1__BRA__7__KET____DOT__VX_Context_one__out_a_reg_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_wspawn_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_write_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src2_fwd_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_src1_fwd_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__genblk1__BRA__7__KET____DOT__VX_Context_one__in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
|
||||
};
|
||||
// Begin mtask footprint all:
|
||||
VL_SIG8(__Vtableidx1,2,0);
|
||||
VL_SIG8(__Vdly__Vortex__DOT__vx_fetch__DOT__warp_num,3,0);
|
||||
VL_SIG8(__Vclklast__TOP__clk,0,0);
|
||||
VL_SIG8(__Vclklast__TOP__reset,0,0);
|
||||
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT____Vlvbound1,11,0);
|
||||
VL_SIGW(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT____Vcellout__vx_execute__out_a_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data,127,0,4);
|
||||
VL_SIGW(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data,127,0,4);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||
VL_SIGW(Vortex__DOT__vx_d_e_reg__DOT____Vcellinp__d_e_reg__in,489,0,16);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__2__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__3__KET____DOT__vx_alu__out_alu_result,31,0);
|
||||
VL_SIGW(Vortex__DOT__vx_e_m_reg__DOT____Vcellinp__f_d_reg__in,719,0,23);
|
||||
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[4],0,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[4],31,0);
|
||||
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[4],31,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__0__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__0__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__1__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__1__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__2__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__2__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__3__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__3__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__4__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__4__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__5__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__5__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__6__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__6__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__genblk2__BRA__7__KET____DOT__VX_Warp__out_valid[4],0,0);
|
||||
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__genblk2__BRA__7__KET____DOT__VX_Warp__in_thread_mask[4],0,0);
|
||||
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
|
||||
|
||||
// INTERNAL VARIABLES
|
||||
@@ -464,9 +288,10 @@ VL_MODULE(VVortex) {
|
||||
static QData _change_request(VVortex__Syms* __restrict vlSymsp);
|
||||
public:
|
||||
static void _combo__TOP__10(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _combo__TOP__8(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _combo__TOP__11(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _combo__TOP__7(VVortex__Syms* __restrict vlSymsp);
|
||||
private:
|
||||
void _ctor_var_reset();
|
||||
void _ctor_var_reset() VL_ATTR_COLD;
|
||||
public:
|
||||
static void _eval(VVortex__Syms* __restrict vlSymsp);
|
||||
private:
|
||||
@@ -474,16 +299,16 @@ VL_MODULE(VVortex) {
|
||||
void _eval_debug_assertions();
|
||||
#endif // VL_DEBUG
|
||||
public:
|
||||
static void _eval_initial(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _eval_settle(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _initial__TOP__1(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _eval_initial(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
|
||||
static void _eval_settle(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
|
||||
static void _initial__TOP__1(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
|
||||
static void _sequent__TOP__4(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _sequent__TOP__6(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _sequent__TOP__8(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _sequent__TOP__9(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _settle__TOP__2(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _settle__TOP__3(VVortex__Syms* __restrict vlSymsp);
|
||||
static void _settle__TOP__2(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
|
||||
static void _settle__TOP__3(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
|
||||
} VL_ATTR_ALIGNED(128);
|
||||
|
||||
#endif // guard
|
||||
|
||||
@@ -10,7 +10,7 @@ default: VVortex
|
||||
# Perl executable (from $PERL)
|
||||
PERL = perl
|
||||
# Path to Verilator kit (from $VERILATOR_ROOT)
|
||||
VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator
|
||||
VERILATOR_ROOT = /usr/local/share/verilator
|
||||
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
|
||||
SYSTEMC_INCLUDE ?=
|
||||
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -19,6 +19,7 @@ VL_MODULE(VVortex_VX_context_slave) {
|
||||
VL_IN8(clk,0,0);
|
||||
VL_IN8(in_warp,0,0);
|
||||
VL_IN8(in_wb_warp,0,0);
|
||||
VL_IN8(in_valid,3,0);
|
||||
VL_IN8(in_write_register,0,0);
|
||||
VL_IN8(in_rd,4,0);
|
||||
VL_IN8(in_src1,4,0);
|
||||
@@ -29,195 +30,37 @@ VL_MODULE(VVortex_VX_context_slave) {
|
||||
VL_IN8(in_src2_fwd,0,0);
|
||||
VL_IN8(in_wspawn,0,0);
|
||||
VL_OUT8(out_clone_stall,0,0);
|
||||
VL_INW(in_write_data,127,0,4);
|
||||
VL_IN(in_curr_PC,31,0);
|
||||
VL_IN8(in_valid[4],0,0);
|
||||
VL_IN(in_write_data[4],31,0);
|
||||
VL_IN(in_src1_fwd_data[4],31,0);
|
||||
VL_IN(in_src2_fwd_data[4],31,0);
|
||||
VL_IN(in_wspawn_regs[32],31,0);
|
||||
VL_OUT(out_a_reg_data[4],31,0);
|
||||
VL_OUT(out_b_reg_data[4],31,0);
|
||||
VL_INW(in_src1_fwd_data,127,0,4);
|
||||
VL_INW(in_src2_fwd_data,127,0,4);
|
||||
VL_INW(in_wspawn_regs,1023,0,32);
|
||||
VL_OUTW(out_a_reg_data,127,0,4);
|
||||
VL_OUTW(out_b_reg_data,127,0,4);
|
||||
|
||||
// LOCAL SIGNALS
|
||||
// Begin mtask footprint all:
|
||||
VL_SIG8(__PVT__clone_state_stall,5,0);
|
||||
VL_SIG8(__PVT__wspawn_state_stall,5,0);
|
||||
VL_SIG(__PVT__rd1_register[4],31,0);
|
||||
VL_SIG(__PVT__rd2_register[4],31,0);
|
||||
VL_SIG(__PVT__clone_regsiters[32],31,0);
|
||||
VL_SIG(__PVT__vx_register_file_master__DOT__registers[32],31,0);
|
||||
VL_SIG(__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
|
||||
VL_SIG(__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
|
||||
VL_SIG(__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
|
||||
VL_SIGW(__PVT__rd1_register,127,0,4);
|
||||
VL_SIGW(__PVT__rd2_register,127,0,4);
|
||||
VL_SIGW(__PVT__vx_register_file_master__DOT__registers,1023,0,32);
|
||||
VL_SIGW(__PVT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
|
||||
VL_SIGW(__PVT__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
|
||||
VL_SIGW(__PVT__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers,1023,0,32);
|
||||
|
||||
// LOCAL VARIABLES
|
||||
// Anonymous structures to workaround compiler member-count bugs
|
||||
struct {
|
||||
// Begin mtask footprint all:
|
||||
VL_SIG8(__Vdly__clone_state_stall,5,0);
|
||||
VL_SIG8(__Vdly__wspawn_state_stall,5,0);
|
||||
VL_SIG8(__Vdlyvdim0__vx_register_file_master__DOT__registers__v0,4,0);
|
||||
VL_SIG8(__Vdlyvset__vx_register_file_master__DOT__registers__v0,0,0);
|
||||
VL_SIG8(__Vdlyvset__vx_register_file_master__DOT__registers__v1,0,0);
|
||||
VL_SIG8(__Vdlyvdim0__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0);
|
||||
VL_SIG8(__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0);
|
||||
VL_SIG8(__Vdlyvset__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0);
|
||||
VL_SIG8(__Vdlyvdim0__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0);
|
||||
VL_SIG8(__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0);
|
||||
VL_SIG8(__Vdlyvset__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0);
|
||||
VL_SIG8(__Vdlyvdim0__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0,4,0);
|
||||
VL_SIG8(__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0,0,0);
|
||||
VL_SIG8(__Vdlyvset__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1,0,0);
|
||||
VL_SIG(__Vcellout__vx_register_file_master__out_src2_data,31,0);
|
||||
VL_SIG(__Vcellout__vx_register_file_master__out_src1_data,31,0);
|
||||
VL_SIG(__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||
VL_SIG(__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||
VL_SIG(__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||
VL_SIG(__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||
VL_SIG(__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||
VL_SIG(__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v0,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v1,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v2,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v3,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v4,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v5,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v6,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v7,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v8,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v9,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v10,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v11,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v12,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v13,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v14,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v15,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v16,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v17,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v18,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v19,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v20,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v21,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v22,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v23,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v24,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v25,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v26,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v27,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v28,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v29,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v30,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v31,31,0);
|
||||
VL_SIG(__Vdlyvval__vx_register_file_master__DOT__registers__v32,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v0,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v1,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v2,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v3,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v4,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v5,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v6,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v7,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v8,31,0);
|
||||
};
|
||||
struct {
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v9,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v10,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v11,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v12,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v13,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v14,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v15,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v16,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v17,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v18,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v19,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v20,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v21,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v22,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v23,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v24,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v25,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v26,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v27,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v28,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v29,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v30,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v31,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers__v32,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v0,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v1,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v2,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v3,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v4,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v5,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v6,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v7,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v8,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v9,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v10,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v11,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v12,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v13,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v14,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v15,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v16,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v17,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v18,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v19,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v20,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v21,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v22,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v23,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v24,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v25,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v26,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v27,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v28,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v29,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v30,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v31,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__DOT__registers__v32,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v0,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v1,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v2,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v3,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v4,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v5,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v6,31,0);
|
||||
};
|
||||
struct {
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v7,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v8,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v9,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v10,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v11,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v12,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v13,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v14,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v15,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v16,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v17,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v18,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v19,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v20,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v21,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v22,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v23,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v24,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v25,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v26,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v27,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v28,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v29,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v30,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v31,31,0);
|
||||
VL_SIG(__Vdlyvval__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__DOT__registers__v32,31,0);
|
||||
VL_SIG(__Vcellout__vx_register_file_master__out_regs[32],31,0);
|
||||
VL_SIG(__Vcellinp__vx_register_file_master__in_wspawn_regs[32],31,0);
|
||||
VL_SIG(__Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
|
||||
VL_SIG(__Vcellinp__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
|
||||
VL_SIG(__Vcellinp__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
|
||||
};
|
||||
// Begin mtask footprint all:
|
||||
VL_SIG8(__Vdly__clone_state_stall,5,0);
|
||||
VL_SIG8(__Vdly__wspawn_state_stall,5,0);
|
||||
VL_SIG(__Vcellout__vx_register_file_master__out_src2_data,31,0);
|
||||
VL_SIG(__Vcellout__vx_register_file_master__out_src1_data,31,0);
|
||||
VL_SIG(__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||
VL_SIG(__Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||
VL_SIG(__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||
VL_SIG(__Vcellout__gen_code_label__BRA__2__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||
VL_SIG(__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
|
||||
VL_SIG(__Vcellout__gen_code_label__BRA__3__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
|
||||
|
||||
// INTERNAL VARIABLES
|
||||
private:
|
||||
@@ -237,21 +80,20 @@ VL_MODULE(VVortex_VX_context_slave) {
|
||||
|
||||
// INTERNAL METHODS
|
||||
void __Vconfigure(VVortex__Syms* symsp, bool first);
|
||||
void _combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__29(VVortex__Syms* __restrict vlSymsp);
|
||||
void _combo__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__36(VVortex__Syms* __restrict vlSymsp);
|
||||
void _combo__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__29(VVortex__Syms* __restrict vlSymsp);
|
||||
private:
|
||||
void _ctor_var_reset();
|
||||
void _ctor_var_reset() VL_ATTR_COLD;
|
||||
public:
|
||||
void _initial__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__1(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__15(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__22(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one__16(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one__17(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one__18(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one__19(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one__20(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one__21(VVortex__Syms* __restrict vlSymsp);
|
||||
void _settle__TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one__8(VVortex__Syms* __restrict vlSymsp);
|
||||
void _initial__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__1(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__15(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__22(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one__16(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one__17(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one__18(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one__19(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one__20(VVortex__Syms* __restrict vlSymsp);
|
||||
void _sequent__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one__21(VVortex__Syms* __restrict vlSymsp);
|
||||
void _settle__TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one__8(VVortex__Syms* __restrict vlSymsp) VL_ATTR_COLD;
|
||||
} VL_ATTR_ALIGNED(128);
|
||||
|
||||
#endif // guard
|
||||
|
||||
42
rtl/obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp
Normal file
42
rtl/obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp
Normal file
@@ -0,0 +1,42 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design implementation internals
|
||||
// See VVortex.h for the primary calling header
|
||||
|
||||
#include "VVortex_VX_frE_to_bckE_req_inter.h"
|
||||
#include "VVortex__Syms.h"
|
||||
|
||||
|
||||
//--------------------
|
||||
// STATIC VARIABLES
|
||||
|
||||
|
||||
//--------------------
|
||||
|
||||
VL_CTOR_IMP(VVortex_VX_frE_to_bckE_req_inter) {
|
||||
// Reset internal values
|
||||
// Reset structure values
|
||||
_ctor_var_reset();
|
||||
}
|
||||
|
||||
void VVortex_VX_frE_to_bckE_req_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
|
||||
if (0 && first) {} // Prevent unused
|
||||
this->__VlSymsp = vlSymsp;
|
||||
}
|
||||
|
||||
VVortex_VX_frE_to_bckE_req_inter::~VVortex_VX_frE_to_bckE_req_inter() {
|
||||
}
|
||||
|
||||
//--------------------
|
||||
// Internal Methods
|
||||
|
||||
void VVortex_VX_frE_to_bckE_req_inter::_ctor_var_reset() {
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_frE_to_bckE_req_inter::_ctor_var_reset\n"); );
|
||||
// Body
|
||||
csr_address = VL_RAND_RESET_I(12);
|
||||
VL_RAND_RESET_W(128,a_reg_data);
|
||||
VL_RAND_RESET_W(128,b_reg_data);
|
||||
itype_immed = VL_RAND_RESET_I(32);
|
||||
branch_type = VL_RAND_RESET_I(3);
|
||||
jal = VL_RAND_RESET_I(1);
|
||||
jal_offset = VL_RAND_RESET_I(32);
|
||||
}
|
||||
53
rtl/obj_dir/VVortex_VX_frE_to_bckE_req_inter.h
Normal file
53
rtl/obj_dir/VVortex_VX_frE_to_bckE_req_inter.h
Normal file
@@ -0,0 +1,53 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design internal header
|
||||
// See VVortex.h for the primary calling header
|
||||
|
||||
#ifndef _VVortex_VX_frE_to_bckE_req_inter_H_
|
||||
#define _VVortex_VX_frE_to_bckE_req_inter_H_
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
class VVortex__Syms;
|
||||
|
||||
//----------
|
||||
|
||||
VL_MODULE(VVortex_VX_frE_to_bckE_req_inter) {
|
||||
public:
|
||||
|
||||
// PORTS
|
||||
|
||||
// LOCAL SIGNALS
|
||||
// Begin mtask footprint all:
|
||||
VL_SIG8(branch_type,2,0);
|
||||
VL_SIG8(jal,0,0);
|
||||
VL_SIG16(csr_address,11,0);
|
||||
VL_SIGW(a_reg_data,127,0,4);
|
||||
VL_SIGW(b_reg_data,127,0,4);
|
||||
VL_SIG(itype_immed,31,0);
|
||||
VL_SIG(jal_offset,31,0);
|
||||
|
||||
// LOCAL VARIABLES
|
||||
|
||||
// INTERNAL VARIABLES
|
||||
private:
|
||||
VVortex__Syms* __VlSymsp; // Symbol table
|
||||
public:
|
||||
|
||||
// PARAMETERS
|
||||
|
||||
// CONSTRUCTORS
|
||||
private:
|
||||
VL_UNCOPYABLE(VVortex_VX_frE_to_bckE_req_inter); ///< Copying not allowed
|
||||
public:
|
||||
VVortex_VX_frE_to_bckE_req_inter(const char* name="TOP");
|
||||
~VVortex_VX_frE_to_bckE_req_inter();
|
||||
|
||||
// API METHODS
|
||||
|
||||
// INTERNAL METHODS
|
||||
void __Vconfigure(VVortex__Syms* symsp, bool first);
|
||||
private:
|
||||
void _ctor_var_reset() VL_ATTR_COLD;
|
||||
} VL_ATTR_ALIGNED(128);
|
||||
|
||||
#endif // guard
|
||||
36
rtl/obj_dir/VVortex_VX_inst_mem_wb_inter.cpp
Normal file
36
rtl/obj_dir/VVortex_VX_inst_mem_wb_inter.cpp
Normal file
@@ -0,0 +1,36 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design implementation internals
|
||||
// See VVortex.h for the primary calling header
|
||||
|
||||
#include "VVortex_VX_inst_mem_wb_inter.h"
|
||||
#include "VVortex__Syms.h"
|
||||
|
||||
|
||||
//--------------------
|
||||
// STATIC VARIABLES
|
||||
|
||||
|
||||
//--------------------
|
||||
|
||||
VL_CTOR_IMP(VVortex_VX_inst_mem_wb_inter) {
|
||||
// Reset internal values
|
||||
// Reset structure values
|
||||
_ctor_var_reset();
|
||||
}
|
||||
|
||||
void VVortex_VX_inst_mem_wb_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
|
||||
if (0 && first) {} // Prevent unused
|
||||
this->__VlSymsp = vlSymsp;
|
||||
}
|
||||
|
||||
VVortex_VX_inst_mem_wb_inter::~VVortex_VX_inst_mem_wb_inter() {
|
||||
}
|
||||
|
||||
//--------------------
|
||||
// Internal Methods
|
||||
|
||||
void VVortex_VX_inst_mem_wb_inter::_ctor_var_reset() {
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_inst_mem_wb_inter::_ctor_var_reset\n"); );
|
||||
// Body
|
||||
VL_RAND_RESET_W(128,mem_result);
|
||||
}
|
||||
47
rtl/obj_dir/VVortex_VX_inst_mem_wb_inter.h
Normal file
47
rtl/obj_dir/VVortex_VX_inst_mem_wb_inter.h
Normal file
@@ -0,0 +1,47 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design internal header
|
||||
// See VVortex.h for the primary calling header
|
||||
|
||||
#ifndef _VVortex_VX_inst_mem_wb_inter_H_
|
||||
#define _VVortex_VX_inst_mem_wb_inter_H_
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
class VVortex__Syms;
|
||||
|
||||
//----------
|
||||
|
||||
VL_MODULE(VVortex_VX_inst_mem_wb_inter) {
|
||||
public:
|
||||
|
||||
// PORTS
|
||||
|
||||
// LOCAL SIGNALS
|
||||
// Begin mtask footprint all:
|
||||
VL_SIGW(mem_result,127,0,4);
|
||||
|
||||
// LOCAL VARIABLES
|
||||
|
||||
// INTERNAL VARIABLES
|
||||
private:
|
||||
VVortex__Syms* __VlSymsp; // Symbol table
|
||||
public:
|
||||
|
||||
// PARAMETERS
|
||||
|
||||
// CONSTRUCTORS
|
||||
private:
|
||||
VL_UNCOPYABLE(VVortex_VX_inst_mem_wb_inter); ///< Copying not allowed
|
||||
public:
|
||||
VVortex_VX_inst_mem_wb_inter(const char* name="TOP");
|
||||
~VVortex_VX_inst_mem_wb_inter();
|
||||
|
||||
// API METHODS
|
||||
|
||||
// INTERNAL METHODS
|
||||
void __Vconfigure(VVortex__Syms* symsp, bool first);
|
||||
private:
|
||||
void _ctor_var_reset() VL_ATTR_COLD;
|
||||
} VL_ATTR_ALIGNED(128);
|
||||
|
||||
#endif // guard
|
||||
36
rtl/obj_dir/VVortex_VX_inst_meta_inter.cpp
Normal file
36
rtl/obj_dir/VVortex_VX_inst_meta_inter.cpp
Normal file
@@ -0,0 +1,36 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design implementation internals
|
||||
// See VVortex.h for the primary calling header
|
||||
|
||||
#include "VVortex_VX_inst_meta_inter.h"
|
||||
#include "VVortex__Syms.h"
|
||||
|
||||
|
||||
//--------------------
|
||||
// STATIC VARIABLES
|
||||
|
||||
|
||||
//--------------------
|
||||
|
||||
VL_CTOR_IMP(VVortex_VX_inst_meta_inter) {
|
||||
// Reset internal values
|
||||
// Reset structure values
|
||||
_ctor_var_reset();
|
||||
}
|
||||
|
||||
void VVortex_VX_inst_meta_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
|
||||
if (0 && first) {} // Prevent unused
|
||||
this->__VlSymsp = vlSymsp;
|
||||
}
|
||||
|
||||
VVortex_VX_inst_meta_inter::~VVortex_VX_inst_meta_inter() {
|
||||
}
|
||||
|
||||
//--------------------
|
||||
// Internal Methods
|
||||
|
||||
void VVortex_VX_inst_meta_inter::_ctor_var_reset() {
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_inst_meta_inter::_ctor_var_reset\n"); );
|
||||
// Body
|
||||
valid = VL_RAND_RESET_I(4);
|
||||
}
|
||||
47
rtl/obj_dir/VVortex_VX_inst_meta_inter.h
Normal file
47
rtl/obj_dir/VVortex_VX_inst_meta_inter.h
Normal file
@@ -0,0 +1,47 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design internal header
|
||||
// See VVortex.h for the primary calling header
|
||||
|
||||
#ifndef _VVortex_VX_inst_meta_inter_H_
|
||||
#define _VVortex_VX_inst_meta_inter_H_
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
class VVortex__Syms;
|
||||
|
||||
//----------
|
||||
|
||||
VL_MODULE(VVortex_VX_inst_meta_inter) {
|
||||
public:
|
||||
|
||||
// PORTS
|
||||
|
||||
// LOCAL SIGNALS
|
||||
// Begin mtask footprint all:
|
||||
VL_SIG8(valid,3,0);
|
||||
|
||||
// LOCAL VARIABLES
|
||||
|
||||
// INTERNAL VARIABLES
|
||||
private:
|
||||
VVortex__Syms* __VlSymsp; // Symbol table
|
||||
public:
|
||||
|
||||
// PARAMETERS
|
||||
|
||||
// CONSTRUCTORS
|
||||
private:
|
||||
VL_UNCOPYABLE(VVortex_VX_inst_meta_inter); ///< Copying not allowed
|
||||
public:
|
||||
VVortex_VX_inst_meta_inter(const char* name="TOP");
|
||||
~VVortex_VX_inst_meta_inter();
|
||||
|
||||
// API METHODS
|
||||
|
||||
// INTERNAL METHODS
|
||||
void __Vconfigure(VVortex__Syms* symsp, bool first);
|
||||
private:
|
||||
void _ctor_var_reset() VL_ATTR_COLD;
|
||||
} VL_ATTR_ALIGNED(128);
|
||||
|
||||
#endif // guard
|
||||
37
rtl/obj_dir/VVortex_VX_mem_req_inter.cpp
Normal file
37
rtl/obj_dir/VVortex_VX_mem_req_inter.cpp
Normal file
@@ -0,0 +1,37 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design implementation internals
|
||||
// See VVortex.h for the primary calling header
|
||||
|
||||
#include "VVortex_VX_mem_req_inter.h"
|
||||
#include "VVortex__Syms.h"
|
||||
|
||||
|
||||
//--------------------
|
||||
// STATIC VARIABLES
|
||||
|
||||
|
||||
//--------------------
|
||||
|
||||
VL_CTOR_IMP(VVortex_VX_mem_req_inter) {
|
||||
// Reset internal values
|
||||
// Reset structure values
|
||||
_ctor_var_reset();
|
||||
}
|
||||
|
||||
void VVortex_VX_mem_req_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
|
||||
if (0 && first) {} // Prevent unused
|
||||
this->__VlSymsp = vlSymsp;
|
||||
}
|
||||
|
||||
VVortex_VX_mem_req_inter::~VVortex_VX_mem_req_inter() {
|
||||
}
|
||||
|
||||
//--------------------
|
||||
// Internal Methods
|
||||
|
||||
void VVortex_VX_mem_req_inter::_ctor_var_reset() {
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_mem_req_inter::_ctor_var_reset\n"); );
|
||||
// Body
|
||||
VL_RAND_RESET_W(128,alu_result);
|
||||
wb = VL_RAND_RESET_I(2);
|
||||
}
|
||||
48
rtl/obj_dir/VVortex_VX_mem_req_inter.h
Normal file
48
rtl/obj_dir/VVortex_VX_mem_req_inter.h
Normal file
@@ -0,0 +1,48 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design internal header
|
||||
// See VVortex.h for the primary calling header
|
||||
|
||||
#ifndef _VVortex_VX_mem_req_inter_H_
|
||||
#define _VVortex_VX_mem_req_inter_H_
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
class VVortex__Syms;
|
||||
|
||||
//----------
|
||||
|
||||
VL_MODULE(VVortex_VX_mem_req_inter) {
|
||||
public:
|
||||
|
||||
// PORTS
|
||||
|
||||
// LOCAL SIGNALS
|
||||
// Begin mtask footprint all:
|
||||
VL_SIG8(wb,1,0);
|
||||
VL_SIGW(alu_result,127,0,4);
|
||||
|
||||
// LOCAL VARIABLES
|
||||
|
||||
// INTERNAL VARIABLES
|
||||
private:
|
||||
VVortex__Syms* __VlSymsp; // Symbol table
|
||||
public:
|
||||
|
||||
// PARAMETERS
|
||||
|
||||
// CONSTRUCTORS
|
||||
private:
|
||||
VL_UNCOPYABLE(VVortex_VX_mem_req_inter); ///< Copying not allowed
|
||||
public:
|
||||
VVortex_VX_mem_req_inter(const char* name="TOP");
|
||||
~VVortex_VX_mem_req_inter();
|
||||
|
||||
// API METHODS
|
||||
|
||||
// INTERNAL METHODS
|
||||
void __Vconfigure(VVortex__Syms* symsp, bool first);
|
||||
private:
|
||||
void _ctor_var_reset() VL_ATTR_COLD;
|
||||
} VL_ATTR_ALIGNED(128);
|
||||
|
||||
#endif // guard
|
||||
37
rtl/obj_dir/VVortex_VX_warp_ctl_inter.cpp
Normal file
37
rtl/obj_dir/VVortex_VX_warp_ctl_inter.cpp
Normal file
@@ -0,0 +1,37 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design implementation internals
|
||||
// See VVortex.h for the primary calling header
|
||||
|
||||
#include "VVortex_VX_warp_ctl_inter.h"
|
||||
#include "VVortex__Syms.h"
|
||||
|
||||
|
||||
//--------------------
|
||||
// STATIC VARIABLES
|
||||
|
||||
|
||||
//--------------------
|
||||
|
||||
VL_CTOR_IMP(VVortex_VX_warp_ctl_inter) {
|
||||
// Reset internal values
|
||||
// Reset structure values
|
||||
_ctor_var_reset();
|
||||
}
|
||||
|
||||
void VVortex_VX_warp_ctl_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
|
||||
if (0 && first) {} // Prevent unused
|
||||
this->__VlSymsp = vlSymsp;
|
||||
}
|
||||
|
||||
VVortex_VX_warp_ctl_inter::~VVortex_VX_warp_ctl_inter() {
|
||||
}
|
||||
|
||||
//--------------------
|
||||
// Internal Methods
|
||||
|
||||
void VVortex_VX_warp_ctl_inter::_ctor_var_reset() {
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_warp_ctl_inter::_ctor_var_reset\n"); );
|
||||
// Body
|
||||
change_mask = VL_RAND_RESET_I(1);
|
||||
thread_mask = VL_RAND_RESET_I(4);
|
||||
}
|
||||
48
rtl/obj_dir/VVortex_VX_warp_ctl_inter.h
Normal file
48
rtl/obj_dir/VVortex_VX_warp_ctl_inter.h
Normal file
@@ -0,0 +1,48 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design internal header
|
||||
// See VVortex.h for the primary calling header
|
||||
|
||||
#ifndef _VVortex_VX_warp_ctl_inter_H_
|
||||
#define _VVortex_VX_warp_ctl_inter_H_
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
class VVortex__Syms;
|
||||
|
||||
//----------
|
||||
|
||||
VL_MODULE(VVortex_VX_warp_ctl_inter) {
|
||||
public:
|
||||
|
||||
// PORTS
|
||||
|
||||
// LOCAL SIGNALS
|
||||
// Begin mtask footprint all:
|
||||
VL_SIG8(change_mask,0,0);
|
||||
VL_SIG8(thread_mask,3,0);
|
||||
|
||||
// LOCAL VARIABLES
|
||||
|
||||
// INTERNAL VARIABLES
|
||||
private:
|
||||
VVortex__Syms* __VlSymsp; // Symbol table
|
||||
public:
|
||||
|
||||
// PARAMETERS
|
||||
|
||||
// CONSTRUCTORS
|
||||
private:
|
||||
VL_UNCOPYABLE(VVortex_VX_warp_ctl_inter); ///< Copying not allowed
|
||||
public:
|
||||
VVortex_VX_warp_ctl_inter(const char* name="TOP");
|
||||
~VVortex_VX_warp_ctl_inter();
|
||||
|
||||
// API METHODS
|
||||
|
||||
// INTERNAL METHODS
|
||||
void __Vconfigure(VVortex__Syms* symsp, bool first);
|
||||
private:
|
||||
void _ctor_var_reset() VL_ATTR_COLD;
|
||||
} VL_ATTR_ALIGNED(128);
|
||||
|
||||
#endif // guard
|
||||
36
rtl/obj_dir/VVortex_VX_wb_inter.cpp
Normal file
36
rtl/obj_dir/VVortex_VX_wb_inter.cpp
Normal file
@@ -0,0 +1,36 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design implementation internals
|
||||
// See VVortex.h for the primary calling header
|
||||
|
||||
#include "VVortex_VX_wb_inter.h"
|
||||
#include "VVortex__Syms.h"
|
||||
|
||||
|
||||
//--------------------
|
||||
// STATIC VARIABLES
|
||||
|
||||
|
||||
//--------------------
|
||||
|
||||
VL_CTOR_IMP(VVortex_VX_wb_inter) {
|
||||
// Reset internal values
|
||||
// Reset structure values
|
||||
_ctor_var_reset();
|
||||
}
|
||||
|
||||
void VVortex_VX_wb_inter::__Vconfigure(VVortex__Syms* vlSymsp, bool first) {
|
||||
if (0 && first) {} // Prevent unused
|
||||
this->__VlSymsp = vlSymsp;
|
||||
}
|
||||
|
||||
VVortex_VX_wb_inter::~VVortex_VX_wb_inter() {
|
||||
}
|
||||
|
||||
//--------------------
|
||||
// Internal Methods
|
||||
|
||||
void VVortex_VX_wb_inter::_ctor_var_reset() {
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex_VX_wb_inter::_ctor_var_reset\n"); );
|
||||
// Body
|
||||
VL_RAND_RESET_W(128,write_data);
|
||||
}
|
||||
47
rtl/obj_dir/VVortex_VX_wb_inter.h
Normal file
47
rtl/obj_dir/VVortex_VX_wb_inter.h
Normal file
@@ -0,0 +1,47 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design internal header
|
||||
// See VVortex.h for the primary calling header
|
||||
|
||||
#ifndef _VVortex_VX_wb_inter_H_
|
||||
#define _VVortex_VX_wb_inter_H_
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
class VVortex__Syms;
|
||||
|
||||
//----------
|
||||
|
||||
VL_MODULE(VVortex_VX_wb_inter) {
|
||||
public:
|
||||
|
||||
// PORTS
|
||||
|
||||
// LOCAL SIGNALS
|
||||
// Begin mtask footprint all:
|
||||
VL_SIGW(write_data,127,0,4);
|
||||
|
||||
// LOCAL VARIABLES
|
||||
|
||||
// INTERNAL VARIABLES
|
||||
private:
|
||||
VVortex__Syms* __VlSymsp; // Symbol table
|
||||
public:
|
||||
|
||||
// PARAMETERS
|
||||
|
||||
// CONSTRUCTORS
|
||||
private:
|
||||
VL_UNCOPYABLE(VVortex_VX_wb_inter); ///< Copying not allowed
|
||||
public:
|
||||
VVortex_VX_wb_inter(const char* name="TOP");
|
||||
~VVortex_VX_wb_inter();
|
||||
|
||||
// API METHODS
|
||||
|
||||
// INTERNAL METHODS
|
||||
void __Vconfigure(VVortex__Syms* symsp, bool first);
|
||||
private:
|
||||
void _ctor_var_reset() VL_ATTR_COLD;
|
||||
} VL_ATTR_ALIGNED(128);
|
||||
|
||||
#endif // guard
|
||||
Binary file not shown.
@@ -2,4 +2,10 @@
|
||||
#define VL_INCLUDE_OPT include
|
||||
#include "VVortex.cpp"
|
||||
#include "VVortex___024unit.cpp"
|
||||
#include "VVortex_VX_inst_meta_inter.cpp"
|
||||
#include "VVortex_VX_frE_to_bckE_req_inter.cpp"
|
||||
#include "VVortex_VX_mem_req_inter.cpp"
|
||||
#include "VVortex_VX_inst_mem_wb_inter.cpp"
|
||||
#include "VVortex_VX_warp_ctl_inter.cpp"
|
||||
#include "VVortex_VX_wb_inter.cpp"
|
||||
#include "VVortex_VX_context_slave.cpp"
|
||||
|
||||
@@ -1,5 +1,11 @@
|
||||
VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
|
||||
VVortex__Syms.h VVortex___024unit.h VVortex_VX_context_slave.h \
|
||||
VVortex___024unit.cpp VVortex_VX_context_slave.cpp
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h VVortex__Syms.h \
|
||||
VVortex___024unit.h VVortex_VX_inst_meta_inter.h \
|
||||
VVortex_VX_frE_to_bckE_req_inter.h VVortex_VX_mem_req_inter.h \
|
||||
VVortex_VX_inst_mem_wb_inter.h VVortex_VX_warp_ctl_inter.h \
|
||||
VVortex_VX_wb_inter.h VVortex_VX_context_slave.h VVortex___024unit.cpp \
|
||||
VVortex_VX_inst_meta_inter.cpp VVortex_VX_frE_to_bckE_req_inter.cpp \
|
||||
VVortex_VX_mem_req_inter.cpp VVortex_VX_inst_mem_wb_inter.cpp \
|
||||
VVortex_VX_warp_ctl_inter.cpp VVortex_VX_wb_inter.cpp \
|
||||
VVortex_VX_context_slave.cpp
|
||||
|
||||
Binary file not shown.
@@ -1,4 +1,7 @@
|
||||
VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
|
||||
VVortex.h VVortex___024unit.h VVortex_VX_context_slave.h
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h VVortex.h \
|
||||
VVortex___024unit.h VVortex_VX_inst_meta_inter.h \
|
||||
VVortex_VX_frE_to_bckE_req_inter.h VVortex_VX_mem_req_inter.h \
|
||||
VVortex_VX_inst_mem_wb_inter.h VVortex_VX_warp_ctl_inter.h \
|
||||
VVortex_VX_wb_inter.h VVortex_VX_context_slave.h
|
||||
|
||||
Binary file not shown.
@@ -4,6 +4,12 @@
|
||||
#include "VVortex__Syms.h"
|
||||
#include "VVortex.h"
|
||||
#include "VVortex___024unit.h"
|
||||
#include "VVortex_VX_inst_meta_inter.h"
|
||||
#include "VVortex_VX_frE_to_bckE_req_inter.h"
|
||||
#include "VVortex_VX_mem_req_inter.h"
|
||||
#include "VVortex_VX_inst_mem_wb_inter.h"
|
||||
#include "VVortex_VX_warp_ctl_inter.h"
|
||||
#include "VVortex_VX_wb_inter.h"
|
||||
#include "VVortex_VX_context_slave.h"
|
||||
|
||||
// FUNCTIONS
|
||||
@@ -12,31 +18,49 @@ VVortex__Syms::VVortex__Syms(VVortex* topp, const char* namep)
|
||||
: __Vm_namep(namep)
|
||||
, __Vm_didInit(false)
|
||||
// Setup submodule names
|
||||
, TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[1].VX_Context_one"))
|
||||
, TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[2].VX_Context_one"))
|
||||
, TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[3].VX_Context_one"))
|
||||
, TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[4].VX_Context_one"))
|
||||
, TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[5].VX_Context_one"))
|
||||
, TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[6].VX_Context_one"))
|
||||
, TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk1[7].VX_Context_one"))
|
||||
, TOP__Vortex__DOT__VX_exe_mem_req (Verilated::catName(topp->name(),"Vortex.VX_exe_mem_req"))
|
||||
, TOP__Vortex__DOT__VX_frE_to_bckE_req (Verilated::catName(topp->name(),"Vortex.VX_frE_to_bckE_req"))
|
||||
, TOP__Vortex__DOT__VX_mem_wb (Verilated::catName(topp->name(),"Vortex.VX_mem_wb"))
|
||||
, TOP__Vortex__DOT__VX_warp_ctl (Verilated::catName(topp->name(),"Vortex.VX_warp_ctl"))
|
||||
, TOP__Vortex__DOT__VX_writeback_inter (Verilated::catName(topp->name(),"Vortex.VX_writeback_inter"))
|
||||
, TOP__Vortex__DOT__fe_inst_meta_fd (Verilated::catName(topp->name(),"Vortex.fe_inst_meta_fd"))
|
||||
, TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk2[1].VX_Context_one"))
|
||||
, TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk2[2].VX_Context_one"))
|
||||
, TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk2[3].VX_Context_one"))
|
||||
, TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk2[4].VX_Context_one"))
|
||||
, TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk2[5].VX_Context_one"))
|
||||
, TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk2[6].VX_Context_one"))
|
||||
, TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one (Verilated::catName(topp->name(),"Vortex.vx_decode.genblk2[7].VX_Context_one"))
|
||||
{
|
||||
// Pointer to top level
|
||||
TOPp = topp;
|
||||
// Setup each module's pointers to their submodules
|
||||
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one;
|
||||
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one;
|
||||
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one;
|
||||
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one;
|
||||
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one;
|
||||
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one;
|
||||
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one;
|
||||
TOPp->__PVT__Vortex__DOT__VX_exe_mem_req = &TOP__Vortex__DOT__VX_exe_mem_req;
|
||||
TOPp->__PVT__Vortex__DOT__VX_frE_to_bckE_req = &TOP__Vortex__DOT__VX_frE_to_bckE_req;
|
||||
TOPp->__PVT__Vortex__DOT__VX_mem_wb = &TOP__Vortex__DOT__VX_mem_wb;
|
||||
TOPp->__PVT__Vortex__DOT__VX_warp_ctl = &TOP__Vortex__DOT__VX_warp_ctl;
|
||||
TOPp->__PVT__Vortex__DOT__VX_writeback_inter = &TOP__Vortex__DOT__VX_writeback_inter;
|
||||
TOPp->__PVT__Vortex__DOT__fe_inst_meta_fd = &TOP__Vortex__DOT__fe_inst_meta_fd;
|
||||
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one;
|
||||
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one;
|
||||
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one;
|
||||
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one;
|
||||
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one;
|
||||
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one;
|
||||
TOPp->__PVT__Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one = &TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one;
|
||||
// Setup each module's pointer back to symbol table (for public functions)
|
||||
TOPp->__Vconfigure(this, true);
|
||||
TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one.__Vconfigure(this, true);
|
||||
TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||
TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||
TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||
TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||
TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||
TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||
TOP__Vortex__DOT__VX_exe_mem_req.__Vconfigure(this, true);
|
||||
TOP__Vortex__DOT__VX_frE_to_bckE_req.__Vconfigure(this, true);
|
||||
TOP__Vortex__DOT__VX_mem_wb.__Vconfigure(this, true);
|
||||
TOP__Vortex__DOT__VX_warp_ctl.__Vconfigure(this, true);
|
||||
TOP__Vortex__DOT__VX_writeback_inter.__Vconfigure(this, true);
|
||||
TOP__Vortex__DOT__fe_inst_meta_fd.__Vconfigure(this, true);
|
||||
TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one.__Vconfigure(this, true);
|
||||
TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||
TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||
TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||
TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||
TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||
TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one.__Vconfigure(this, false);
|
||||
}
|
||||
|
||||
@@ -1,7 +1,8 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Symbol table internal header
|
||||
//
|
||||
// Internal details; most calling programs do not need this header
|
||||
// Internal details; most calling programs do not need this header,
|
||||
// unless using verilator public meta comments.
|
||||
|
||||
#ifndef _VVortex__Syms_H_
|
||||
#define _VVortex__Syms_H_
|
||||
@@ -11,6 +12,12 @@
|
||||
// INCLUDE MODULE CLASSES
|
||||
#include "VVortex.h"
|
||||
#include "VVortex___024unit.h"
|
||||
#include "VVortex_VX_inst_meta_inter.h"
|
||||
#include "VVortex_VX_frE_to_bckE_req_inter.h"
|
||||
#include "VVortex_VX_mem_req_inter.h"
|
||||
#include "VVortex_VX_inst_mem_wb_inter.h"
|
||||
#include "VVortex_VX_warp_ctl_inter.h"
|
||||
#include "VVortex_VX_wb_inter.h"
|
||||
#include "VVortex_VX_context_slave.h"
|
||||
|
||||
// SYMS CLASS
|
||||
@@ -23,13 +30,19 @@ class VVortex__Syms : public VerilatedSyms {
|
||||
|
||||
// SUBCELL STATE
|
||||
VVortex* TOPp;
|
||||
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__1__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__2__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__3__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__4__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__5__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__6__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk1__BRA__7__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_mem_req_inter TOP__Vortex__DOT__VX_exe_mem_req;
|
||||
VVortex_VX_frE_to_bckE_req_inter TOP__Vortex__DOT__VX_frE_to_bckE_req;
|
||||
VVortex_VX_inst_mem_wb_inter TOP__Vortex__DOT__VX_mem_wb;
|
||||
VVortex_VX_warp_ctl_inter TOP__Vortex__DOT__VX_warp_ctl;
|
||||
VVortex_VX_wb_inter TOP__Vortex__DOT__VX_writeback_inter;
|
||||
VVortex_VX_inst_meta_inter TOP__Vortex__DOT__fe_inst_meta_fd;
|
||||
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__1__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__2__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__3__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__4__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__5__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__6__KET____DOT__VX_Context_one;
|
||||
VVortex_VX_context_slave TOP__Vortex__DOT__vx_decode__DOT__genblk2__BRA__7__KET____DOT__VX_Context_one;
|
||||
|
||||
// CREATORS
|
||||
VVortex__Syms(VVortex* topp, const char* namep);
|
||||
@@ -40,4 +53,4 @@ class VVortex__Syms : public VerilatedSyms {
|
||||
|
||||
} VL_ATTR_ALIGNED(64);
|
||||
|
||||
#endif // guard
|
||||
#endif // guard
|
||||
|
||||
@@ -39,7 +39,7 @@ VL_MODULE(VVortex___024unit) {
|
||||
// INTERNAL METHODS
|
||||
void __Vconfigure(VVortex__Syms* symsp, bool first);
|
||||
private:
|
||||
void _ctor_var_reset();
|
||||
void _ctor_var_reset() VL_ATTR_COLD;
|
||||
} VL_ATTR_ALIGNED(128);
|
||||
|
||||
#endif // guard
|
||||
|
||||
@@ -1 +1 @@
|
||||
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_context_slave.cpp obj_dir/VVortex_VX_context_slave.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex___024unit.cpp obj_dir/VVortex___024unit.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_context.v VX_context_slave.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_master_slave.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v buses.vh
|
||||
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex_VX_context_slave.cpp obj_dir/VVortex_VX_context_slave.h obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp obj_dir/VVortex_VX_frE_to_bckE_req_inter.h obj_dir/VVortex_VX_inst_mem_wb_inter.cpp obj_dir/VVortex_VX_inst_mem_wb_inter.h obj_dir/VVortex_VX_inst_meta_inter.cpp obj_dir/VVortex_VX_inst_meta_inter.h obj_dir/VVortex_VX_mem_req_inter.cpp obj_dir/VVortex_VX_mem_req_inter.h obj_dir/VVortex_VX_warp_ctl_inter.cpp obj_dir/VVortex_VX_warp_ctl_inter.h obj_dir/VVortex_VX_wb_inter.cpp obj_dir/VVortex_VX_wb_inter.h obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex___024unit.cpp obj_dir/VVortex___024unit.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin VX_alu.v VX_context.v VX_context_slave.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_generic_register.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_master_slave.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v buses.vh interfaces//VX_frE_to_bckE_req_inter.v interfaces//VX_inst_mem_wb_inter.v interfaces//VX_inst_meta_inter.v interfaces//VX_mem_req_inter.v interfaces//VX_warp_ctl_inter.v interfaces//VX_wb_inter.v
|
||||
|
||||
@@ -1,36 +1,55 @@
|
||||
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
|
||||
C "-Wall -cc Vortex.v --exe test_bench.cpp -CFLAGS -std=c++11"
|
||||
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
|
||||
C "--compiler gcc -Wall -cc Vortex.v -Iinterfaces/ --exe test_bench.cpp -CFLAGS -std=c++11"
|
||||
S 6746612 12892413243 1567548409 0 1567548409 0 "/usr/local/bin/verilator_bin"
|
||||
S 2785 1565236 1567474434 0 1567474434 0 "VX_alu.v"
|
||||
S 3553 1565237 1567474434 0 1567474434 0 "VX_context.v"
|
||||
S 4995 1565238 1567474434 0 1567474434 0 "VX_context_slave.v"
|
||||
S 3553 1572595 1567702966 0 1567702966 0 "VX_context.v"
|
||||
S 4995 1572594 1567702948 0 1567702948 0 "VX_context_slave.v"
|
||||
S 1699 1565239 1567474434 0 1567474434 0 "VX_csr_handler.v"
|
||||
S 5512 1565240 1567474434 0 1567474434 0 "VX_d_e_reg.v"
|
||||
S 17808 1565241 1567474434 0 1567474434 0 "VX_decode.v"
|
||||
S 6179 1572602 1567698562 0 1567698562 0 "VX_d_e_reg.v"
|
||||
S 18559 1572589 1567703138 0 1567703138 0 "VX_decode.v"
|
||||
S 1676 1565244 1567474434 0 1567474434 0 "VX_define.v"
|
||||
S 4267 1565245 1567474434 0 1567474434 0 "VX_e_m_reg.v"
|
||||
S 3692 1565246 1567474434 0 1567474434 0 "VX_execute.v"
|
||||
S 2537 1567951 1567541896 0 1567541896 0 "VX_f_d_reg.v"
|
||||
S 6742 1567193 1567540852 0 1567540852 0 "VX_fetch.v"
|
||||
S 6293 1565249 1567474434 0 1567474434 0 "VX_forwarding.v"
|
||||
S 1866 1565250 1567474434 0 1567474434 0 "VX_m_w_reg.v"
|
||||
S 4352 1565251 1567474434 0 1567474434 0 "VX_memory.v"
|
||||
S 1249 1565252 1567474434 0 1567474434 0 "VX_register_file.v"
|
||||
S 1655 1565253 1567474434 0 1567474434 0 "VX_register_file_master_slave.v"
|
||||
S 1599 1565254 1567474434 0 1567474434 0 "VX_register_file_slave.v"
|
||||
S 1782 1572383 1567725862 0 1567725862 0 "VX_e_m_reg.v"
|
||||
S 3753 1572381 1567704198 0 1567704198 0 "VX_execute.v"
|
||||
S 776 1572788 1567631138 0 1567631138 0 "VX_f_d_reg.v"
|
||||
S 6600 1571625 1567568548 0 1567568548 0 "VX_fetch.v"
|
||||
S 6318 1572489 1567703920 0 1567703920 0 "VX_forwarding.v"
|
||||
S 399 1565278 1567537322 0 1567537322 0 "VX_generic_register.v"
|
||||
S 1038 1572397 1567725842 0 1567725842 0 "VX_m_w_reg.v"
|
||||
S 2441 1572393 1567725910 0 1567725910 0 "VX_memory.v"
|
||||
S 1249 1572596 1567702894 0 1567702894 0 "VX_register_file.v"
|
||||
S 1655 1572598 1567702916 0 1567702916 0 "VX_register_file_master_slave.v"
|
||||
S 1599 1572597 1567702888 0 1567702888 0 "VX_register_file_slave.v"
|
||||
S 1915 1565256 1567474434 0 1567474434 0 "VX_warp.v"
|
||||
S 1568 1565257 1567474434 0 1567474434 0 "VX_writeback.v"
|
||||
S 19239 1565260 1567539986 0 1567539986 0 "Vortex.v"
|
||||
S 1335 1565265 1567540424 0 1567540424 0 "buses.vh"
|
||||
T 937657 1568790 1567541908 0 1567541908 0 "obj_dir/VVortex.cpp"
|
||||
T 33938 1568786 1567541908 0 1567541908 0 "obj_dir/VVortex.h"
|
||||
T 1814 1568896 1567541908 0 1567541908 0 "obj_dir/VVortex.mk"
|
||||
T 597541 1568856 1567541908 0 1567541908 0 "obj_dir/VVortex_VX_context_slave.cpp"
|
||||
T 19362 1568854 1567541908 0 1567541908 0 "obj_dir/VVortex_VX_context_slave.h"
|
||||
T 3699 1568785 1567541908 0 1567541908 0 "obj_dir/VVortex__Syms.cpp"
|
||||
T 1578 1568784 1567541908 0 1567541908 0 "obj_dir/VVortex__Syms.h"
|
||||
T 754 1568852 1567541908 0 1567541908 0 "obj_dir/VVortex___024unit.cpp"
|
||||
T 860 1568851 1567541908 0 1567541908 0 "obj_dir/VVortex___024unit.h"
|
||||
T 702 1569200 1567541908 0 1567541908 0 "obj_dir/VVortex__ver.d"
|
||||
T 0 0 1567541908 0 1567541908 0 "obj_dir/VVortex__verFiles.dat"
|
||||
T 1208 1568895 1567541908 0 1567541908 0 "obj_dir/VVortex_classes.mk"
|
||||
S 1368 1572593 1567702438 0 1567702438 0 "VX_writeback.v"
|
||||
S 9956 1572384 1567726302 0 1567726302 0 "Vortex.v"
|
||||
S 1356 1571954 1567552292 0 1567552292 0 "buses.vh"
|
||||
S 1689 1571958 1567565366 0 1567565366 0 "interfaces//VX_frE_to_bckE_req_inter.v"
|
||||
S 789 1572399 1567724612 0 1567724612 0 "interfaces//VX_inst_mem_wb_inter.v"
|
||||
S 444 1571666 1567552516 0 1567552516 0 "interfaces//VX_inst_meta_inter.v"
|
||||
S 995 1572568 1567701364 0 1567701364 0 "interfaces//VX_mem_req_inter.v"
|
||||
S 603 1571976 1567568452 0 1567568452 0 "interfaces//VX_warp_ctl_inter.v"
|
||||
S 450 1572588 1567702406 0 1567702406 0 "interfaces//VX_wb_inter.v"
|
||||
T 611319 1572409 1567726304 0 1567726304 0 "obj_dir/VVortex.cpp"
|
||||
T 20930 1572391 1567726304 0 1567726304 0 "obj_dir/VVortex.h"
|
||||
T 1791 1572466 1567726304 0 1567726304 0 "obj_dir/VVortex.mk"
|
||||
T 218860 1572451 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_context_slave.cpp"
|
||||
T 4606 1572450 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_context_slave.h"
|
||||
T 1131 1572441 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.cpp"
|
||||
T 1208 1572440 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_frE_to_bckE_req_inter.h"
|
||||
T 882 1572445 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.cpp"
|
||||
T 1008 1572444 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_inst_mem_wb_inter.h"
|
||||
T 863 1572402 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_inst_meta_inter.cpp"
|
||||
T 987 1572401 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_inst_meta_inter.h"
|
||||
T 883 1572443 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_mem_req_inter.cpp"
|
||||
T 1005 1572442 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_mem_req_inter.h"
|
||||
T 900 1572447 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_warp_ctl_inter.cpp"
|
||||
T 1017 1572446 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_warp_ctl_inter.h"
|
||||
T 819 1572449 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_wb_inter.cpp"
|
||||
T 954 1572448 1567726304 0 1567726304 0 "obj_dir/VVortex_VX_wb_inter.h"
|
||||
T 5392 1572390 1567726304 0 1567726304 0 "obj_dir/VVortex__Syms.cpp"
|
||||
T 2283 1572389 1567726304 0 1567726304 0 "obj_dir/VVortex__Syms.h"
|
||||
T 754 1572398 1567726304 0 1567726304 0 "obj_dir/VVortex___024unit.cpp"
|
||||
T 873 1572396 1567726304 0 1567726304 0 "obj_dir/VVortex___024unit.h"
|
||||
T 1324 1572474 1567726304 0 1567726304 0 "obj_dir/VVortex__ver.d"
|
||||
T 0 0 1567726304 0 1567726304 0 "obj_dir/VVortex__verFiles.dat"
|
||||
T 1472 1572465 1567726304 0 1567726304 0 "obj_dir/VVortex_classes.mk"
|
||||
|
||||
@@ -11,12 +11,20 @@ VM_COVERAGE = 0
|
||||
VM_THREADS = 0
|
||||
# Tracing output mode? 0/1 (from --trace)
|
||||
VM_TRACE = 0
|
||||
# Tracing threadeds output mode? 0/1 (from --trace-fst-thread)
|
||||
VM_TRACE_THREADED = 0
|
||||
|
||||
### Object file lists...
|
||||
# Generated module classes, fast-path, compile with highest optimization
|
||||
VM_CLASSES_FAST += \
|
||||
VVortex \
|
||||
VVortex___024unit \
|
||||
VVortex_VX_inst_meta_inter \
|
||||
VVortex_VX_frE_to_bckE_req_inter \
|
||||
VVortex_VX_mem_req_inter \
|
||||
VVortex_VX_inst_mem_wb_inter \
|
||||
VVortex_VX_warp_ctl_inter \
|
||||
VVortex_VX_wb_inter \
|
||||
VVortex_VX_context_slave \
|
||||
|
||||
# Generated module classes, non-fast-path, compile with low/medium optimization
|
||||
|
||||
@@ -1,4 +1,3 @@
|
||||
test_bench.o: ../test_bench.cpp ../test_bench.h ../VX_define.h ../ram.h \
|
||||
VVortex.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h
|
||||
VVortex.h /usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilatedos.h
|
||||
|
||||
Binary file not shown.
@@ -1,9 +1,8 @@
|
||||
verilated.o: \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.cpp \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_imp.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_syms.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_sym_props.h \
|
||||
/usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_config.h
|
||||
verilated.o: /usr/local/share/verilator/include/verilated.cpp \
|
||||
/usr/local/share/verilator/include/verilatedos.h \
|
||||
/usr/local/share/verilator/include/verilated_imp.h \
|
||||
/usr/local/share/verilator/include/verilated.h \
|
||||
/usr/local/share/verilator/include/verilated_heavy.h \
|
||||
/usr/local/share/verilator/include/verilated_syms.h \
|
||||
/usr/local/share/verilator/include/verilated_sym_props.h \
|
||||
/usr/local/share/verilator/include/verilated_config.h
|
||||
|
||||
Binary file not shown.
@@ -3,5 +3,5 @@
|
||||
# of forwarding stalls: 0
|
||||
# of branch stalls: 0
|
||||
# CPI: 1.01056
|
||||
# time to simulate: 6.95312e-310 milliseconds
|
||||
# time to simulate: 2.19224e-314 milliseconds
|
||||
# GRADE: Failed on test: 4294967295
|
||||
|
||||
@@ -355,9 +355,10 @@ bool Vortex::simulate(std::string file_to_simulate)
|
||||
// unsigned cycles;
|
||||
counter = 0;
|
||||
while (this->stop && ((counter < 5)))
|
||||
// while (this->stats_total_cycles <= 30)
|
||||
{
|
||||
|
||||
// std::cout << "************* Cycle: " << cycle << "\n";
|
||||
// std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
|
||||
istop = ibus_driver();
|
||||
// dstop = !dbus_driver();
|
||||
|
||||
|
||||
Reference in New Issue
Block a user