152 lines
4.5 KiB
Verilog
152 lines
4.5 KiB
Verilog
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`include "VX_define.v"
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module VX_fetch (
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input wire clk,
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input wire reset,
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input wire in_branch_dir,
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input wire in_freeze,
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input wire[31:0] in_branch_dest,
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input wire in_branch_stall,
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input wire in_fwd_stall,
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input wire in_branch_stall_exe,
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input wire in_clone_stall,
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input wire in_jal,
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input wire[31:0] in_jal_dest,
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input wire in_interrupt,
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input wire in_debug,
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input wire[31:0] in_instruction,
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input wire in_thread_mask[`NT_M1:0],
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input wire in_change_mask,
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input wire[`NW_M1:0] in_decode_warp_num,
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input wire[`NW_M1:0] in_memory_warp_num,
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input wire in_wspawn,
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input wire[31:0] in_wspawn_pc,
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input wire in_ebreak,
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output wire[31:0] out_instruction,
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output wire out_delay,
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output wire[`NW_M1:0] out_warp_num,
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output wire[31:0] out_curr_PC,
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output wire out_valid[`NT_M1:0],
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output wire out_ebreak
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);
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reg stall;
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reg[31:0] out_PC;
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reg[`NW_M1:0] warp_num;
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reg[`NW_M1:0] warp_state;
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initial begin
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warp_num = 0;
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warp_state = 0;
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end
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wire add_warp = in_wspawn && !in_ebreak && !in_clone_stall;
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wire remove_warp = in_ebreak && !in_wspawn && !in_clone_stall;
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always @(posedge clk or posedge reset) begin
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if (reset || (warp_num == warp_state) || remove_warp || add_warp) begin
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warp_num <= 0;
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end else begin
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warp_num <= warp_num + 1;
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end
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if (add_warp) begin
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// $display("Adding a new warp %h", warp_state);
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warp_state <= warp_state + 1;
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end else if (remove_warp) begin
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// $display("Removing a warp %h", warp_state);
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warp_state <= warp_state - 1;
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end
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end
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assign out_ebreak = (warp_state == 0) && in_ebreak;
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assign stall = in_clone_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || in_freeze || in_debug;
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wire warp_zero_change_mask = in_change_mask && (in_decode_warp_num == 0);
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wire warp_zero_jal = in_jal && (in_memory_warp_num == 0);
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wire warp_zero_branch = in_branch_dir && (in_memory_warp_num == 0);
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wire warp_zero_stall = stall || (warp_num == 1);
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wire warp_zero_wspawn = 0;
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wire[31:0] warp_zero_wspawn_pc = 32'h0;
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wire[31:0] warp_zero_pc;
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wire warp_zero_valid[`NT_M1:0];
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VX_warp VX_Warp_zero(
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.clk (clk),
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.reset (reset),
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.stall (warp_zero_stall),
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.in_thread_mask(in_thread_mask),
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.in_change_mask(warp_zero_change_mask),
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.in_jal (warp_zero_jal),
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.in_jal_dest (in_jal_dest),
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.in_branch_dir (warp_zero_branch),
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.in_branch_dest(in_branch_dest),
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.in_wspawn (warp_zero_wspawn),
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.in_wspawn_pc (warp_zero_wspawn_pc),
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.out_PC (warp_zero_pc),
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.out_valid (warp_zero_valid)
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);
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wire warp_one_change_mask = in_change_mask && (in_decode_warp_num == 1);
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wire warp_one_jal = in_jal && (in_memory_warp_num == 1);
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wire warp_one_branch = in_branch_dir && (in_memory_warp_num == 1);
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wire warp_one_stall = stall || (warp_num == 0);
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wire[31:0] warp_one_pc;
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wire warp_one_valid[`NT_M1:0];
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VX_warp VX_Warp_one(
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.clk (clk),
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.reset (reset),
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.stall (warp_one_stall),
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.in_thread_mask(in_thread_mask),
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.in_change_mask(warp_one_change_mask),
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.in_jal (warp_one_jal),
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.in_jal_dest (in_jal_dest),
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.in_branch_dir (warp_one_branch),
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.in_branch_dest(in_branch_dest),
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.in_wspawn (in_wspawn),
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.in_wspawn_pc (in_wspawn_pc),
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.out_PC (warp_one_pc),
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.out_valid (warp_one_valid)
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);
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// always @(*) begin
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// if (in_wspawn) begin
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// $display("Spawning a warp @ %h",in_wspawn_pc);
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// end
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// end
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// always @(posedge clk) begin
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// $display("curr warp: %h Threads:%d%d PC: %h", warp_num, out_valid[0],out_valid[1], out_PC);
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// end
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// always @(*) begin
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// if (warp_num == 1) begin
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// $display("Going to PC: %h", warp_one_pc);
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// end
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// end
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assign out_PC = (warp_num == 0) ? warp_zero_pc : warp_one_pc;
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assign out_valid = (warp_num == 0) ? warp_zero_valid : warp_one_valid;
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// always @(*) begin
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// $display("FETCH PC: %h (%h, %h, %h)",delete, delete, in_jal_dest, in_branch_dest);
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// end
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assign out_curr_PC = out_PC;
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assign out_warp_num = warp_num;
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assign out_delay = 0;
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assign out_instruction = stall ? 32'b0 : in_instruction;
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endmodule |