felsabbagh3
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82ea79c680
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Fix for Single-Threaded
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2020-03-22 14:44:46 -07:00 |
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wgulian3
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e9cdc6e5af
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SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
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2020-01-24 06:10:24 -05:00 |
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felsabbagh3
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bbb2373919
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Intrinsics: tests for TMC+Control Divergence
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2019-11-01 21:53:37 -04:00 |
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felsabbagh3
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28ee1d3c36
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Sucess Synthesis - Finding db
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2019-10-28 13:52:49 -04:00 |
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felsabbagh3
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88eab9e746
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Removed dependancy on
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2019-10-27 22:30:32 -04:00 |
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felsabbagh3
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1181af1df2
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Modelsim basic sim
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2019-10-26 00:34:57 -04:00 |
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felsabbagh3
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1bfafca896
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Cleanup before integration
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2019-10-22 03:03:17 -04:00 |
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felsabbagh3
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b3f464dd89
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Barriers impl + tested
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2019-10-22 01:47:39 -04:00 |
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felsabbagh3
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31d3d51392
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WSPAWN imp + tested
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2019-10-21 23:35:53 -04:00 |
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felsabbagh3
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b6375e76de
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Readded IPDOM stack + SPLIT/Join tested
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2019-10-21 21:24:49 -04:00 |
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felsabbagh3
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bab1852a99
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Added Split/Join - not tested
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2019-10-21 03:03:15 -04:00 |
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felsabbagh3
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84f5ccb484
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Added CSR TID/WID reads
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2019-10-21 02:10:05 -04:00 |
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felsabbagh3
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f7d826593f
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TMC working and tested
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2019-10-18 16:09:06 -04:00 |
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felsabbagh3
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f7b55427b4
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Added ISA2 infrastructure with bugs
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2019-10-18 05:21:32 -04:00 |
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