59 lines
1.7 KiB
Verilog
59 lines
1.7 KiB
Verilog
module VX_gpgpu_inst (
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// Input
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VX_gpu_inst_req_inter VX_gpu_inst_req,
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// Output
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VX_warp_ctl_inter VX_warp_ctl
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);
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wire[`NT_M1:0] tmc_new_mask;
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genvar curr_t;
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for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1)
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begin
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assign tmc_new_mask[curr_t] = curr_t < VX_gpu_inst_req.a_reg_data[0];
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end
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wire valid_inst = (|VX_gpu_inst_req.valid);
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assign VX_warp_ctl.warp_num = VX_gpu_inst_req.warp_num;
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assign VX_warp_ctl.change_mask = (VX_gpu_inst_req.is_tmc || VX_gpu_inst_req.is_split) && valid_inst;
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assign VX_warp_ctl.thread_mask = VX_gpu_inst_req.is_tmc ? tmc_new_mask : 0;
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assign VX_warp_ctl.ebreak = (VX_gpu_inst_req.a_reg_data[0] == 0) && valid_inst;
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assign VX_warp_ctl.wspawn = 0;
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assign VX_warp_ctl.wspawn_pc = 0;
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wire[`NT_M1:0] split_new_use_mask;
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wire[`NT_M1:0] split_new_later_mask;
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// VX_gpu_inst_req.pc
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genvar curr_s_t;
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for (curr_s_t = 0; curr_s_t < `NT; curr_s_t=curr_s_t+1) begin
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wire curr_bool = (VX_gpu_inst_req.a_reg_data == 32'b1);
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assign split_new_use_mask[curr_s_t] = VX_gpu_inst_req.valid[curr_s_t] & (curr_bool);
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assign split_new_later_mask[curr_s_t] = VX_gpu_inst_req.valid[curr_s_t] & (!curr_bool);
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end
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reg[$clog2(`NT)-1:0] num_valids;
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integer z;
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always @(*) begin
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num_valids = 0;
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for (z = 0; z < `NT; z=z+1) begin
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if (VX_gpu_inst_req.valid) num_valids = num_valids + 1
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end
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end
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assign VX_warp_ctl.is_split = (VX_gpu_inst_req.is_split) && (num_valids > 1);
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assign VX_warp_ctl.split_new_mask = split_new_use_mask;
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assign VX_warp_ctl.split_later_mask = split_new_later_mask;
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assign VX_warp_ctl.split_save_pc = VX_gpu_inst_req.pc_next;
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// VX_gpu_inst_req.is_wspawn
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// VX_gpu_inst_req.is_split
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// VX_gpu_inst_req.is_barrier
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endmodule |