Commit Graph

134 Commits

Author SHA1 Message Date
Lyons, Ethan Tyler
1c21110ffe Add files via upload
ICache_In_Place
2019-11-08 10:56:11 -05:00
Lyons, Ethan Tyler
6c4cd2468f Add files via upload
ICache_In_Place
2019-11-08 10:55:35 -05:00
Lyons, Ethan Tyler
b0f685c2e2 Add files via upload
ICache_In_Place
2019-11-08 10:55:08 -05:00
felsabbagh3
5d5ad9c4ec FIXED BUGS 2019-11-07 13:54:46 -05:00
felsabbagh3
58a9140f08 Before evict_wb_old removal 2019-11-07 13:27:38 -05:00
Savan Roshan
e4ee2a9cbd Parameterization working 2019-11-07 00:14:46 -05:00
felsabbagh3
9e2de897f0 Added simple_main 2019-11-07 00:10:06 -05:00
Savan Roshan
cb1bf65017 Parameterization working 2019-11-06 11:12:27 -05:00
Savan Roshan
3a71a2ebdb Fixed bugs in parameterization 2019-11-06 01:09:30 -05:00
Savan Roshan
8468e7d4d9 Added prefix DCACHE_ 2019-11-05 08:33:38 -05:00
Savan Roshan
1db160a289 Fixed parameterization 2019-11-04 14:32:02 -05:00
Savan Roshan
8264339853 Added Parameterization 2019-11-04 13:20:34 -05:00
felsabbagh3
a28a1c45c1 wsapwn tested - NOTE in vx_main.c 2019-11-03 20:56:07 -05:00
felsabbagh3
a39979a844 Fixed ASIC GPR warp number delay 2019-11-03 15:56:18 -05:00
felsabbagh3
bbb2373919 Intrinsics: tests for TMC+Control Divergence 2019-11-01 21:53:37 -04:00
Savan Roshan
2b9f6f3d0b Fixed eviction_wb 2019-11-01 00:39:02 -04:00
felsabbagh3
46b09028d0 Added runtime (kernel 2.0) 2019-10-30 23:40:01 -04:00
felsabbagh3
06e5f6df1d Init num cycles 2019-10-30 15:18:52 -04:00
felsabbagh3
7863175233 Set associative bank working 2019-10-30 14:57:20 -04:00
felsabbagh3
3b49b82c46 GPR ASIC Working 2019-10-29 23:20:16 -04:00
felsabbagh3
3caae2b88e Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2019-10-29 14:28:41 -04:00
felsabbagh3
4aa04e76e6 Simulate debug 2019-10-29 14:28:20 -04:00
Lingjun Zhu
b6558714ca Finished synthesis with all memory but no optimization 2019-10-28 16:18:11 -04:00
Lingjun Zhu
0b30b3a35f Resolved most connection error, expect QA of rf2_256x19_wm0 in VX_cache_data 2019-10-28 15:06:23 -04:00
felsabbagh3
7af6575b97 SYN=1 2019-10-28 13:57:01 -04:00
felsabbagh3
28ee1d3c36 Sucess Synthesis - Finding db 2019-10-28 13:52:49 -04:00
felsabbagh3
a8d063e9ad Synthesis Cleanup 1 2019-10-28 13:43:12 -04:00
felsabbagh3
88eab9e746 Removed dependancy on 2019-10-27 22:30:32 -04:00
felsabbagh3
1b7f28273b Removed -O3 from makefile 2019-10-27 20:34:32 -04:00
felsabbagh3
0ee74bc566 migrated 100% to modelsim 2019-10-27 20:08:44 -04:00
felsabbagh3
715982cca7 Modelsim Working + Simulating + dumping - Some bugs 2019-10-27 03:36:02 -04:00
felsabbagh3
372c81d90c Generate VCD with ModelSim 2019-10-26 19:35:21 -04:00
felsabbagh3
6fda88b68f Modelsim Makefile compile + simulate - DPI 2019-10-26 19:01:49 -04:00
felsabbagh3
ad46194d1b fixed width 2019-10-26 00:39:27 -04:00
felsabbagh3
1181af1df2 Modelsim basic sim 2019-10-26 00:34:57 -04:00
Elsabbagh
9110e8367e modelsim 2019-10-25 23:41:34 -04:00
felsabbagh3
667dbfbbe8 Trying icarus 2019-10-25 22:54:02 -04:00
felsabbagh3
820007ae80 NUM_REQ 2019-10-25 13:46:31 -04:00
felsabbagh3
c85c01e082 Parametized cache 2019-10-25 13:36:06 -04:00
felsabbagh3
89d0390965 CACHE FINALLY WORKING 2019-10-25 04:01:23 -04:00
felsabbagh3
01efe02e8b CACHE WORKING just needs lb/sb 2019-10-25 03:03:09 -04:00
felsabbagh3
1e648c5819 FIxed first circular issue 2019-10-24 10:38:04 -04:00
felsabbagh3
de8de00f6e Finished cache not tested 2019-10-23 19:07:26 -04:00
felsabbagh3
6340ffcc2a new cache states 2019-10-23 15:07:14 -04:00
felsabbagh3
1645a04b1d Fixed SM + added def SYN 2019-10-22 15:56:30 -04:00
felsabbagh3
9d8273afe4 Finished Cache Integration 2019-10-22 06:02:08 -04:00
felsabbagh3
b7af8c3f34 Integrated Shared Memory 2019-10-22 05:03:47 -04:00
felsabbagh3
1bfafca896 Cleanup before integration 2019-10-22 03:03:17 -04:00
felsabbagh3
b3f464dd89 Barriers impl + tested 2019-10-22 01:47:39 -04:00
felsabbagh3
31d3d51392 WSPAWN imp + tested 2019-10-21 23:35:53 -04:00