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Simulate debug

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This commit is contained in:
felsabbagh3
2019-10-29 14:28:20 -04:00
parent 557c987bb0
commit 4aa04e76e6
12 changed files with 242 additions and 33 deletions
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2
rtl/VX_define.v
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@@ -9,7 +9,7 @@
// Uncomment the below line if NW=1
// `define ONLY
`define SYN 1
// `define SYN 1
`define CACHE_NUM_BANKS 8

86
rtl/VX_gpr.v
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@@ -16,25 +16,43 @@ module VX_gpr (
wire write_enable;
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0));
`ifndef SYN
// `ifndef SYN
byte_enabled_simple_dual_port_ram first_ram(
.we (write_enable),
.clk (clk),
.reset (reset),
.waddr (VX_writeback_inter.rd),
.raddr1(VX_gpr_read.rs1),
.raddr2(VX_gpr_read.rs2),
.be (VX_writeback_inter.wb_valid),
.wdata (VX_writeback_inter.write_data),
.q1 (out_a_reg_data),
.q2 (out_b_reg_data)
);
// byte_enabled_simple_dual_port_ram first_ram(
// .we (write_enable),
// .clk (clk),
// .reset (reset),
// .waddr (VX_writeback_inter.rd),
// .raddr1(VX_gpr_read.rs1),
// .raddr2(VX_gpr_read.rs2),
// .be (VX_writeback_inter.wb_valid),
// .wdata (VX_writeback_inter.write_data),
// .q1 (out_a_reg_data),
// .q2 (out_b_reg_data)
// );
// `else
wire writing_to_zero = (VX_writeback_inter.rd == 5'h0);
reg[31:0] use_before;
wire going_to_write = write_enable & (|VX_writeback_inter.wb_valid);
integer i;
always @(posedge clk) begin
if (reset) begin
use_before = 0;
end else if (going_to_write) begin
use_before[VX_writeback_inter.rd] = 1;
end
end
`else
wire[`NT_M1:0][31:0] write_bit_mask;
genvar curr_t;
@@ -43,7 +61,6 @@ module VX_gpr (
assign write_bit_mask[curr_t] = {32{~local_write}};
end
wire going_to_write = write_enable & (|VX_writeback_inter.wb_valid);
wire cenb = !going_to_write;
@@ -51,6 +68,33 @@ module VX_gpr (
wire cena_1 = (VX_gpr_read.rs1 == 0);
wire cena_2 = (VX_gpr_read.rs2 == 0);
wire[`NT_M1:0][31:0] temp_a;
wire[`NT_M1:0][31:0] temp_b;
`ifndef SYN
genvar thread;
genvar curr_bit;
for (thread = 0; thread < `NT; thread = thread + 1)
begin
for (curr_bit = 0; curr_bit < 32; curr_bit=curr_bit+1)
begin
assign out_a_reg_data[thread][curr_bit] = (temp_a[thread][curr_bit] === 1'dx) ? 1'b0 : temp_a[thread][curr_bit];
assign out_b_reg_data[thread][curr_bit] = (temp_b[thread][curr_bit] === 1'dx) ? 1'b0 : temp_b[thread][curr_bit];
end
end
`else
assign out_a_reg_data = (cena_1 | !use_before[VX_gpr_read.rs1]) ? 0 : temp_a;
assign out_b_reg_data = (cena_2 | !use_before[VX_gpr_read.rs2]) ? 0 : temp_b;
`endif
wire[`NT_M1:0][31:0] to_write = writing_to_zero ? 0 : VX_writeback_inter.write_data;
// wire cena_1 = 0;
// wire cena_2 = 0;
// wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
/* verilator lint_off PINCONNECTEMPTY */
rf2_32x128_wm1 first_ram (
@@ -59,7 +103,7 @@ module VX_gpr (
.CENYB(),
.WENYB(),
.AYB(),
.QA(out_a_reg_data),
.QA(temp_a),
.SOA(),
.SOB(),
.CLKA(clk),
@@ -69,7 +113,7 @@ module VX_gpr (
.CENB(cenb),
.WENB(write_bit_mask),
.AB(VX_writeback_inter.rd),
.DB(VX_writeback_inter.write_data),
.DB(to_write),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
@@ -98,7 +142,7 @@ module VX_gpr (
.CENYB(),
.WENYB(),
.AYB(),
.QA(out_b_reg_data),
.QA(temp_b),
.SOA(),
.SOB(),
.CLKA(clk),
@@ -108,7 +152,7 @@ module VX_gpr (
.CENB(cenb),
.WENB(write_bit_mask),
.AB(VX_writeback_inter.rd),
.DB(VX_writeback_inter.write_data),
.DB(to_write),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
@@ -129,6 +173,6 @@ module VX_gpr (
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
`endif
// `endif
endmodule

9
rtl/modelsim/Makefile
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@@ -73,13 +73,20 @@ SRC = \
../shared_memory/VX_bank_valids.v \
../shared_memory/VX_priority_encoder_sm.v \
../shared_memory/VX_shared_memory.v \
../shared_memory/VX_shared_memory_block.v
../shared_memory/VX_shared_memory_block.v \
../../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \
../../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \
../../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \
../../models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.v
# ../../models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
# vortex_dpi.h
CMD= \
-do "vcd file vortex.vcd; \
vcd add -r /vortex_tb/*; \
vcd add -r /vortex/*; \
run -all; \
quit -f"

2
rtl/modelsim/vortex_tb.v
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@@ -102,7 +102,7 @@ module vortex_tb (
if (out_ebreak) begin
gracefulExit();
$finish;
#20 $finish;
end
end