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Added runtime (kernel 2.0)

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This commit is contained in:
felsabbagh3
2019-10-30 23:40:01 -04:00
parent 06e5f6df1d
commit 46b09028d0
37 changed files with 569 additions and 3866 deletions
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2
rtl/VX_dmem_controller.v
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@@ -57,7 +57,7 @@ module VX_dmem_controller (
`ifdef SYN
.CACHE_WAYS(1),
`else
.CACHE_WAYS(4),
.CACHE_WAYS(2),
`endif
.CACHE_BLOCK(128), // Bytes
.CACHE_BANKS(8),

126
rtl/icarus/Makefile
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@@ -1,126 +0,0 @@
###############################################################################
#
# ICARUS VERILOG & GTKWAVE MAKEFILE
# MADE BY WILLIAM GIBB FOR HACDC
# williamgibb@gmail.com
#
# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE
# "make check" - compiles your verilog design - good for checking code
# "make simulate" - compiles your design+TB & simulates your design
# "make display" - compiles, simulates and displays waveforms
#
###############################################################################
#
# CHANGE THESE THREE LINES FOR YOUR DESIGN
#
#TOOL INPUT
SRC = \
vortex_tb.v \
../VX_define.v \
../interfaces/VX_branch_response_inter.v \
../interfaces/VX_csr_req_inter.v \
../interfaces/VX_csr_wb_inter.v \
../interfaces/VX_dcache_request_inter.v \
../interfaces/VX_dcache_response_inter.v \
../interfaces/VX_dram_req_rsp_inter.v \
../interfaces/VX_exec_unit_req_inter.v \
../interfaces/VX_frE_to_bckE_req_inter.v \
../interfaces/VX_gpr_clone_inter.v \
../interfaces/VX_gpr_data_inter.v \
../interfaces/VX_gpr_jal_inter.v \
../interfaces/VX_gpr_read_inter.v \
../interfaces/VX_gpr_wspawn_inter.v \
../interfaces/VX_gpu_inst_req_inter.v \
../interfaces/VX_icache_request_inter.v \
../interfaces/VX_icache_response_inter.v \
../interfaces/VX_inst_exec_wb_inter.v \
../interfaces/VX_inst_mem_wb_inter.v \
../interfaces/VX_inst_meta_inter.v \
../interfaces/VX_jal_response_inter.v \
../interfaces/VX_join_inter.v \
../interfaces/VX_lsu_req_inter.v \
../interfaces/VX_mem_req_inter.v \
../interfaces/VX_mw_wb_inter.v \
../interfaces/VX_warp_ctl_inter.v \
../interfaces/VX_wb_inter.v \
../interfaces/VX_wstall_inter.v \
../VX_alu.v \
../VX_back_end.v \
../VX_csr_handler.v \
../VX_csr_wrapper.v \
../VX_decode.v \
../VX_dmem_controller.v \
../VX_execute_unit.v \
../VX_fetch.v \
../VX_front_end.v \
../VX_generic_priority_encoder.v \
../VX_generic_register.v \
../VX_generic_stack.v \
../VX_gpgpu_inst.v \
../VX_gpr.v \
../VX_gpr_stage.v \
../VX_gpr_wrapper.v \
../VX_inst_multiplex.v \
../VX_lsu.v \
../VX_lsu_addr_gen.v \
../VX_one_counter.v \
../VX_priority_encoder.v \
../VX_priority_encoder_w_mask.v \
../VX_rename.v \
../VX_scheduler.v \
../VX_warp.v \
../VX_warp_scheduler.v \
../VX_writeback.v \
../Vortex.v \
../byte_enabled_simple_dual_port_ram.v \
../cache/VX_Cache_Bank.v \
../cache/VX_Cache_Block_DM.v \
../cache/VX_cache_bank_valid.v \
../cache/VX_cache_data.v \
../cache/VX_d_cache.v \
../cache/VX_d_cache_encapsulate.v \
../cache/VX_d_cache_tb.v \
../cache/VX_generic_pe.v \
../cache/bank.v \
../cache/cache_set.v \
../pipe_regs/VX_d_e_reg.v \
../pipe_regs/VX_f_d_reg.v \
../shared_memory/VX_bank_valids.v \
../shared_memory/VX_priority_encoder_sm.v \
../shared_memory/VX_set_bit.v \
../shared_memory/VX_shared_memory.v \
../shared_memory/VX_shared_memory_block.v
TESTBENCH = vortex_tb.v
TBOUTPUT = waves.lxt #THIS NEEDS TO MATCH THE OUTPUT FILE
#FROM YOUR TESTBENCH
###############################################################################
# BE CAREFUL WHEN CHANGING ITEMS BELOW THIS LINE
###############################################################################
#TOOLS
COMPILER = iverilog
SIMULATOR = vvp
VIEWER = gtkwave
#TOOL OPTIONS
COFLAGS = -v -o
SFLAGS = -v
SOUTPUT = -lxt #SIMULATOR OUTPUT TYPE
#TOOL OUTPUT
COUTPUT = compiler.out #COMPILER OUTPUT
###############################################################################
#MAKE DIRECTIVES
check : $(TESTBENCH) $(SRC)
$(COMPILER) -g2012 -o vortex $(SRC) -I../ -I.
simulate: $(COUTPUT)
$(SIMULATOR) $(SFLAGS) $(COUTPUT) $(SOUTPUT)
display: $(TBOUTPUT)
$(VIEWER) $(TBOUTPUT) &
#MAKE DEPENDANCIES
$(TBOUTPUT): $(COUTPUT)
$(SIMULATOR) $(SOPTIONS) $(COUTPUT) $(SOUTPUT)
$(COUTPUT): $(TESTBENCH) $(SRC)
$(COMPILER) $(COFLAGS) $(COUTPUT) $(TESTBENCH) $(SRC)

2
rtl/icarus/cmdfile
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@@ -1,2 +0,0 @@

57
rtl/icarus/vortex_tb.v
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@@ -1,57 +0,0 @@
// `include "../VX_define.v"
// `include "../Vortex.v"
`timescale 1ns/1ps
module vortex_tb (
);
reg clk;
reg reset;
reg[31:0] icache_response_instruction;
reg[31:0] icache_request_pc_address;
// IO
reg io_valid;
reg[31:0] io_data;
// Req
reg [31:0] o_m_read_addr;
reg [31:0] o_m_evict_addr;
reg o_m_valid;
reg [31:0] o_m_writedata[8 - 1:0][4-1:0];
reg o_m_read_or_write;
// Rsp
reg [31:0] i_m_readdata[8 - 1:0][4-1:0];
reg i_m_ready;
reg out_ebreak;
initial begin
while (!out_ebreak) begin
icache_response_instruction = 0;
end
end
Vortex vortex(
.clk (clk),
.reset (reset),
.icache_response_instruction(icache_response_instruction),
.icache_request_pc_address (icache_request_pc_address),
.io_valid (io_valid),
.io_data (io_data),
.o_m_read_addr (o_m_read_addr),
.o_m_evict_addr (o_m_evict_addr),
.o_m_valid (o_m_valid),
.o_m_writedata (o_m_writedata),
.o_m_read_or_write (o_m_read_or_write),
.i_m_readdata (i_m_readdata),
.i_m_ready (i_m_ready),
.out_ebreak (out_ebreak)
);
always @(clk) #5 clk <= ~clk;
endmodule

4
rtl/modelsim/Makefile
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@@ -109,8 +109,8 @@ comp:
sim: comp
vsim vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log
# vsim -novopt vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log
# vsim vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log
vsim -novopt vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log

8
rtl/modelsim/vortex_dpi.cpp
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@@ -17,7 +17,7 @@ extern "C" {
void ibus_driver (bool clk, unsigned pc_addr, unsigned * instruction);
void dbus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, svLogicVecVal * i_m_readdata, bool * i_m_ready);
void io_handler (bool clk, bool io_valid, unsigned io_data);
void gracefulExit();
void gracefulExit(int);
}
RAM ram;
@@ -50,11 +50,11 @@ void ibus_driver(bool clk, unsigned pc_addr, unsigned * instruction)
// printf("Inside ibus_driver\n");
if (clk)
{
num_cycles++;
(*instruction) = 0;
}
else
{
num_cycles++;
uint32_t curr_inst = 0;
curr_inst = 0xdeadbeef;
@@ -200,10 +200,10 @@ void io_handler(bool clk, bool io_valid, unsigned io_data)
}
}
void gracefulExit()
void gracefulExit(int cycles)
{
fprintf(stderr, "Num Cycles: %d\n", num_cycles);
fprintf(stderr, "\n*********************\n\n");
fprintf(stderr, "DPI Cycle Num: %d\tVerilog Cycle Num: %d\n", num_cycles, cycles);
}

24
rtl/modelsim/vortex_tb.v
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@@ -27,13 +27,13 @@ import "DPI-C" dbus_driver = function void dbus_driver( input logic clk,
import "DPI-C" io_handler = function void io_handler(input logic clk, input logic io_valid, input int io_data);
import "DPI-C" gracefulExit = function void gracefulExit();
import "DPI-C" gracefulExit = function void gracefulExit(input int cycle_num);
module vortex_tb (
);
reg[31:0] cycle_num;
int cycle_num;
reg clk;
reg reset;
@@ -61,7 +61,7 @@ module vortex_tb (
initial begin
// $fdumpfile("vortex1.vcd");
load_file("../../kernel/vortex_test.hex");
load_file("../../runtime/vortex_runtime.hex");
$dumpvars(0, vortex_tb);
reset = 1;
clk = 0;
@@ -87,13 +87,24 @@ module vortex_tb (
.out_ebreak (out_ebreak)
);
always @(*) begin
always @(negedge clk) begin
ibus_driver(clk, icache_request_pc_address, icache_response_instruction);
dbus_driver(clk, o_m_read_addr, o_m_evict_addr, o_m_valid, o_m_writedata, o_m_read_or_write, i_m_readdata, i_m_ready);
io_handler (clk, io_valid, io_data);
end
always @(posedge clk) begin
if (out_ebreak) begin
gracefulExit(cycle_num);
#40 $finish;
end
end
always @(posedge clk) begin
cycle_num = cycle_num + 1;
end
always @(clk, posedge reset) begin
if (reset) begin
reset = 0;
@@ -102,11 +113,6 @@ module vortex_tb (
#5 clk <= ~clk;
if (out_ebreak) begin
gracefulExit();
#20 $finish;
end
end
endmodule