minor updates
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@@ -226,9 +226,7 @@ module VX_mem_unit # (
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.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
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.BANK_ADDR_OFFSET (`SBANK_ADDR_OFFSET)
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) smem (
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`SCOPE_BIND_VX_mem_unit_smem
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) smem (
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.clk (clk),
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.reset (scache_reset),
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4
hw/rtl/cache/VX_shared_mem.v
vendored
4
hw/rtl/cache/VX_shared_mem.v
vendored
@@ -26,9 +26,7 @@ module VX_shared_mem #(
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// bank offset from beginning of index range
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parameter BANK_ADDR_OFFSET = 0
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) (
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`SCOPE_IO_VX_cache
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) (
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input wire clk,
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input wire reset,
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@@ -60,7 +60,6 @@
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"VX_gpu_unit": {},
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"VX_mem_unit": {
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"submodules": {
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"smem": {"type":"VX_cache", "enabled":"`SM_ENABLE", "params":{"NUM_BANKS":"`SNUM_BANKS"}},
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"dcache": {"type":"VX_cache", "params":{"NUM_BANKS":"`DNUM_BANKS"}},
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"icache": {"type":"VX_cache", "params":{"NUM_BANKS":"`INUM_BANKS"}}
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}
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@@ -203,7 +202,7 @@
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"!scoreboard_delay": 1,
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"!execute_delay": 1
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},
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"afu/vortex/l3cache/bank, afu/vortex/cluster/l2cache/bank, afu/vortex/cluster/core/mem_unit/dcache/bank, afu/vortex/cluster/core/mem_unit/icache/bank, afu/vortex/cluster/core/mem_unit/smem/bank": {
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"afu/vortex/l3cache/bank, afu/vortex/cluster/l2cache/bank, afu/vortex/cluster/core/mem_unit/dcache/bank, afu/vortex/cluster/core/mem_unit/icache/bank": {
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"?valid_st0": 1,
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"?valid_st1": 1,
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"addr_st0": 32,
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