diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v
index 14f1caa1..cac99407 100644
--- a/hw/rtl/VX_mem_unit.v
+++ b/hw/rtl/VX_mem_unit.v
@@ -226,9 +226,7 @@ module VX_mem_unit # (
             .CORE_TAG_WIDTH     (`DCORE_TAG_WIDTH),
             .CORE_TAG_ID_BITS   (`DCORE_TAG_ID_BITS),
             .BANK_ADDR_OFFSET   (`SBANK_ADDR_OFFSET)
-        ) smem (
-            `SCOPE_BIND_VX_mem_unit_smem
-            
+        ) smem (            
             .clk                (clk),
             .reset              (scache_reset),
 
diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.v
index 42b55308..2d851098 100644
--- a/hw/rtl/cache/VX_shared_mem.v
+++ b/hw/rtl/cache/VX_shared_mem.v
@@ -26,9 +26,7 @@ module VX_shared_mem #(
 
     // bank offset from beginning of index range
     parameter BANK_ADDR_OFFSET              = 0    
- ) (
-    `SCOPE_IO_VX_cache
-    
+ ) (    
     input wire clk,
     input wire reset,   
 
diff --git a/hw/scripts/scope.json b/hw/scripts/scope.json
index 63e1e130..86659ba4 100644
--- a/hw/scripts/scope.json
+++ b/hw/scripts/scope.json
@@ -60,7 +60,6 @@
         "VX_gpu_unit": {},
         "VX_mem_unit": {
             "submodules": {                
-                "smem":   {"type":"VX_cache", "enabled":"`SM_ENABLE", "params":{"NUM_BANKS":"`SNUM_BANKS"}},
                 "dcache": {"type":"VX_cache", "params":{"NUM_BANKS":"`DNUM_BANKS"}},
                 "icache": {"type":"VX_cache", "params":{"NUM_BANKS":"`INUM_BANKS"}}
             }
@@ -203,7 +202,7 @@
             "!scoreboard_delay": 1,        
             "!execute_delay": 1
         },   
-        "afu/vortex/l3cache/bank, afu/vortex/cluster/l2cache/bank, afu/vortex/cluster/core/mem_unit/dcache/bank, afu/vortex/cluster/core/mem_unit/icache/bank, afu/vortex/cluster/core/mem_unit/smem/bank": {
+        "afu/vortex/l3cache/bank, afu/vortex/cluster/l2cache/bank, afu/vortex/cluster/core/mem_unit/dcache/bank, afu/vortex/cluster/core/mem_unit/icache/bank": {
             "?valid_st0": 1,
             "?valid_st1": 1,
             "addr_st0": 32,