d97afcdfbc
bug using verilator, make the whitespace consistend in Makefrag-verilator, explicitly name the verilog sources to match vsim, and update verisim/Makefile to use the new source variable names
37 lines
1.4 KiB
Plaintext
37 lines
1.4 KiB
Plaintext
# Build and install our own Verilator, to work around versionining issues.
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VERILATOR_VERSION=3.920
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VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION)
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INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator)
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$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator
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$(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata
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touch $@
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$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile
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$(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin
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touch $@
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$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure
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mkdir -p $(dir $@)
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cd $(dir $@) && ./configure --prefix=$(abspath verilator/install)
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$(VERILATOR_SRCDIR)/configure: verilator/verilator-$(VERILATOR_VERSION).tar.gz
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rm -rf $(dir $@)
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mkdir -p $(dir $@)
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cat $^ | tar -xz --strip-components=1 -C $(dir $@)
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touch $@
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verilator/verilator-$(VERILATOR_VERSION).tar.gz:
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mkdir -p $(dir $@)
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wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@
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rocketchip_csrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/csrc
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# Run Verilator to produce a fast binary to emulate this circuit.
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VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
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VERILATOR_FLAGS := --top-module $(MODEL) \
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+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
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+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
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--output-split 20000 \
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-Wno-STMTDLY --x-assign unique \
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-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(rocketchip_csrc_dir)/verilator.h"
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