Howard Mao 9dc0abb485 explain how to add IceNet and TestChipIP hardware to design

2019-09-25 16:41:32 -07:00

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_static/images

add section on IceNet [ci skip]

2019-09-25 13:02:38 -07:00

Advanced-Usage

small clarifications + cleanup [skip ci]

2019-09-20 12:25:23 -07:00

Chipyard-Basics

small clarifications + cleanup [skip ci]

2019-09-20 12:25:23 -07:00

Customization

add quotes around core/tile [skip ci]

2019-09-20 18:00:11 -07:00

Generators

explain how to add IceNet and TestChipIP hardware to design

2019-09-25 16:41:32 -07:00

Simulation

Update naming in docs

2019-08-28 14:53:24 -07:00

TileLink-Diplomacy-Reference

move NodeTypes code to scala source

2019-09-16 10:25:10 -07:00

Tools

Add some documentation for dsptools et al

2019-08-02 23:21:59 -07:00

VLSI

grammer + spell check

2019-08-08 11:19:57 -07:00

.gitignore

[docs] gitignore build files

2019-09-08 15:45:21 -07:00

conf.py

rename to "Chipyard"

2019-06-23 22:47:23 -07:00

index.rst

add Google Group to the index

2019-09-12 18:14:39 -07:00

Makefile

rename to "Chipyard"

2019-06-23 22:47:23 -07:00

Quick-Start.rst

[docs] A couple spelling fixes in Quick Start

2019-09-08 21:37:02 -07:00

requirements.txt

readthedocs fix

2019-05-14 22:16:29 -07:00