Add some documentation for dsptools et al

docs/Tools/Chisel-Testers.rst

@@ -0,0 +1,6 @@
+Chisel Testers
+==============================
+
+`Chisel testers <https://github.com/freechipsproject/chisel-testers>`__ is a library for writing tests for Chisel designs.
+It provides a Scala API for interacting with a DUT.
+It can use multiple backends, including :ref:`Treadle` and Verilator.

docs/Tools/Dsptools.rst

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+Dsptools
+===============================
+
+`Dsptools <https://github.com/ucb-bar/dsptools/>`__ is a Chisel library for writing custom signal processing hardware.
+Additionally, dsptools is useful for integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC).
+
+Some features:
+
+* Complex type
+* Typeclasses for writing polymorphic hardware generators
+  * For example, write one FIR filter generator that works for real or complex inputs
+* Extensions to Chisel testers for fixed point and floating point types
+* A diplomatic implementation of AXI4-Stream
+* Models for verifying APB, AXI-4, and TileLink interfaces with chisel-testers
+* DSP building blocks

docs/Tools/Treadle.rst

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+Treadle
+==============================
+
+`Treadle <https://github.com/freechipsproject/treadle>`__ is a circuit simulator that directly executes FIRRTL.
+It is especially useful for interactive debugging and small unit tests that benefit from a low-overhead simulator.

docs/Tools/index.rst

@@ -10,5 +10,8 @@ The following pages will introduce them, and how we can use them in order to gen
 
    Chisel
    FIRRTL
+   Treadle
+   Chisel-Testers
+   Dsptools
    Barstools