Update naming in docs

docs/Advanced-Usage/DTM-Debugging.rst

@@ -16,12 +16,12 @@ This involves specifying the SoC top-level to add a DTM as well as configuring t
 .. code-block:: scala
 
     class DTMBoomConfig extends Config(
-      new WithDTMBoomRocketTop ++
+      new WithDTMTop ++
       new WithBootROM ++
       new WithJtagDTM ++
       new boom.common.SmallBoomConfig)
 
-In this example, the ``WithDTMBoomRocketTop`` mixin specifies that the top-level SoC will instantiate a DTM.
+In this example, the ``WithDTMTop`` mixin specifies that the top-level SoC will instantiate a DTM.
 The ``WithJtagDTM`` will configure that instantiated DTM to use JTAG as the bringup method (note: this can be removed if you want a DTM-only bringup).
 The rest of the mixins specify the rest of the system (cores, accelerators, etc).
 
@@ -36,7 +36,7 @@ After creating the config, call the ``make`` command like the following:
     # or
     cd sims/vcs
 
-    make CONFIG=DTMBoomConfig TOP=BoomRocketTopWithDTM MODEL=TestHarnessWithDTM
+    make CONFIG=DTMBoomConfig TOP=TopWithDTM MODEL=TestHarnessWithDTM
 
 In this example, this will use the config that you previously specified, as well as set the other parameters that are needed to satisfy the build system.
 After that point, you should have a JTAG enabled simulation that you can attach to using OpenOCD and GDB!

docs/Chipyard-Basics/Running-A-Simulation.rst

@@ -58,12 +58,6 @@ Therefore, in order to simulate a simple Rocket-based example system we can use:
 
     make SUB_PROJECT=example
 
-Alternatively, if we would like to simulate a simple BOOM-based example system we can use:
-
-.. code-block:: shell
-
-    make SUB_PROJECT=exampleboom
-
 Once the simulator has been constructed, we would like to run RISC-V programs on it.
 In the simulation directory, we will find an executable file called ``<...>-<package>-<config>``.
 We run this executable with our target RISC-V program as a command line argument in one of two ways.

docs/Customization/Heterogeneous-SoCs.rst

@@ -15,18 +15,18 @@ The following example shows a dual core BOOM with a single core Rocket.
 .. code-block:: scala
 
     class DualBoomAndOneRocketConfig extends Config(
-      new WithNormalBoomRocketTop ++
+      new WithTop ++
       new WithBootROM ++
       new boom.system.WithRenumberHarts ++
       new boom.common.WithRVC ++
-      new boom.common.DefaultBoomConfig ++
+      new boom.common.LargeBoomConfig ++
       new boom.system.WithNBoomCores(2) ++
       new freechips.rocketchip.subsystem.WithoutTLMonitors ++
       new freechips.rocketchip.subsystem.WithNBigCores(1) ++
       new freechips.rocketchip.system.BaseConfig)
 
 In this example, the ``WithNBoomCores`` and ``WithNBigCores`` mixins set up the default parameters for the multiple BOOM and Rocket cores, respectively.
-However, for BOOM, an extra mixin called ``DefaultBoomConfig`` is added to override the default parameters with a different set of more common default parameters.
+However, for BOOM, an extra mixin called ``LargeBoomConfig`` is added to override the default parameters with a different set of more common default parameters.
 This mixin applies to all BOOM cores in the system and changes the parameters for each.
 
 Great! Now you have a heterogeneous setup with BOOMs and Rockets.
@@ -62,7 +62,7 @@ Then you could use this new mixin like the following.
 .. code-block:: scala
 
     class SixCoreConfig extends Config(
-      new WithNormalBoomRocketTop ++
+      new WithTop ++
       new WithBootROM ++
       new WithHeterCoresSetup ++
       new freechips.rocketchip.system.BaseConfig)
@@ -78,12 +78,12 @@ An example of adding a Hwacha to all tiles in the system is below.
 .. code-block:: scala
 
     class DualBoomAndRocketWithHwachasConfig extends Config(
-      new WithNormalBoomRocketTop ++
+      new WithTop ++
       new WithBootROM ++
       new hwacha.DefaultHwachaConfig ++
       new boom.system.WithRenumberHarts ++
       new boom.common.WithRVC ++
-      new boom.common.DefaultBoomConfig ++
+      new boom.common.LargeBoomConfig ++
       new boom.system.WithNBoomCores(2) ++
       new freechips.rocketchip.subsystem.WithoutTLMonitors ++
       new freechips.rocketchip.subsystem.WithNBigCores(1) ++
@@ -103,14 +103,14 @@ An example is shown below with two BOOM cores, and one Rocket tile with a RoCC a
 .. code-block:: scala
 
     class DualBoomAndOneHwachaRocketConfig extends Config(
-      new WithNormalBoomRocketTop ++
+      new WithTop ++
       new WithBootROM ++
       new WithMultiRoCC ++
       new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket
       new boom.system.WithRenumberHarts(rocketFirst = true) ++
       new hwacha.DefaultHwachaConfig ++
       new boom.common.WithRVC ++
-      new boom.common.DefaultBoomConfig ++
+      new boom.common.LargeBoomConfig ++
       new boom.system.WithNBoomCores(2) ++
       new freechips.rocketchip.subsystem.WithoutTLMonitors ++
       new freechips.rocketchip.subsystem.WithNBigCores(1) ++

docs/Simulation/Software-RTL-Simulators.rst

@@ -12,16 +12,16 @@ The Chipyard framework can download, build, and execute simulations using Verila
 To run a simulation using Verilator, perform the following steps:
 
 To compile the example design, run ``make`` in the ``sims/verilator`` directory.
-This will elaborate the ``DefaultRocketConfig`` in the example project.
+This will elaborate the ``RocketConfig`` in the example project.
 
-An executable called ``simulator-example-DefaultRocketConfig`` will be produced.
+An executable called ``simulator-example-RocketConfig`` will be produced.
 This executable is a simulator that has been compiled based on the design that was built.
 You can then use this executable to run any compatible RV64 code.
 For instance, to run one of the riscv-tools assembly tests.
 
 .. code-block:: shell
 
-    ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
+    ./simulator-example-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
 
 If you later create your own project, you can use environment variables to build an alternate configuration.
 
@@ -50,16 +50,16 @@ To run a simulation using VCS, perform the following steps:
 Make sure that the VCS simulator is on your ``PATH``.
 
 To compile the example design, run make in the ``sims/vcs`` directory.
-This will elaborate the ``DefaultRocketConfig`` in the example project.
+This will elaborate the ``RocketConfig`` in the example project.
 
-An executable called ``simulator-example-DefaultRocketConfig`` will be produced.
+An executable called ``simulator-example-RocketConfig`` will be produced.
 This executable is a simulator that has been compiled based on the design that was built.
 You can then use this executable to run any compatible RV64 code.
 For instance, to run one of the riscv-tools assembly tests.
 
 .. code-block:: shell
 
-    ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
+    ./simulator-example-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
 
 If you later create your own project, you can use environment variables to build an alternate configuration.