Jerry Zhao
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e7f10348b0
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Merge remote-tracking branch 'origin/main' into clusters
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2023-12-15 16:46:51 -08:00 |
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-T.K.-
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e078fcba49
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REFACTOR: rename arty35t explicitly
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2023-12-04 01:54:59 -08:00 |
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Jerry Zhao
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3fa3d745b9
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Support breaking out ChipTop I/O out of the expected bundle type
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2023-10-30 21:25:11 -07:00 |
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Jerry Zhao
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a5597fd32f
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Support using HarnessBinders without IOBinders
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2023-10-25 11:49:16 -07:00 |
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Jerry Zhao
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1e26618e8d
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Fix fpga platforms cbus freq
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2023-10-21 15:48:01 -07:00 |
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Jerry Zhao
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eb3a0aecf4
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Add PortAPI between IO and Harness blocks
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2023-10-05 15:02:56 -07:00 |
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Jerry Zhao
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5495d05aa0
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Bump to latest rocket-chip
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2023-08-22 11:28:57 -07:00 |
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Jerry Zhao
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2077e4304d
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Explicitly provide refClockFreqMHz to harnessClockInstantiator
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2023-05-13 11:18:03 -07:00 |
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Jerry Zhao
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b8e95e0305
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Rename implicit clock/reset to referenceclock/reset
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2023-05-12 15:11:44 -07:00 |
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Jerry Zhao
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607c2b5a73
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Unify multi-node btw chipyard/firechip | unify harness clocking
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2023-05-12 08:41:34 -07:00 |
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Jerry Zhao
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64ad77bbcf
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Make FPGA flows use the harnessClockInstantiator
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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ac281daa78
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Move TestHarness to chipyard.harness, make chipyard/harness directory
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2023-05-08 08:00:56 -07:00 |
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Jerry Zhao
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e93bc3bed7
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Fix Arty FPGA reset harness binder
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2023-04-01 13:53:56 -07:00 |
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Jerry Zhao
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6abf970ccb
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Fix ArtyJTAG matching
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2023-04-01 10:23:22 -07:00 |
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Jerry Zhao
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df2e5ad9dc
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Bump to latest rocket-chip/chisel3.5.6
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2023-03-28 16:48:27 -07:00 |
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Jerry Zhao
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85fa9d1120
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Add ARTY100t bringup + TSI-over-UART
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2023-02-14 15:01:52 -08:00 |
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abejgonzalez
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292cc753ce
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Run pre-commit on all files
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2022-12-21 15:59:46 -08:00 |
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Abraham Gonzalez
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8e851b0285
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Merge pull request #1278 from Lorilandly/vc707fpga
Add support for VC707 FPGA board changelog:added
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2022-12-14 19:16:49 -08:00 |
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-T.K.-
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1b7457d2fc
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FIX: fix Arty FPGA reset signal (#1257)
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2022-12-07 19:34:35 -08:00 |
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Lori Li
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0724431873
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Clean up code
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2022-11-30 16:56:09 +09:00 |
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James Dunn
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8e59db02fd
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Merge pull request #968 from duyhieubui/master
Fixes UART portmap for Arty.
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2021-10-13 13:25:10 -07:00 |
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Jerry Zhao
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f668ffdb03
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Switch PRCI to HarnessBinder/IOBinders
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2021-09-29 11:39:52 -07:00 |
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Duy-Hieu Bui
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d9858c1dc8
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Fixes UART portmap for Arty.
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2021-09-03 05:02:36 +07:00 |
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Jerry Zhao
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ed2bfa8249
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Don't pass JTAG oe signal off-chip (#832)
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2021-03-24 01:08:46 -07:00 |
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abejgonzalez
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09ef82cabf
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Update harnessClk/Rst naming to buildtop | Small docs cleanup
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2021-03-22 13:11:12 -07:00 |
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abejgonzalez
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b797077334
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Fix Arty documentation link
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2020-12-27 22:00:06 -08:00 |
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abejgonzalez
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8f6de22e72
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Fixed TinyRocketConfig | Small cleanup to VCU118/Arty configs
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2020-11-23 16:30:39 -08:00 |
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abejgonzalez
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661a7701a7
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Share DigitalTop/ChipyardSystem | Fix small naming compile error
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2020-11-23 15:46:03 -08:00 |
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James Dunn
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95e8365105
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Small change to Arty reset binder name, per Jerry's PR comment.
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2020-11-18 16:53:37 -08:00 |
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Abraham Gonzalez
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5a4cad0172
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Merge pull request #6 from ucb-bar/local-fpga-support-docs
Local fpga support docs
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2020-11-06 21:03:15 -08:00 |
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James Dunn
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98fcea7b57
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Adding initial Arty documentation; will be expanded further.
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2020-11-06 17:25:05 -08:00 |
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abejgonzalez
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c721d897f3
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Point to SiFive license | Add require on Arty
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2020-11-06 10:18:10 -08:00 |
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abejgonzalez
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b0fc0457aa
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Use Chipyard configs as base (Arty)
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2020-11-05 20:46:03 -08:00 |
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abejgonzalez
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a281869041
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Fix Arty merge and errors from CY bump
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2020-11-05 15:04:44 -08:00 |
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abejgonzalez
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a7ab0dab59
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Updated VCU118 | Bumped naming on Arty
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2020-11-05 13:59:10 -08:00 |
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abejgonzalez
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3994bcecdf
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Merge remote-tracking branch 'secret/local-fpga-arty-harnessbinders' into local-fpga-support
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2020-11-05 11:08:36 -08:00 |
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abejgonzalez
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dda7622c29
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temp commit
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2020-10-14 14:49:22 -07:00 |
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James Dunn
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895dcd6831
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referencing fully qualified chipyard.harness.OverrideHarnessBinder to debug import issue.
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2020-10-11 11:12:33 -07:00 |
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James Dunn
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dca56cd858
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Removing redefinitions of HasHarnessSignalReferences and HasTestHarnessFunctions in TestHarness.scala.
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2020-10-10 19:55:02 -07:00 |
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James Dunn
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54acfe71fc
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Some HarnessBinder testing with Jerry's debug suggestions.
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2020-10-10 13:45:27 -07:00 |
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dunn
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7d1a1539e6
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Initial pass at HarnessBinders for Arty.
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2020-10-09 23:17:36 -07:00 |
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dunn
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252f9c6a12
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Beginning to modify Arty TestHarness to conform with HarnessBinders. Currently does not compile; debugging.
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2020-10-07 11:55:16 -07:00 |
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James Dunn
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afc085a5f4
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Removed AON block from E300 design. Debug over JTAG still functioning.
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2020-10-04 18:13:47 -07:00 |
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James Dunn
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9135cda959
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Bypassing AON for system.reset. Using reset_core in ArtyShell test harness, which is derived from Xilinx reset IP block's mb_reset. Changing dutReset to same reset_core.
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2020-09-17 13:43:28 -07:00 |
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abejgonzalez
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2580073d75
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Comment cleanup
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2020-09-07 15:30:21 -07:00 |
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abejgonzalez
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c49eef3224
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Small cleanup to CY DigitalTop | Move E300 configs to unique folder
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2020-09-07 15:26:30 -07:00 |
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abejgonzalez
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a8083aa570
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First pass at fpga-shells with IOBinders
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2020-09-07 11:48:27 -07:00 |
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abejgonzalez
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8eb807a2fd
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Use DigitalTop in Platform | Use Chipyard BootRom
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2020-09-04 18:56:32 -07:00 |
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abejgonzalez
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0656c5da4f
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First pass on using CY make system
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2020-09-03 20:29:19 -07:00 |
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James Dunn
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a8834c7766
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First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.
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2020-09-02 12:48:44 -07:00 |
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