joonho.whangbo
74998229fb
Add large boom cospike config
2024-02-05 23:17:26 -08:00
Jerry Zhao
45d74f6db2
Merge remote-tracking branch 'origin/main' into symmetric_sertl
2024-01-11 11:43:24 -08:00
Jerry Zhao
8073ecb1e8
Merge pull request #1697 from ucb-bar/clock_tap
...
Add debug clock tap port to all default designs
2024-01-11 11:38:20 -08:00
Jerry Zhao
d51a9a74d3
Merge remote-tracking branch 'origin/main' into clusters
2024-01-09 13:30:26 -08:00
-T.K.-
3eef3c36a6
Merge branch 'main' into clock_tap
2023-12-29 16:59:29 -08:00
Jerry Zhao
194d4462f9
Update testchipip with source-synchronous serdes
2023-12-21 20:33:24 -08:00
Jerry Zhao
1e5ebf192a
Update firesim/firechip with new testchipip packaging
2023-12-19 12:11:12 -08:00
Jerry Zhao
b02621db35
Merge remote-tracking branch 'origin/main' into clusters
2023-12-16 17:00:34 -08:00
Jerry Zhao
2f1012294d
Merge branch 'main' into clock_tap
2023-12-16 16:56:10 -08:00
Jerry Zhao
e7f10348b0
Merge remote-tracking branch 'origin/main' into clusters
2023-12-15 16:46:51 -08:00
Jerry Zhao
b37b6b0d9b
Remove clock tap from firesim designs
2023-12-15 15:51:04 -08:00
Jerry Zhao
30ac9dc2c8
Merge remote-tracking branch 'origin/main' into tcip-bump
2023-12-14 10:58:57 -08:00
Abraham Gonzalez
4132296831
Update TargetConfigs.scala
2023-11-15 16:49:19 -08:00
Jerry Zhao
a8766ea8fc
Precisely specify bus frequencies
2023-10-31 14:25:16 -07:00
Jerry Zhao
d83f395738
Update firechip for new testchipip
2023-10-24 18:42:27 -07:00
Jerry Zhao
a4be708771
Fix firechip cbus freq
2023-10-22 14:23:35 -07:00
Jerry Zhao
e6203bb25c
Fix fsim supernode memmodel
2023-10-05 23:56:29 -07:00
Jerry Zhao
eb3a0aecf4
Add PortAPI between IO and Harness blocks
2023-10-05 15:02:56 -07:00
Jerry Zhao
57ee757016
Remove MultiClockHarnessAXIMem
...
Previously, the MultiClockHarnessAXIMem stuff attached SimDRAM over the serial-tl link.
This was done to enable test-chip-like simulations, where the HarnessBinder/BridgeBinder
would effectively implement a similar system as what would go on the bringup platform.
Now that multi-chip-tops are supported, and co-simulation of the ChipTop and the BringupTop
are supported, we can remove all this old Harness-level stuff to reduce duplication
2023-09-16 09:47:47 -07:00
Jerry Zhao
563897ba22
Add WithUARTInitBaud/fix firesim uart configs
2023-06-19 06:03:56 -07:00
Jerry Zhao
1e3d4aad46
Update WithBackingScratchpad for firechip
2023-06-09 00:06:30 -07:00
Jerry Zhao
2f2cb1ac8b
Fix firesim clockgen to auto-generated the reference pll clock if not requested
2023-05-27 11:16:18 -07:00
Jerry Zhao
3f06dbc280
Fix clock group combiner behavior for rational-tile clocks
2023-05-26 17:50:55 -07:00
Jerry Zhao
f73951ac7f
Add TestChipConfigTweaks to model 2/1 tile/uncore division
2023-05-26 11:56:58 -07:00
Jerry Zhao
94d471bd9a
Set firesim harnessbinder freq to 1000 MHz by default
2023-05-12 14:44:07 -07:00
Jerry Zhao
607c2b5a73
Unify multi-node btw chipyard/firechip | unify harness clocking
2023-05-12 08:41:34 -07:00
Sagar Karandikar
abe8a7fb8b
remove extra newlines
2023-05-10 11:31:05 -07:00
Sagar Karandikar
95da9cefb5
4GB DRAM configs
2023-05-08 13:41:51 -07:00
Sagar Karandikar
40d0a1f3bd
low mem configs
2023-05-07 11:47:14 -07:00
Jerry Zhao
df2e5ad9dc
Bump to latest rocket-chip/chisel3.5.6
2023-03-28 16:48:27 -07:00
Sagar Karandikar
c14d11faac
lean gemmini tutorial ( #1413 )
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* lean gemmini tutorial
* bump firesim
* Update check-commit.sh
2023-03-22 20:26:26 -07:00
abejgonzalez
f4124e4cb6
Add Lean Gemmini FireChip target
2023-03-11 22:31:36 -08:00
abejgonzalez
a62c1f5010
Add a frag./config for MMIO only bridges
2023-03-09 20:09:46 -08:00
Jerry Zhao
9e7cdb6ccd
Remove Ringbus config from firechip
2023-02-11 15:48:16 -08:00
Tushar Sondhi
95f30d0411
add more minimal firesim configs for testing ( #1313 )
2023-01-19 14:02:47 -08:00
tsondhi
ace6c7f490
add minimal firesim configs for testing fpga sims
2023-01-04 23:21:34 +00:00
Sagar Karandikar
8c56a5fe3c
Merge pull request #1172 from ucb-bar/firesim-no-mem
...
firesim: Add a config with no mem port
2022-06-15 11:55:07 -07:00
David Biancolin
26dc18e878
firesim: Add a config with no mem port
2022-06-09 08:28:20 -07:00
Jerry Zhao
f8d83dddf5
Increase default SerialTL width to 32 ( #1040 )
2021-11-12 12:23:48 -08:00
Jerry Zhao
f668ffdb03
Switch PRCI to HarnessBinder/IOBinders
2021-09-29 11:39:52 -07:00
alonamid
610adfc3f7
address PR review comments
2021-06-03 22:23:17 -07:00
alonamid
f2b56072a1
remove crossings in single clock domain
2021-06-02 21:26:29 -07:00
alonamid
06b8cf84f9
update default firesim config freqs
2021-06-02 20:00:02 -07:00
alonamid
225cf9d29a
update frequency config fragements
2021-06-01 16:40:31 -07:00
alonamid
b99d6bb7ac
multiclock config multiple
2021-03-29 00:01:13 -07:00
alonamid
c93cd255ab
sane firesim default target freqs
2021-03-25 23:28:07 -07:00
abejgonzalez
5ffad327db
Bump testchipip
2021-03-21 15:34:01 -07:00
abejgonzalez
1e42113926
Splitting up FireSim default frequencies into a separate config frag.
2021-03-19 17:33:39 -07:00
abejgonzalez
6476c7e7f0
Small renaming/cleanup | Use LinkedHashMaps
2021-03-15 16:54:42 -07:00
Abraham Gonzalez
6ab8f8f8fc
Update FireSim to support harness clocks | Small config renaming
2021-03-08 22:03:07 +00:00
