abejgonzalez
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87e4090e38
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bump boom | correct error on first cmd in pipe
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2019-07-08 14:31:41 -07:00 |
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abejgonzalez
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ef1620b753
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update verilator.mk to support different install location
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2019-07-06 15:13:37 -07:00 |
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David Biancolin
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473bc0aa4e
|
Comment out FireChip make variables for now
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2019-06-28 23:54:08 +00:00 |
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David Biancolin
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1f48e33be5
|
Bump FireSim, and add back the firrtl intrp lib dep
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2019-06-28 19:16:34 +00:00 |
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David Biancolin
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f65d5d57d6
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Bump FireSim
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2019-06-28 19:01:44 +00:00 |
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David Biancolin
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1bd9b08717
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Merge branch 'rebar-dev' of https://github.com/ucb-bar/project-template into firesim-integration
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2019-06-28 18:10:19 +00:00 |
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abejgonzalez
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4cca0ed57e
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bump verilator version
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2019-06-19 09:35:46 -07:00 |
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David Biancolin
|
d9a82e914c
|
Bump FireSim
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2019-05-29 22:29:24 +00:00 |
|
David Biancolin
|
0cb1608e2c
|
Bump FireSim
|
2019-05-29 15:34:56 +00:00 |
|
David Biancolin
|
baf7a6c30d
|
Bump FireSim
|
2019-05-29 00:50:40 +00:00 |
|
David Biancolin
|
c0d4e848ba
|
WIP
|
2019-05-27 22:53:05 +00:00 |
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abejgonzalez
|
cc0d33ee4d
|
updated permissive naming | small bugfix for vcd/vpd dumping
|
2019-05-20 17:19:46 -07:00 |
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abejgonzalez
|
30d54a6851
|
readme addition | pipe out output | renamed output files
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2019-05-20 17:12:22 -07:00 |
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abejgonzalez
|
65d6a900c3
|
rename output | helper rules to run binaries
|
2019-05-20 16:15:08 -07:00 |
|
Jerry Zhao
|
340ed90652
|
Remove permissive flag for verisim
|
2019-05-11 19:59:49 -07:00 |
|
Jerry Zhao
|
ca3678087c
|
Add verilator_install make target for CI purposes
|
2019-05-10 17:06:03 -07:00 |
|
Jerry Zhao
|
cf9ef97676
|
Fix verilator clean
|
2019-05-07 23:05:13 -07:00 |
|
Jerry Zhao
|
2f2243df40
|
Minor Makefile fixes
|
2019-05-07 21:56:50 -07:00 |
|
Jerry Zhao
|
b88937b8a0
|
Fix vcs tests for rocketchip and hwacha
|
2019-04-24 18:23:26 -07:00 |
|
abejgonzalez
|
4c3dc0889c
|
update make variable names | change hwacha to use its own generator
|
2019-04-24 00:43:44 -07:00 |
|
abejgonzalez
|
2bd70937cb
|
support verilator | rename build variable
|
2019-04-22 23:26:13 -07:00 |
|
abejgonzalez
|
e4aa81b2f8
|
fix make clean
|
2019-04-18 14:25:37 -07:00 |
|
abejgonzalez
|
7d887b212c
|
align rebar with tip of project-template master | fixes build issues
|
2019-04-17 16:02:44 -07:00 |
|
abejgonzalez
|
c364869563
|
default to .gitignoring all files in verisim/vsim | read verilator.mk
|
2019-03-12 14:39:15 -07:00 |
|
abejgonzalez
|
2c246af110
|
rename makefiles | move verilog rule to common.mk
|
2019-03-12 14:39:15 -07:00 |
|
abejgonzalez
|
82273107c1
|
makefile changes/split | add scripts
|
2019-03-12 14:39:15 -07:00 |
|
alonamid
|
2def0dfea7
|
change dir structure
|
2019-03-12 14:30:38 -07:00 |
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