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align rebar with tip of project-template master | fixes build issues

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abejgonzalez
2019-04-17 16:02:44 -07:00
parent 419d41239f
commit 7d887b212c
7 changed files with 24 additions and 41 deletions
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4
sims/verisim/Makefile
View File

@@ -56,7 +56,7 @@ $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
touch $@
@@ -64,7 +64,7 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name).debug
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
-o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
touch $@

3
sims/vsim/Makefile
View File

@@ -55,7 +55,8 @@ VCS_NONCC_OPTS = \
+v2k \
+vcs+lic+wait \
+vc+list \
-f $(sim_blackboxes) \
-f $(sim_top_blackboxes) \
-f $(sim_harness_blackboxes) \
-f $(sim_dotf) \
-sverilog \
+incdir+$(build_dir) \