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readme addition | pipe out output | renamed output files

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This commit is contained in:
abejgonzalez
2019-05-20 17:12:22 -07:00
parent 65d6a900c3
commit 30d54a6851
5 changed files with 15 additions and 4 deletions
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2
sims/verisim/Makefile
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@@ -84,7 +84,7 @@ $(sim_debug): $(model_mk_debug)
# helper rules to run simulator with debug
#########################################################################################
run-binary-debug: $(sim_debug)
$(sim_debug) $(SIM_FLAGS) -v$(long_name).vcd $(BINARY)
$(sim_debug) $(SIM_FLAGS) -v$(sim_out_name).vcd $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out
#########################################################################################
# create a verisim vpd rule

2
sims/vsim/Makefile
View File

@@ -90,7 +90,7 @@ $(sim_debug) : $(sim_vsrcs) $(sim_dotf)
# helper rules to run simulator with debug
#########################################################################################
run-binary-debug: $(sim_debug)
$(sim_debug) $(PERMISSIVEON) $(SIM_FLAGS) +vcdplusfile=$(long_name).vpd $(PERMISSIVEOFF) $(BINARY)
$(sim_debug) $(PERMISSIVEON) $(SIM_FLAGS) +vcdplusfile=$(sim_out_name).vpd $(PERMISSIVEOFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out
#########################################################################################
# create a vcs vpd rule